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AN ULTRALOW POWER RF RECEIVER BASED ON DOUBLEGATE CMOS (FINFET) TECHNOLOGY By JIANNING WANG Bachelor of Science Beijing University of Aeronautics & Astronautics Beijing, China 1997 Master of Science Beijing University of Aeronautics & Astronautics Beijing, China 2000 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY May, 2006 AN ULTRALOW POWER RF RECEIVER BASED ON DOUBLEGATE CMOS (FINFET) TECHNOLOGY Thesis Approved: Dr. Chris Hutchens Thesis Advisor Dr. Yumin Zhang Dr. Weili Zhang Dr. Jack Cartinhour Dr. Gordon Emslie Dean of the Graduate College ii ACKNOWLEDGMENTS The completion of this dissertation marks the end of my formal education. Throughout my life, there were numerous supports that are given to me unconditionally and lovingly. At this moment, I will take this opportunity to express my sincere gratitude to who have supported and loved me all along. To begin, I thank my parents for their deep love and full supports. Their caring always extends to the deepest of my heart. I would not be able to achieve this milestone of my life without them. Especially, I would like to express my deep appreciation to my wife, Beining Nie, who has accompanied and encouraged me in many aspects of my life these years. Her supports were the driving force for the writeup of this dissertation. Being in MixedSignal VLSI Lab has definitely been a lot of fun, and an unforgettable part of my experience. I learned as much in the MSVLSI Lab as I did in the classroom. I would like to thank all the past and present members of the MSVLSI Lab, especially Dr. Liu. He gave me a lot of supports in the lab. I’ll never forget all these labmates, Narendra, Venket, Vijay, Vanay, Barad, Srini, Vamsi, Henry, Lisa, and Shooi. I would also like to thank the faculty of the ECEN Department at OSU, especially Dr. Weili Zhang, and Dr. Jack Cartinghour of Electrical Engineering Technology for being on my Graduate Committee. In addition, I thank Space and Warfare iii (SPAWAR) Systems Center (formerly NRaD), San Diego, CA for its support of this project. Last and foremost, I would like to thank Dr. Chris Hutchens and Dr. Yumin Zhang. I appreciate all the opportunities and assistance they have provided me over the past three years. Their numerous guidance and advice have deeply enhanced my chances for success at OSU and my subsequent career and life. Thank you! iv TABLE OF CONTENTS Chapter Page CHAPTER 1.......................................................................................................................1 OBJECTIVE......................................................................................................................1 1.1 Motivation.....................................................................................................................1 1.2 Overview.......................................................................................................................1 CHAPTER 2.......................................................................................................................3 LOW POWER TECHNIQUES..........................................................................................3 2.1 Introduction...................................................................................................................3 2.2 Low Supply Voltage Technique...................................................................................3 2.1.1 Opportunities for Reduced Supply Voltage...........................................................4 2.2.2 Challenges for Low Power Supply........................................................................5 2.3 Subthreshold Operation Technique...............................................................................5 2.3.1 Fundamental of Subthreshold Operation...............................................................6 2.3.2 Advantages of Subthreshold Operation.................................................................8 2.3.3 The challenges of Subthreshold Operation............................................................9 CHAPTER 3.....................................................................................................................13 INTEGRATED INDUCTORS.........................................................................................13 3.1 Introduction.................................................................................................................13 3.2 Structure and Layout...................................................................................................13 3.3 Inductor Model and Parameterextraction Method.....................................................15 3.4 Results and Model Verification..................................................................................18 3.4.1 Series Inductance (Ls)..........................................................................................18 3.4.2 Series Resistance (Rs)..........................................................................................18 3.4.3 Series Capacitance (Cs).......................................................................................19 v 3.4.4 Model Verification...............................................................................................19 3.5 Conclusion..................................................................................................................23 CHAPTER 4.....................................................................................................................24 INTEGRATED VARACTOR..........................................................................................24 4.1 Introduction.................................................................................................................24 4.2 Structure and Layout...................................................................................................25 4.3 Model Parameter Extraction and Model Verification.................................................27 4.4 Layout Summary and Usage.......................................................................................32 4.4.1 Capacitance Calculation and Length choice.................................................33 4.4.2 Resistance Estimation...................................................................................34 4.4.3 Inductance Estimation...................................................................................35 4.5 Conclusion..................................................................................................................35 CHAPTER 5.....................................................................................................................37 FINFET TRANSISTORS AND MODELING.................................................................37 5.1 Introduction.................................................................................................................37 5.2 Performance of FinFET Transistors............................................................................40 5.2.1 DC Measurements................................................................................................41 5.2.2 AC Measurement.................................................................................................45 5.2.3 Noise Measurement.............................................................................................47 5.2.4 Capacitance Measurement...................................................................................47 5.3 FinFET Model.............................................................................................................48 5.3.1 FinFET SmallSignal Model................................................................................48 5.3.2 FinFET BSIMSOI Model....................................................................................54 5.3.3 FinFET Model Summary.....................................................................................54 5.4 Summary.....................................................................................................................56 CHAPTER 6.....................................................................................................................58 vi GPS RECEIVER DESIGN...............................................................................................58 6.1 Introduction.................................................................................................................58 6.2 GPS Receiver Architectures.......................................................................................59 6.2.1 Typical GPS Receiver Architectures...................................................................59 6.2.2 LowIF Architecture............................................................................................61 6.3 Receiver System Design.............................................................................................62 6.4 Receiver Implementation Requirements.....................................................................64 6.4.1 Noise Figure.........................................................................................................64 6.4.2 Phase Noise..........................................................................................................66 6.4.3 Summary..............................................................................................................68 CHAPTER 7.....................................................................................................................70 ULTRALOW POWER LOW NOISE AMPLIFIER (LNA) DESIGN...........................70 7.1 Introduction.................................................................................................................70 7.2 LNA Topology Choice...............................................................................................71 7.2.1 Commonsource LNA (CSLNA).........................................................................73 7.2.2 Commongate LNA (CGLNA)............................................................................78 7.2.3 Comparisons of CSLNA and CGLNA................................................................79 7.3 Circuit Design.............................................................................................................81 7.4 LNA Performance.......................................................................................................84 CHAPTER 8.....................................................................................................................89 MICROPOWER RF VOLTAGE CONTROLLED OSCILLATOR DESIGN...............89 8.1 Introduction.................................................................................................................89 8.2 Oscillators Fundamental.............................................................................................89 8.2.1 Feedback Oscillator Model..................................................................................89 8.2.2 OnePort Oscillator Model...................................................................................91 8.3 Oscillator Topology Comparison................................................................................92 vii 8.4 Oscillator Circuit Design............................................................................................97 8.4 VCO Performance.....................................................................................................100 CHAPTER 9...................................................................................................................104 ULTRALOW POWER MIXER DESIGN....................................................................104 9.1 Introduction...............................................................................................................104 9.2 Mixer Fundamentals.................................................................................................105 9.2.1 Conversion Gain................................................................................................105 9.2.2 SSB and DSB Noise Figure...............................................................................106 9.2.3 Isolation and Linearity.......................................................................................107 9.3 Mixer Topology Comparison....................................................................................107 9.3.1 Passive Mixer.....................................................................................................108 9.3.2 Active Mixer......................................................................................................109 9.4 Circuit Design...........................................................................................................111 9.5 Mixer Performance...................................................................................................113 CHAPTER 10.................................................................................................................116 CONCLUSIONS.............................................................................................................116 10.1 Research Summary.................................................................................................116 10.2 Future Work............................................................................................................122 APPENDIX A.................................................................................................................125 INTEGRATED DIFFERENTIAL INDUCTORS AND TRANSFORMERS................125 APPENDIX B.................................................................................................................128 FINFET BSIMSOI MODEL EXTRACTION................................................................128 APPENDIX C.................................................................................................................132 viii GATECHANNEL CAPACITANCE CHARACTERISTICS IN NANOSCALE FINFET........................................................................................................................................132 ix LIST OF FIGURES Figure Page Figure 2.1 Schematic of low power supply LO..................................................................5 Figure 2.2 gm/ID and fT for a modern CMOS 0.13um process[Pletcher, 2004 #78]..........11 Figure 2.3 Comparision of Tf with technology scaling[Pletcher, 2004 #78]..................11 Figure 3.1 (a) Structural parameters of an onchip spiral inductor, (b) Die photograph of the spiral inductor.............................................................................................................15 Figure 3.2 Crosssection of inductor.................................................................................15 Figure 3.3 Equivalent circuit for models: (a) with substrate, (b) without substrate, (c) equivalent circuit at low frequency...................................................................................16 Figure 3.4 (a) Measured (dot) and simulated (line) sparameter, n=2.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................20 Figure 3.4 (b) Measured inductance as a function of frequency. n=2.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................21 Figure 3.5 (a) Measured (dot) and simulated (line) sparameter, n=4.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................21 Figure 3.5 (b) Measured inductance as a function of frequency. n=4.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................21 Figure 3.6 Comparison between measurement data and model simulation......................22 Figure 3.7 Measured (dot) and simulated (line) sparameter, n=5.5, w=25um, s=3um, and IDOD=0.5.........................................................................................................................23 Figure 4.1 The crosssection of the single varactor..........................................................25 Figure 4.2 The micrograph of the varactor under test......................................................26 Figure 4.3 (a) Capacitance versus frequency and (b) quality factor versus frequency.....27 Figure 4.4 The equivalent varactor circuit........................................................................28 Figure 4.5 Capacitance versus length at VG=0V..............................................................28 Figure 4.6 Capacitance and Resistance change verse gate bias voltage as extracted from the varactor parametrics....................................................................................................30 Figure 4.7 L=0.8um Vg=0V symbol is measured data and line is the simulated.............31 Figure 4.8 L=1um Vg=0V symbol is measured data and line is the simulated...............32 Figure 4.9 Comparison of the measured (symbol) and simulated (solidline) CV characteristics for the L=0.8um and L=1um devices........................................................32 Figure 5.1 Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or: GAA structure); 5) Pigate MOSFET. [Park, 2001 #48]..........................................................................................................................................37 Figure 5.2 The possible Doublegate MOSFET orientations on silicon[Wong, 1997 #49]...........................................................................................................................................38 Figure 5.3 The 3D FinFET..............................................................................................39 x Figure 5.4 Scanning electron microscope picture of the cross section of FinFET (compliments of SPAWAR SC San Diego)......................................................................39 Figure 5.5 FinFET Process steps; from [Hisamoto, 2000 #45]........................................40 Figure 5.6 FinFET drain current versus drain voltage at various gate voltages...............41 Figure 5.7 FinFET drain current versus gate voltage with drain voltage equal 50mV.....42 Figure 5.8 FinFET drain current versus gate voltage with drain voltage equal 1.4V.......42 Figure 5.9 FinFET mg versus gate voltage with drain voltage equal 1.4V......................43 Figure 5.10 FinFET drain current versus gate voltage at various drain voltages............44 Figure 5.11 FinFET transistor power gain versus frequency (0.7V V Δ≈, VDS=1.2V).....45 Figure 5.12 FinFET transistor current gain versus frequency (0.7V V Δ≈, VDS=1.2V)...45 Figure 5.13 FinFET transistor current gain versus frequency (50VmV Δ≈, VDS=1.2V). 46 Figure 5.14 The low frequency noise of the FinFET for L=120nm, W=4.2um[Zhu, 2005 #77]..................................................................................................................................47 Figure 5.15 Equilibrium high frequency CV curve.........................................................48 Figure 5.16 The 3D FinFET. Tbox=400nm, Hfin=50nm, Tsi=20 nm.................................49 Figure 5.17 Die picture of the circuit with test frame.......................................................49 Figure 5.18 FinFET transistor characteristics (W=72 um, L=80 nm)..............................49 Figure 5.19 The FinFET smallsignal equivalent model..................................................51 Figure 5.20 Zero bias smallsignal equivalent model.......................................................51 Figure 5.21 Measured (dot) and modeled (line) Sparameters (Vgs=0.6V, Vds=1.2V)..53 Figure 5.22 Measured (dashed) and modeled (solid line) S21 (Vgs=0.6V, Vds=1.2V)....53 Figure 5.23 Measured (dot) and modeled (line) h21 (50VmV Δ≈, Vds=1.2V).................56 Figure 6.1 The GPS L1/L2 band signal spectrum[Ko, 2005 #88]....................................59 Figure 6.2 Dualconversion GPS receiver........................................................................60 Figure 6.3 Singleconversion GPS receiver......................................................................60 Figure 6.4 Block diagram of CMOS GPS receiver...........................................................61 Figure 6.5 The GPS band signal spectrum after downconverted to 2 MHz IF[Shaeffer, 1998 #86]..........................................................................................................................62 Figure 6.7 Cascaded stages of receiver system.................................................................63 Figure 6.8 Block diagram of the GPS receiver.................................................................64 Figure 6.9 Reciprocal mixing of the inband thermal noise and phase noise[Ko, 2005 #88]..................................................................................................................................67 Figure 7.1 Common LNA topologies. (a) Resistive termination, (b) 1/mg termination, (c) shuntseries feed back, and (d) inductive degeneration....................................................72 Figure 7.2 CSLNA Schematic Diagram...........................................................................73 Figure 7.3 MOSFET equivalent noise model...................................................................76 Figure 7.4 Smallsignal model for noise calculation of CSLNA......................................77 Figure 7.5 the CGLNA schematic diagram......................................................................78 Figure 7.6 gm/ID versus inversion coefficient curve..........................................................82 Figure 7.7 Proposed differential LNA schematic.............................................................83 xi Figure 7.8 Voltage gain of differential LNA....................................................................85 Figure 7.9 S12 of differential LNA...................................................................................85 Figure 7.10 S11 and S22 of LNA.....................................................................................86 Figure 7.11 Noise Figure of LNA.....................................................................................86 Figure 7.12 Stability measurement of LNA......................................................................87 Figure 7.13 1dB compression point measurement of LNA.............................................87 Figure 8.1 oscillator viewed as feedback system..............................................................90 Figure 8.2 Feedback model for oscillator with LC resonant tank.....................................91 Figure 8.3 LC tank............................................................................................................92 Figure 8.4 the typical crosscouple oscillator...................................................................93 Figure 8.5 The complementary crosscoupled oscillator..................................................94 Figure 8.6 The typical Colpitts oscillator.........................................................................95 Figure 8.7 The typical differential Colpitts oscillator.......................................................96 Figure 8.8 The differential Colpitts oscillator with currentswitching technique.............97 Figure 8.9 Inversion coefficient for L=80 nm FinFET transistor.....................................99 Figure 8.10 Micropower VCO schematics....................................................................101 Figure 8.11 Simulated tuning characteristics of the VCO..............................................102 Figure 8.12 Output LO signal magnitude versus frequency...........................................102 Figure 8.13 VCO Phase noise versus frequency............................................................103 Figure 9.1 The heterodyne receiver system with a mixer...............................................105 Figure 9.2 Simple doublebalanced passive mixer.........................................................108 Figure 9.3 A active doublebalanced mixer....................................................................110 Figure 9.4 Minimum supplyheadroom doublebalanced mixer....................................112 Figure 9.5 Conversion gain versus frequency.................................................................113 Figure 9.6 Noise figure versus frequency.......................................................................114 Figure 9.7 1dB compression point of mixer..................................................................114 Figure 10.1 The diagram of system simulation of GPS receiver frontend subblocking circuits............................................................................................................................117 Figure 10.8 A typical commonsource amplifier with inductor load..............................123 Figure A.1 Microstrip inductor physical layouts for differential inputs[Danesh, 2002 #33]. (a) Two asymmetric spiral conductors. (b) Symmetrical microstrip inductor................125 Figure A.2 (a) Lumped equivalentcircuit model of a microstrip inductor, and circuit equivalents for (b) singleended (port 2 grounded) and (c) differential excitation.........126 Figure A.3 The test structures of differential inductors and transformers[Long, 2000 #34]. (a) 1:1 transformer. (b) differential inductor. (c) Rabjon Balun. (d) 1:2.5 transformer..127 Figure C.1 The 3D FinFET structure.............................................................................132 Figure C.2 Scheme of capacitance measurements for FinFET.......................................133 Figure C.3 Equilibrium high frequency CV curve........................................................134 Figure C.4 (a) Potential profile and (b) band diagram of FinFET..................................136 xii xiii LIST OF TABLES Table Page Table 3.1 Extracted circuit model parameters..................................................................20 Table 4.1 Extracted parameter values for 200 finger (Wf = 5um) varactors for L equal 1 um and 0.8 um respectively..............................................................................................30 Table 5.1 Extracted Model Parameters.............................................................................52 Table 5.1 The modified FinFET BSIM3SOI model.........................................................55 Table 6.1 Signal degradation due to finite quantization in the ADC................................66 Table 6.2 Summary for GPS receiver frontend requirements.........................................68 Table 7.1 The comparison between CSLNA and CGLNA (“+” indicates better, “” indicates worse)................................................................................................................79 Table 7.2 Differential LNA passive components values..................................................84 Table 7.3 Differential LNA active components values....................................................84 Table 7.4 Ultralow power LNA performance summary..................................................88 Table 8.1 Onchip inductors specifications at 1.5 GHz....................................................98 Table 8.2 Device sizing and IC for oscillator transistor.................................................100 Table 8.3 Summary of VCO performance......................................................................103 Table 9.1 Active doublebalanced mixer performance summary...................................115 Table 10.1 Summary of GPS receiver frontend subblocking circuits of plan A..........119 Table 10.2 Summary of GPS receiver frontend subblocking circuits of plan B..........121 Table 10.3 Comparison of GPS receiver subblocking circuit performance..................122 xiv LIST OF DEFINITIONS Subthreshold region: include weak and moderate inversion Moderate inversion: Gatetosource voltage is close to threshold voltage. Weak inversion: Gatetosource voltage is far below threshold voltage. Inversion coefficient: parameter describing the transistor’s working region, for example, weak, moderate and strong inversion xv Chapter 1 Objective 1.1 Motivation In the past 40 years, many kinds of electronic circuits were developed at an amazing speed. The low power integrated circuit (IC) is one of the targets designers are pursuing. Among the applications of low power ICs, wireless RF transceivers are new emerging application that requires small size, low cost and low power. One of the most critical components in wireless transceiver is the wireless receiver. The objective of this research is to study and realize an ultralow power RF receiver based on doublegate CMOS (FinFET) technology. In this work, tradeoffs and strategies for low power receiver design are investigated. A low power global position system (GPS) receiver is taken as an example to test our study. 1.2 Overview This dissertation is organized as follows. Chapter 2 describes techniques for the design of analog circuits for low power. It focuses on the importance of moderate inversion usage in this design, which is the main method to reduce the power consumption of RF receiver. Chapter 3 and 4 focuses on the design, test and model integrated passive devices, such as inductors and varactors. Chapter 5 introduces a new doublegate CMOS architecture, FinFET. We characterized the FinFETs with IV, CV, 1 and Sparameter measurements at GHz frequency range. A BSIM3SOI model is developed for further implementation and validation of the FinFET transistor RF circuits in moderate inversion. Starting from Chapter 6, we apply the passive and active devices to the GPS receiver frontend circuit design. In Chapter 6, the GPS receiver’s architecture, system design and implementation requirement are described. Chapters 7 to 9 describe the GPS receiver frontend subblocks, such as ultralow power LNA, VCO and mixer design, respectively. The performances and trade offs of each building blocks are summarized at the end of each chapter. Chapter 10 concludes the dissertation with a brief summary of results and discussion of future research directions. 2 Chapter 2 Low Power Techniques 2.1 Introduction The silicon CMOS technology has become dominant in integrated circuits. CMOS gate lengths have reduced from 10um in the 1970’s to the present day geometries of less than 90 nm. According to the 2004 International Technology Roadmap for Semiconductors (ITRS), by 2006, MOS transistors with a physical gate length of 80 nm will become widely available. Its scalability provides decreased power consumption at enhanced performance levels. When the CMOS devices are scaled into the sub100nm dimension, the deep submicron CMOS opens up new frontiers in low voltage and current circuit design. In this chapter, design techniques are outlined first, and the advantages of modern CMOS devices are analyzed and the ultra low power consumption for RF front end circuits is investigated. 2.2 Low Supply Voltage Technique Conventional CMOS technology has, for over 3 decades, been locked into designing processes with high performance digital circuits as the objective. Analog/RF designers basically just used discrete solutions or hybrid blocks of bipolar GaAs, and more recently BiCMOS and Heterojunction Bipolar Transistors (HBT). Not only are digital device models not sufficient for the accurate circuit simulation, the analog/RF designer must face a constantly shrinking design space. One of the most difficult 3 problems is the constantly decreasing supply voltage for modern CMOS processes, causing reduced voltage headroom and dynamic range for analog and RF application [1]. 2.1.1 Opportunities for Reduced Supply Voltage Here a typical differential local oscillator (LO) is shown in Figure 2.1. It is an example capable of operating with a very low supply voltage. It contains two stacked transistors. The inductors comprising the resonant load do not consume additional voltage headroom, additionally the output is allowed to swing above the supply voltage, VDD. Theoretically, the LO may operate on a supply voltage as low as VDsat1+VDsat3, where VDsat is the MOSFET saturation voltage. Furthermore, if the devices M1 and M2 are designed to operate in the subthreshold regime, VGS and VDsat may be quite small. The main challenge in operating under a low VDD is the reduction in output voltage swing. Generally, system level considerations are critical when designing low voltage circuits and choosing the optimal power supply voltage. Supply voltage is not typically considered a variable parameter available to the designer, because it is impractical from an integration perspective if each component requires its own unique supply. However, it is entirely reasonable that two supply voltages will be available in a network environment: e.g. high voltage for active mode and low voltage for sleep mode. Recent research in low voltage digital design has shown that significant savings in memory leakage power may be achieved by reducing the supply to a few hundred mill volts during standby periods [2]. If a lower voltage supply is made available for use in digital standby mode, it may also be available for analog circuits [3]. 4 Figure 2.1 Schematic of low power supply LO. 2.2.2 Challenges for Low Power Supply For analogue circuits, downscaling supply voltage and process feature size will not automatically reduce power consumption and, in fact, usually it often has the opposite effect in analog design. In analogue chips, power is consumed to maintain the signal energy above the thermal noise floor in order to achieve the desired signaltonoise ratio or dynamic range. Since minimum power consumption is related to the ratio between supply voltages and signal amplitude, powerefficient analogue circuits should be designed to maximize the voltage swing. Reducing the supply voltage, while maintaining the signaltonoise ratio and bandwidth, therefore requires that the transconductance be increased. This is normally done at the expense of power or by reduced channel length. Therefore the approach for analogue designs must therefore be different. 2.3 Subthreshold Operation Technique 5 2.3.1 Fundamental of Subthreshold Operation For gatesource voltage (VGS) less than the extrapolated threshold voltage but high enough to create an inversion region at the surface of the silicon, the device operates in the subthreshold region. In this work, both weak and moderate inversion are considered as subthreshold operation even we know VtVGS may larger than Vt in moderate inversion. Later in this chapter we will point out this work is based on moderate inversion because of the bandwidth limitation. In subthreshold region, the channel charge is much less than the fixed charge in the depletion region and the drain current arising from the drift process is negligible. The drain current is caused by a gradient in minoritycarrier concentration, i.e. diffusion current. In subthreshold operation, the surface potential is approximately a linear function of the gatesource voltage [4]. Assume that the charge stored at the oxidesilicon interface is independent of the surface potential in the subthreshold region, and then changes in the surface potential sψΔare controlled by changes in the gatesource voltage through a voltage divider between the oxide capacitance and the depletionregion capacitanceGSVΔoxCjsC. Therefore, 1soxGSjsoxdCdVCCnψ=+ = (2.1) where n is called subthreshold slope factor and takes on a values from 1 to 2. The drain current equation in the subthreshold region is exp1expGStDSDtTTVVVWIILnUU⎡⎤⎛⎞⎛−=− ⎞ − ⎢⎥⎜⎟⎜ ⎟ ⎢⎥⎝⎠⎝ ⎠ ⎣⎦ (2.2) 6 where is the thermal voltage. is the gate to source threshold voltage. is intrinsic or specific current. TUtVtI 202toxInCUμ= T (2.3) Physically, represents the characteristic current for the device in the center of the moderate inversion region, providing a convenient normalization factor. The drain current of a given device may be normalized to, producing the inversion coefficient, tItIDtIICWIL= (2.4) The inversion coefficient provides a very useful way of identifying the operation region and level of inversion [5] of MOS transistors, 1IC<<: Weak inversion 1:IC≈Moderate inversion 1:IC>>Strong inversion Unlike in strong inversion, the minimum drainsource voltage required to force the transistor to operate as a current source in the subthreshold region is independent of the overdrive [4]. Calculating DGSIV∂∂from (2.4) and using (2.3) gives exp1exptGStDSoxDDmtTTTToxIVVVCIIWgLnUnUUnUUCC⎡⎤⎛⎞⎛⎞−=−−==⎢⎥⎜⎟⎜⎟+⎢⎥⎝⎠⎝⎠⎣⎦ js (2.5) The ratio of the transconductance to the current of an MOS transistor in subthreshold region is 1mDTgInU= (2.6) 7 The Equation above predicts that this ratio is independent of the overdrive, . For the transistor in the strong inversion, theVΔmDgIratios is 2mDgIV=Δ (2.7) where is the overdrive voltage. Comparing (2.6) to (2.7), we find the VΔmDgI of subthreshold region may 4 to 8 times higher than in strong inversion. 2.3.2 Advantages of Subthreshold Operation Motivated by the needs for low power narrowband wireless communication systems, the micropower RFIC frontend, a LNA combined with a downconversion mixer, has been designed using weak inversion CMOS techniques [6]. Within the active (saturation) region a device may be biased in the moderate or weak inversion region. The available transcondance per amp may 4 to 8 times higher than in strong inversion. This can be a big benefit for wireless applications where power consumption is much concerned if the bandwidth is available. The second advantage of subthreshold operation is the relatively low drain saturation voltage VDsat, which is typically around 3 to 4 UT (about 78mV) [7] at room temperatuer. More practically as a result of anticipated temperature variation VDsat, must be greater than 120mV. Compared with strong inversion, the value of VDsat in weak inversion is independence of gate voltage. The low saturation voltage implies that transistors operating in weak or moderate inversion require less overhead resulting in greater headroom than do devices in strong inversion. Therefore subthreshold operation is a natural choice for circuits operating with reduced supply voltage when the bandwidth is available. 8 The third advantage of subthreshold operation is low flicker noise achieved in moderate inversion since the flicker noise is reduced with less current flow [8, [9]. A detailed explanation follows in chapter 5. Finally, nonlinearity is not a problem. In subthreshold region the third order intercept point voltage () is approximately [10] 3IIPV (2.11) mVUVTIIP12010043−≈= If the system signal is much less than 100 mV we could ignore the effects os VIIP3. The second order intercept point voltage () is inversely proportion to input offset voltage () [10] 2IIPVosV ()OSTIIPVUV224= (2.12) For 80 nm FinFET the VOS is approximately 4.8 mV per square root of finger numbers [11]. For a 200 um device it has 2000 fingers. The VOS is calculated 0.1 V. Thus the VIIP2 is 25 V. Since for this work the amplitude of signal is on the order of microvolts, the effects of IP2 and IP3 could be ignored. 2.3.3 The challenges of Subthreshold Operation Although there are many advantages obtained in weak inversion region there are drawbacks as well. The first and obvious problem is the reduced bandwidth. Traditionally, transistors for high frequency applications are operated in strong inversion to take advantage of the high device transit frequency (Tf) in this regime. Transit frequency is defined as the frequency where the current gain of the device falls to unity and is normally given by: 9 ()2mTgsgdgfCCπ=+ (2.9) Since gm in weak or moderate inversion may be ten or more times smaller than that in strong inversion mode, Tf in the weak inversion is several orders of magnitude below that in the strong inversion although the Cgs in subthreshold may several times smaller than that in strong inversion shown in Figure 5.15 in Chapter 5. In the past, this speed limitation prohibits the applications in RF design. However, technology scaling is beginning to provide the solution since in the weak or moderate inversion, Tf is inversely proportional to the square of the channel length in (2.10) 2TVnUtToxIefLCΔ≈ (2.10) The present deep submicron CMOS technology makes this feasible. As shown in Figure 2.2 [3], the peak Tf is around 100GHz, decreasing sharply at lower inversion coefficient. At the center of moderate inversion, indicated by the vertical line at IC equal 1, Tf is approximately 5 GHz for the 130nm process. The bandwidth is adequate to implement circuits operating in the hundreds of MHz or above. In the Figure 2.3, device Tf is simulated across inversion level for three generations of submicron CMOS. At the center of moderate inversion, Tf is approximately 6 GHz for 180 nm, 12 GHz for 130 nm, and 21 GHz for 90 nm node. The current state of the art, 90nm CMOS device, can provide sufficient bandwidth for subthreshold circuits up to the low GHz range, such as GPS receiver front end which works at 1.5 GHz. From now on, we will only concentrate on the moderate inversion since it can provide enough bandwidth for low GHz application. 10 As a result the expected gm efficient improvement is only expected to be 2 to 4 greater than square law. Figure 2.2 gm/ID and fT for a modern CMOS 0.13um process [3]. Figure 2.3 Comparision of Tf with technology scaling [3]. In addition to the reduceTf, the current mismatch is another problem. In subthreshold region the drain current has an exponential relationship with the gate 11 voltage. As a result any small change in the gate to source voltage will have a larger change in drain current, which makes it unpredictable for the circuit. Fortunately, with the device area increase the current mismatch will decrease since [12] 22211.25SiISiTLWToxAkLWTToxfinΔ⎛⎞ΔΔΔΔ⎛⎞⎛⎞⎛⎞=±⋅+++⎜⎟⎜⎟⎜⎟⎜⎟⋅⎝⎠⎝⎠⎝⎠⎝⎠ 2 (2.10) Where IAΔ is the ratio of current mismatch. 12 Chapter 3 Integrated Inductors 3.1 Introduction The inductor is a key component in high RF frequency circuits. In the past a few years there was a great drive to improve the quality factor of integrated inductors so that a radioonchip system can be readily realized [13]. Bulk silicon inductors generally have peak Q’s of less than 10 with low selfresonant frequencies [14]. These values are typically not satisfactory for high performance, voltagecontrolled oscillator (VCO) designed to meet the stringent phase noise and low power constraints. In this chapter, the inductor structure and layout were discussed first. Then the inductor model and model parameters extraction methods were presented. Finally, the model simulation results were compared with the measurement for some typical inductor and the conclusion was drawn. 3.2 Structure and Layout High quality factor integrated circular spiral inductors were fabricated in SPAWAR Systems Center’s novel 0.5 μm TSOI CMOS technology with a stacked 1.7 μmthick aluminum metal. The geometry of the spiral inductors can be described by the following parameters: number of turns (n), turn width (w), turn spacing (s), inner diameter (d) or inner to outer radius ratio (IDOD). These parameters are shown in Figure 13 3.1(a). The die photo is shown in Figure 3.1(b). The width of the spiral metal is from 15 um to 50 um. The innertoouter diameter ratio is from 0.3 to 0.7. And the number of turns is from 1.5 to 10.5. Figure 3.2 shows a crosssection of an integrated inductor fabricated in this technology. The test frame with groundsignalground pad was laid out for shielding. The inductors we investigated can be grouped in the following classes: 1) Same IDOD, but different n and w; 2) Same w, but different IDOD and n; 3) Same n, but different IDOD and w. All the inductors have a fixed spacing between the turns, s = 3 μm. In this case, the inner radius (Ri) can be derived analytically from the parameters set (n, w, IDOD), Ri=IDOD*n*(w+s)/(1IDOD). Three families of inductors were characterized by sparameter measurement with HP 8720D network analyzer and Cascade Microtech coplanar groundsignalground (GSG) probes. Deembedding was carried out to remove the parasitic components. (a) 14 (b) Figure 3.1 (a) Structural parameters of an onchip spiral inductor, (b) Die photograph of the spiral inductor. Figure 3.2 Crosssection of inductor. 3.3 Inductor Model and Parameterextraction Method (a) 15 (b) (c) Figure 3.3 Equivalent circuit for models: (a) with substrate, (b) without substrate, (c) equivalent circuit at low frequency. The equivalent circuit for the inductor is shown in Figure 3.3, where Ls is the inductance and Rs is the parasitic series resistance of the metal wire. The overlap between the spiral and the underpass allows direct capacitive coupling between the two terminals of the inductor. This path is modeled by the series capacitance Cs. In a conventional inductor structure, the oxide capacitance between the inductor and the silicon substrate has to be taken into account, as well as the subcircuit of the substrate, which are shown in Figure 3.3(a). However, including these parasitic circuit elements makes the extraction of the important intrinsic inductor parameters very tricky and inaccurate. In order to improve the inductor performance the silicon substrate has been etched away. As a result, the self resonance frequency and quality factor Q of the inductor increase. The resulting circuit model can be simplified to the one shown in Figure 3.3(b). The meaning of Cox in this circuit is no longer the capacitance between the 16 inductor and the substrate; instead, it models the remaining parasitic capacitive coupling between the inductor and the surrounding grounded structures. At low frequency, 100MHz, both the coupling capacitor Cs and the parasitic capacitor Cox can be neglected, thus the circuit model is further reduced to the one in Figure 3.3(c). For this series RL circuit, the two components can be easily extracted from the Yparameter: 2111ImLsYω⎛⎞=−⎜⎟⎝⎠ (3.1) 211ReRsY⎛⎞=−⎜⎟⎝⎠ (3.2) However, as the Yparameters cannot be measured accurately, they are obtained by the transformation from the measured sparameters. The overall capacitance can found from the selfresonance frequency: 201CLsω= (3.3) where C includes Cox and Cs. All parameters (L, R and C) in the inductor model are functions of the number of turns (n), the turn width (w), the turn spacing (s), and one from the following: the outer diameter dout, the inner diameter din, the average diameter davg = 0.5*(din+dout), or the inner and outer diameter ratio (IDOD). By fitting the data, expressions for Ls, Rs and Cs were determined. We have successfully obtained these parameters for inductors in a broad range: the number of turns from 1.5 to 5.5, turn width from 15 um to 50 um, and inner and outer diameter ratio from 0.1 to 0.7. 17 Due to large amount of data collected, computer software was employed to find the dependence on the geometric parameters. However the selected software (Origin 7) can only fit two independent variables, therefore, the following three approach was used: a) Ls = f (w, n), while IDOD is fixed, b) Ls = f (n, IDOD), while w is fixed. c) Ls = f (IDOD, w), while n is fixed, As the approach c) is not practical, the approaches a) and b) were adopted. 3.4 Results and Model Verification 3.4.1 Series Inductance (Ls) The empiric expression of the series inductance is based on the data fitting technique in reference [15]. For fix IDOD, the expression is 321PPLsPnw= (3.4a) Taking the logarithm of Eq. (4a) we can get the following monomial relation: 123loglogloglogLsPPnP=++ w (3.4b) For the inductors with IDOD = 0.5, the fitted the parameters are found: P1 = 0.26591, P2 = 2.21235 and P3 = 0.72121. Therefore, the inductance can be modeled as: 2.212350.721210.26591Lsnw= (3.4c) In a same way, the inductor model can be fitted following the approach b). As an example, inductors with w = 25 can be modeled as: (3.5) 1.548630.511541.07185LsnIDOD= 3.4.2 Series Resistance (Rs) 18 The series resistance of the inductor can be expressed as [16]: effrstwlR⋅=ρ (3.6) where rρ is the resistivity of the metal; l is the overall length of spiral, which equals avgdnπ; w is the line width; is the effective thickness. With the consideration of the skin effect, the effective thickness can be calculated as efft)1(δδteffet−−⋅=; where t is the physical thickness of the metal and δis the skin depth. At 1 GHz, the skin depth of Al and Cu is 2.8 um and 2.5 um, respectively. 3.4.3 Series Capacitance (Cs) The Series capacitance Cs models the parasitic capacitance coupling between the inductor and the underpath. It can be approximated as a parallelplate capacitor [17]. 223oxsMMkCnwtε−⋅= (3.7) Where 23MMt− is the oxide thickness between spiral and the under path, which is 0.9 um in our sample; = 0.7 is a fitting parameter. k 3.4.4 Model Verification With the method described above, the parameters of the series resistance, inductance and capacitance can be extracted; the results from two samples are shown in Table 1. The measured and simulated Sparameters have been compared in Figure 3.4 and Figure 3.5, where the numbers of turns are 2.5 and 4.5, respectively. The measured inductances as the function of frequency are plotted in Figure 3.4(b) and Figure 3.5(b). 19 The total error [18] between the measured and the simulated sparameter calculated as follows by (3.8) is less than 3% over the frequency range from 0.1 to 10 GHz. 221()1004ijijtot 1 freqijfreqijmeasSsimSSNmeasSε⎧⎫−⎪=⋅⋅⎨⎪⎪⎩⎭ΣΣ ⎪⎬ (3.8) The simulation is carried out with ADS. We also compared the results from inductors with other structural parameters, they consistently have good agreement. Table 3.1 Extracted circuit model parameters. Turn w (μm) IDOD Ls(nH) Rs (Ω) Cs(fF) 2.5 25 0.5 2.8 0.13 41.48 4.5 25 0.5 12 0.36 75 freq (100.0MHz to 10.00GHz)S(2,1)inductor_mod..S(2,1) Figure 3.4 (a) Measured (dot) and simulated (line) sparameter, n=2.5, w=25um, s=3um, and IDOD=0.5. 20 Figure 3.4 (b) Measured inductance as a function of frequency. n=2.5, w=25um, s=3um, and IDOD=0.5. freq (100.0MHz to 10.00GHz)S(2,1)inductor_mod..S(2,1) Figure 3.5 (a) Measured (dot) and simulated (line) sparameter, n=4.5, w=25um, s=3um, and IDOD=0.5. Figure 3.5 (b) Measured inductance as a function of frequency. n=4.5, w=25um, s=3um, and IDOD=0.5. 21 A typical fit of the VerilogA model vs. the measurement data for two inductor instances is shown in Figure 3.6. Figure 3.6 shows that a 6.5 nH inductor has a peak Q of 18, which is higher than the best Q of 15 reported in [19] for a 5.5 nH inductor in a silicononsapphire (SOS) technology with a thicker 2.5μm aluminum metal. The 6.5 nH inductor has a selfresonant frequency at about 10 GHz, which is about twice the selfresonant frequency reported in [19]. Figure 3.6 Comparison between measurement data and model simulation. We also find the model developed is accurate for inductors with the number of turns less than 5.5, fortunately most practical onchip spiral inductors fall in this range. When the number of turns is larger than 5.5, the error becomes larger and more circuit elements must to be included in the model. As shown in Figure 3.7, the model can not predict the behavior for frequency higher than 7 GHz. 22 freq (100.0MHz to 10.00GHz)S(2,1)inductor_mod..S(2,1) Figure 3.7 Measured (dot) and simulated (line) sparameter, n=5.5, w=25um, s=3um, and IDOD=0.5. 3.5 Conclusion Based on the above analysis, we found that small IDOD ratio inductors were turnrestricted. For example, if IDOD equals to 0.1and 0.2, n should be maintained less than 2, and 3 respectively. Generally IDODs of 0.4 to 0.5, w of 15 um to 30 um and s of 3 provide a better model fit. The obtained equivalent Spice circuit model shows good agreement between the simulated and measured sparameters over a wide frequency range. 23 Chapter 4 Integrated Varactor 4.1 Introduction Integrated voltagecontrolled capacitors (varactors) are widely used as frequency tuning elements for RF applications [20, [21], such as voltage controlled oscillators (VCOs). The core of a VCO is the LC tank circuit, composed of a varactor and an inductor. Several RF models for the MOS varactor have been reported [21, [22, [23, [24]. The physical model proposed in [21] was derived by considering the device structure but consisted of separate models for different operating regions of the device, i.e. in accumulation and in depletion, respectively. The theoretical model reported in [22] includes the physicsbased equations. The SPICE compatible models exploiting a subcircuit based on the BSIM3v3 model were presented in [23] and [24]. This chapter presents a RF model of an accumulationmode MOS varactor with a high capacitance tuning range in a multifinger layout, and it is based on physical parameters. The model describes the voltage dependent capacitances and resistances along with the parasitic inductance, capacitance and resistance terms. A single topology with the lumped elements derived from the device has been proposed for easy integration into common circuit simulator as well as direct linkage to a pcell. Good agreements between measured data and simulation results were obtain in the frequency range of 0.1 to 25 GHz by deembedding the test frame inductance. 24 4.2 Structure and Layout Accumulationmode MOS varactors were fabricated in SPAWAR Systems Center’s Integrated Circuit Fabrication Facility in their 0.5 um CMOSSOI technology where the substrate has been removed. This process has low parasitic capacitance which facilitates fabricating high quality, high frequency RF varactors by decreasing the losses normally associated with bulk silicon processes. The varactors designed, fabricated and tested employ a multifingered layout with finger lengths of 0.5 um, 0.8 um, and 1.0 um, finger widths of 5 um and 10 um, and total widths of 1000 um. A representative crosssection of the device is shown in Figure 4.1 with a micrograph for a typical layout shown in Figure 4.2. Figure 4.1 The crosssection of the single varactor. Measurements confirm that the varactors have a tuning ratio that varies from 1.7 for the 0.5 um device to 2.6 for the 1.0 um device. The worst case selfresonant frequency of 21.5 GHz was observed for the W = 2005mμ×, L = 1.0 um device at its maximum capacitance of about 2.13 pF at 500 MHz, as shown in Figure 4.3(a). As observed in 25 Figure 4.3(b), the quality factor remains satisfactory (above 8) up to 12.8 GHz. These figures are significant compared to other varactors which have been created recently [23]. Figure 4.2 The micrograph of the varactor under test. (a) 26 (b) Figure 4.3 (a) Capacitance versus frequency and (b) quality factor versus frequency. 4.3 Model Parameter Extraction and Model Verification To verify and parameterize the proposed equivalent circuit show in Figure 4.4, the fabricated accumulationmode MOS varactors were laid out and extracted. Direct parameter extraction was performed with Yparameter analysis based on Sparameter data using an HP8720D network analyzer. Cs was extracted out at 1 GHz, with the Rs and L extracted at selfresonance. Deembedding was carried out to remove parasitics, which consisted primarily of an inductance term. Rm1 and Rg and Rs/dcnt (≈ 0) represent the metal1, the gate and gate contact resistance and source/drain contact resistance respectively. In order to model the gate bias dependence of CVar’, varactors capacitance per unit width was described as follows, GGoxavgfCGCGCVarVVLCCCPVPVPCβ+++=++=1''1'321. (4.1) Where 27 , oxCLCP=1 β=CP2, and ''3avgfCCCP+=. Figure 4.4 The equivalent varactor circuit. Figure 4.5 Capacitance versus length at VG=0V. The fringe capacitance per micrometer of varactor width, Cf’ , was obtained by plotting the varactor capacitance at VG equal zero and extrapolating to find the fixed capacitance 28 term or the P3C component of equation (1). All three test devices with gate lengths of 0.5 μm, 0.8 μm and 1 μm respectively, are plotted as shown in Figure 4.5. Cf’ is found to equal 0.24 fF/μm. Equation (4.1) is based on the data fitting and accurately describes the nonlinear characteristic of CVar as a function of the varying gate bias, as shown in Figure 4.6. For the 5_200_p8 (finger width_finger number_gate length) varactor, P1C =1.64 fF/μm, P2C =2.99 V1, P3C =1.23 fF/μm and for 5_200_1 varactor, P1C =2.89 fF/μm P2C =3.63 V1, P3C =1.58 fF/μm. Using the P3C data and Cf’ from Fig 4.5. and solving for CoxAvg and δL, respectively, result in CoxAvg equal 1.765 fF/μm2 and 0.117 μm or Leff = L – 0.234 μm. Varactor resistance consists of both a channel term and the gate poly term. The channel resistance is modeled as follows; (4.2) paccschRRRR//+= In (3.2), is the gate bias independent or static resistance term of RsRch. Racc represents the resistance of the accumulation layer formed in the channel region. Rp is the nwell resistance in parallel with Racc. ,,1(),,accGGchGGchchKVdVifVdVRelsewhere−>⎧=⎨∞⎩ (4.3) In (3.3), is a parametric coefficient that is related to the mobility of electrons in the accumulation layer, and is relevant to the flatband voltage. As VaccKchGdV,G decreases below the flatband voltage, Racc can be considered as being infinite and Rch approaches a constant value of Rs + Rp. When VG increases above the flatband voltage, Racc dominates Rch. As a result, Rch decrease, finally approaching a constant value of Rs, as shown in Figure 4.6. 29 Figure 4.6 Capacitance and Resistance change verse gate bias voltage as extracted from the varactor parametrics. Similarly, a data fitting equation is used to describe the voltage dependence of resistance: RGRGRsPVPVPR3211++=, (4.4) From the extracted resistance data for the 5_200_p8 varactor; P1R = 0.138 V1 P2R = 0.191 V1, P3R = 2.72 Ω and for the 52001 varactor; P1R = 0.0805 V1, P2R = 0.0354 V1, P3R = 2.65Ω. The extracted parameter values for the series resistance and inductance are summarized in Table I for VG =0 V. Table 4.1 Extracted parameter values for 200 finger (Wf = 5um) varactors for L equal 1 um and 0.8 um respectively. L(pH) Rm1(Ohm) Rg(Ohm) Cf(pF) Cs(pF) Rch(ohm) 5_200_0.8 35 0.05 0.078 0.24 0.958 0.658 30 5_200_1 35 0.05 0.0625 0.24 1.20 0.6415 Figure 4.7 and 4.8 compare the measured and simulated Sparameters at 0=GVV for the devices of Table 4.1. Note, the methods for determining L, Rm1, and Rg are presented in section 4. The total error between the measured and the simulated Sparameter with the proposed equivalent circuit was calculated to be in less than 1% over the frequency range from 1 to 25 GHz. Figure 4.9 shows measured and simulated CV characteristics for the L=0.8 μm and L=1 μm devices. freq (1.000GHz to 10.00GHz)S21S11 Figure 4.7 L=0.8um Vg=0V symbol is measured data and line is the simulated. 31 freq (1.000GHz to 10.00GHz)S11S21 Figure 4.8 L=1um Vg=0V symbol is measured data and line is the simulated. Figure 4.9 Comparison of the measured (symbol) and simulated (solidline) CV characteristics for the L=0.8um and L=1um devices. 4.4 Layout Summary and Usage In the circuit design process the designer is given the option to select L in the range of 0.7 um to 1.1 um at fixed finger width Wf of 10 um. The designer selects the varactor channel length L and provides the desired value of C (VG =0) for the varactor at 32 simulation/layout. The number of fingers n, along with the number of rows (r) and columns (c) will then be computed by the pcell generator and modeled for simulation by the Verilog code. It is strongly suggested that all fingers be wired with 10 um wide or wider m1 line with at least two gate contacts per finger for reliability. The pcell and VerilogA model are restricted to Wf=10 um and m1 interconnects that are 10 um in width. 4.4.1 Capacitance Calculation and Length choice The total capacitance of a varactor is modeled as the sum of a strongly bias dependent intrinsic capacitance (Cint) component and a weakly bias dependent fringe capacitance (Cf). The latter is equal to 0.24 fF/um. a. L was selected such that L approached being LCox >> Cf. Note this includes CGDO. The minimum L has been selected to be greater than 0.8um. b. Wf was selected such that Rg << Rch . The gate resistance is propotional to Wf but channel resistance is inversely proportional to Wf. Proper Wf choice will reduce the gate resistance. Thus, it can reduce the gate resistance noise. c. WTotal ≈ CAvg/(LCox + Cf’). Where CAvg is the average or zero bias value of the varactor capacitance and approximately equal: CAvg ≈ WTotal(L2δL) CoxAvg /2 (4.5) At VG equal to 0 V the zero bias value of the capacitance equals: CVar (VG =0) ≈ WT(L2δL) CoxAvg /2 + Cf’ WT. (4.6) Additionally, CMin ≈ WCf’ (4.7) 33 CMax ≈ WLCoxMax + WCfringe’ (4.8) The varactor with longer channel (L=1 um) provides a greater dynamic capacitance range with a reduced Qeff, while a shorter channel length varactor (L=0.8 um) provides a higher Qeff with a reduced dynamic capacitance range. a. nf the number of fingers equals WT/Wf. b. For a square varactor layout i. c (L + 1.6um) = r (Wf+12um) (4.9) ii. c x r = n fingers (4.10) iii. )12(6.1umWumLnrf++= (4.11) where )'(fringefAvgCCoxLWCn+⋅= then rnc= where the row value is rounded to the nearest integer and the column value solved for. 4.4.2 Resistance Estimation The metal1, gate and contact resistance can be written as: 1)2/)((1 10um1.6um)c(L)2/)((1 10um1.6um)c(L1+⎥⎦⎤⎢⎣⎡++⎥⎦⎤⎢⎣⎡+=rRoundRshmrRoundRshmRm (4.12) where Rm1 = 50 mohms. 3fgWRshpolyRLn=⋅ (4.13) 34 For L =1 μm, Wf = 5 μm, and n = 200, it is approximately equal to 20 mΩ. Where Rshpoly = 2.5 . Ω021/≈⋅=nIsRmRDcntS (4.14) Where Rm1Is = 5 ohms. 4.4.3 Inductance Estimation With the interconnect wiring set by the square feature of the varactor the inductance is better controlled and better estimated. The basic unit of inductance is estimated as follows: ⎥⎦⎤⎢⎣⎡−+⋅+⎥⎦⎤⎢⎣⎡−⋅=−−75.02ln)12/(10275.02ln)2/(1021717mmwlcRoundlwlcRoundlLp (4.15) where is set to 10 μm and l equal r(L+1.6 μm). This is an approximation. Due to the lack of separation between the fingers for W1mwf equal 5 or 10 μm it will have limited value above 5 to 10 GHz. Note the centertocenter m1 separation of the gate m1 and S/D m1 will be Wf +10 μm (m1) +2 μm (recommended m1 separation) in the pcell. 4.5 Conclusion In summary an equivalent RF model of an accumulationmode MOS varactor with high capacitance tuning range in a multifinger layout is constructed, which is composed of the following physical parameters: 1. Cf ‘ the total equivalent per um fringe capacitance – 0.24 fF/μm. 2. CoxAvg the equivalent oxide sheet capacitance  1.765 fF/μm2. 35 3. δL the channel foreshortening distance  0.117 μm or Leff = L – 0.234 μm. These parameters along with the fitting equations (4.1) and (4.4) and their coefficients can reliably be used to model the varactor capacitance, CVar’ and its voltage controlled channel resistance Rch. Finally, the inductance and gate resistance parasitics are modeled by equations (4.12) through (4.14). The varactor model is valid for finger widths of 10 μm and lengths from 0.7 to 1.2 μm where the total width is not expected to exceed 2000 μm or 200 fingers. The accompanying pcell and VerilogA model are restricted to finger widths of 10 μm and m1 interconnection width of 10 μm. 36 Chapter 5 FinFET transistors and Modeling 5.1 Introduction As the microelectronic industry is fast approaching the limit of bulk CMOS scaling, there are extensive research activities on advanced CMOS structures to extend CMOS scaling to less than 100 nm gate length. The FinFET is an innovative design of MOSFET, which is built on an SOI structure. The body of the transistor is etched into "fin"like structure, which is wrapped by the gate on both sides. The double gate (DG) MOSFET is a popular choice, because this structure is scalable and the short channel effects can be suppressed for a given equivalent gate oxide thickness . As shown in Figure 5.1, several rectangular multigated structures have been proposed recently, such as FinFET [25], trigate [26], Omegagate [27], pigate [28], etc. The FinFET has emerged as the most popular device because of its ease of babrication with the wellunderstood bulkMOSFET process. Figure 5.1 Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or: GAA structure); 5) Pigate MOSFET. [28] 37 The key challenges in the fabrication of doublegate devices are (a) selfalignment of the two gates, and (b) formation of an ultrathin silicon film. Figure 5.2 shows the different orientations possible for a doublegate device. Several selfaligned planar devices have been proposed [29], however, the process is usually complex and the contact to the bottom gate is very challenging. Devices with ultrathin film are generally considered incompatible with traditional processes. The FinFET is derived from the vertical MOSFET by reducing its height and converting it into a quasiplanar device. Figure 5.2 The possible Doublegate MOSFET orientations on silicon [29]. 38 Figure 5.3 The 3D FinFET. Figure 5.4 Scanning electron microscope picture of the cross section of FinFET (compliments of SPAWAR SC San Diego). Figure 5.4 depicts the geometry of the FinEFT. The fin is a narrow channel of silicon patterned on an SOI wafer. The gate wraps around the fin on three faces. The top insulator (nitride) is usually thicker than the side insulator (oxide), hence the device has effictively two channels. The thickness of the fin represents the body thickness (Tsi) of the doublegate structure, while its hight (Hfin) represents the channel width. 39 Figure 5.5 FinFET Process steps; from [25] Figure 5.5 shows the basic processsteps involved in the fabrication of the FinFET. Since it was first proposed [25], refinements have been reported consistently [30, [31]. 5.2 Performance of FinFET Transistors The FinFET transistors were fabricated using SOI deep submicro (DSM) technology at SPAWAR system center, San Diego. There were two wafers made using the same mask. For the first run there are only four dies working on the whole wafer and 40 most measurements were made with these transistors there. For the second run the finger yield is low. Although transistors seemed to be working but their drain current much is less than expected. Some measurements were also made on this wafer. The discussion is that follows is an attempted to explain the problem. 5.2.1 DC Measurements HP4155A semiconductor analyzer was used to make the DC measurement. Figures 5.6 to Figure 5.9 show FinFET (10 um width, 56 nm length) IV characteristics. Figure 5.6 FinFET drain current versus drain voltage at various gate voltages. 41 Figure 5.7 FinFET drain current versus gate voltage with drain voltage equal 50mV. Figure 5.8 FinFET drain current versus gate voltage with drain voltage equal 1.4V. 42 Figure 5.9 FinFET versus gate voltage with drain voltage equal 1.4V. mg In saturation, the ideal drain current has a squarelaw dependence on the gatetosource voltage for long channel devices. But from the drain current curves shown in Figure 5.6 we find that it has a linear relationship with the gate voltage. This occurs as a result of velocity saturation. The highfield effects become prominent at moderate drain voltage with continued device scaling. The primary highfield effect is velocity saturation. In silicon, as the electric field approaches aboutV/m, the electron drift velocity shows a weak dependence on the field strength and eventually saturates at a value of about 106410×5 m/s. For an 80 nm gate length device, velocity saturation begins to kick in at 320 mV. With the gate voltage above threshold voltage and draintosource voltage above 320 mV the device enters velocity saturation region. In the velocity saturation the drain current can be rewritten as ()2noxDGStsatCIVV E μ=− (5.1) 43 The values of all smallsignal parameters can change significantly in the presence of shortchannel effects. The limiting transconductance of shortchannel MOS device in velocity saturation, 2noxDmGSCI sat gWEVμ∂≡≈∂ (5.2) Figure 5.7 indicates the threshold voltage of the FinFET is around 0.1V. It is difficult to design RF and analog circuits with negative threshold voltage device. Molybdenum gate technology has been applied to modify the threshold voltage of FinFET transistors, and it was successfully adjusted to 0.4 V [32]. Figure 5.10 shows FinFET drain current versus gate voltage at different drain voltages. The subthreshold slope is about 80mV/dec for drain voltage equal 50mV, and n is 1.33. 56 nm (Gate Length) FinFET IV Characteristics10x0.056 (WxL) FinFET, Wafer 2751401.00E101.00E091.00E081.00E071.00E061.00E051.00E041.00E031.00E021.00E011.00E+0010.500.511.5VGS (V)Log ID (A)Vds=0.05 Vvd=1.4v Figure 5.10 FinFET drain current versus gate voltage at various drain voltages. 44 5.2.2 AC Measurement HP8720D network analyzer was used to make Sparameter measurement on FinFET transistor (W=72um, L=80nm). The maxfwas extracted when the power gain equal to unity, that is 2211S=, as shown in Figure 5.11. Convert Sparameters to Hparameter. The fT can be extracted at 211h=. With the transistor working in velocity saturation region (, V0.7VΔ≈ Vt=0.1V, VDS=1.2V), maxfof FinFET is approximately 100 GHz, as shown in Figure 11; And fT is approximately 42 GHz, as shown in Figure 12. 1E81E91E101E111E1251015202530 Power Gain (dB)Frequency (Hz)1 Figure 5.11 FinFET transistor power gain versus frequency (0.7V V Δ≈, VDS=1.2V). 1E81E91E101E111020304050 Current Gain (dB)Frequency (Hz)1 Figure 5.12 FinFET transistor current gain versus frequency (0.7V V Δ≈, VDS=1.2V). 45 With the transistor working in moderate inversion region (, V50VmΔ≈ Vt=0.1V, VDS=1.2V), tf is approximately 20 GHz, as shown in Figure 5.13. Antf of 20GHz is adequate to design low GHz applications when transistor works in moderate inversion region. 1E81E91E101E11510152025303540 Current Gain (dB)Frequency (Hz)1 Figure 5.13 FinFET transistor current gain versus frequency (50VmV Δ≈, VDS=1.2V). Since the FinFET with 80nm channel length works in velocity saturation region, the transition frequency, tf can be rewritten as, ()132243noxsatmnTgsoxCWEgECLWLCμμω≈≈= sat (5.3) In the velocity saturation region the transit frequency is inversely proportional to the channel length, which is different from that in the strong inversion region. The maximum frequency of unit power gain can be rewritten as [33], ()2TMaxfringegSgsffCRRgmC=⎛⎞+⋅⋅⎜⎟⎜⎟⎝⎠ (5.4) 46 5.2.3 Noise Measurement Figure 5.14 shows noise measurement made on FinFET transistor. It also demonstrated less lowfrequency noise in moderate inversion than in the strong inversion [34]. It further supports FinFET use in moderate inversion operation in the design of RF circuits. Figure 5.14 The low frequency noise of the FinFET for L=120nm, W=4.2um [9]. 5.2.4 Capacitance Measurement Measurements were performed on a Keithley 590 CVmeter and Keithley 4200 semiconductor characteristics analyzer. All measurements were performed in the dark chamber. For the equilibrium CV measurement, the hold time and delay were set to 5 sec and 1.5 sec, respectively. The gate voltage sweep rate can be calculated as (bias range)/(total sweep time). The source and drain are shorted together, i.e. Vd = Vs = 0 V. Figure 5.15 shows the high frequency gatetochannel capacitance (hfCgc) curve of an n 47 channel FinFET. The hfCgc reaches its maximum value when the channel is in strong inversion and exhibits a minimum with reverse gate bias. Figure 5.15 Equilibrium high frequency CV curve. The CV measurement is a valuable diagnostic tool to characterize MOSFET. Therefore, if the influence of gate depletion capacitance can be neglected, the measured maximum gatechannel capacitance is equal to oxide capacitance. The extracted oxide thickness found is 2.4 nm, which is different from the designed 2 nm thickness [35]. 5.3 FinFET Model 5.3.1 FinFET SmallSignal Model The framework for generic physics based doublegate MOSEFT modeling has been recently reported [36]. However, to our best knowledge there is no FinFET smallsignal model describes its behavior in GHz region. The FinFET structure investigated is depicted in Figure 5.16, where key geometry parameters are defined. The fabricated 48 transistor is shown in Figure 5.17. Based on the measurement results from this device, we developed a high frequency small signalmodel. Figure 5.16 The 3D FinFET. Tbox=400nm, Hfin=50nm, Tsi=20 nm. Figure 5.17 Die picture of the circuit with test frame. Figure 5.18 FinFET transistor characteristics (W=72 um, L=80 nm). 49 The FinFETs were fabricated at SPAWAR system center, San Diego. The gates of the FinFET were ebeam written at Berkeley with a range of 50 to 200 nm, and the overall gate width is 72 um. There are 720 fins in this transistor, and the gate width (2Hfin) for each fin is 100 nm. The DC IDVDS curves are shown in Figure 5.18. The Sparameters were measured with an Agilent 8510 Network Analyzer and Cascade RF1 probe station using GSG probes. The data was collected from 45 MHz to 10 GHz. The equivalent circuit shown in Figure 5.19 is based on a quasistatic approximation, which is found to be adequate in the GHz range if the extrinsic components are properly modeled [37]. This model includes the complete intrinsic quasistatic MOS model, the series parasitic impedance of the gate, source and drain, as well as a substrate coupling network. The extrinsic part includes the parasitic series resistors Rg, Rd and Rs, and the parasitic series inductors Lg, Ld and Ls. The intrinsic model is composed of the voltagecontrolled current source, the output resistance and the gate to channel impedance, as well as the intrinsic capacitors Cgs, Cgd and Cds. 50 Figure 5.19 The FinFET smallsignal equivalent model. Figure 5.20 Zero bias smallsignal equivalent model. The parasitic resistance is extracted at low frequency with the device biased at VGS=VDS=0V. Under this bias condition the contribution from the intrinsic circuit vanishes except the three capacitors between the intrinsic nodes. In addition, in the low frequency region the parasitic inductors and the substrate coupling can be neglected. The schematic of the zero bias equivalent circuit at low frequency is shown in Figure 5.20, from which the parasitic resistors can be extracted by the Zmatrix components: 11Re()gsZRR=+ (5.5) 22Re()d s ZRR=+ (5.6) 1221Re()Re()sZZR== (5.7) After the parasitic resistors have been extracted, the parasitic inductors can be modeled separately by means of the transmission line equations [38]. With the knowledge of the parasitic resistance and inductance, the intrinsic model can be determined. First, the Sparameters measured at low frequency and under the bias condition of Vgs=0.6V and Vds=1.2V are converted to the Zparameters. Next the parasitic resistance terms are deducted, which is shown in Equation (5.8)(5.11), in this way the intrinsic Zparameters are obtained. In the intrinsic model most of the 51 components are in shunt connection to the internal source node, so the Zparameters are converted to the Yparameters, and then the circuit elements in the intrinsic model have been extracted. The circuit elements in the substrate network are fitted with the high frequency measurement results from inductor model extraction [39]. In Table 5.1 we list the extracted model parameters. '1111( ) gsZZRR=−+ (5.8) '2222(ds) ZZRR=−+ (5.9) '1212sZZR=− (5.10) '2121sZZR=− (5.11) '' (5.12) Z →Y Table 5.1 Extracted Model Parameters Lg(pH) Rg(Ω) Rd(Ω) Ld(pH) Rs(Ω) Ls(pH) 100 4.6 10 50 10 50 Cf(fF) Cdep(pF) Cgs(fF) Rch(Ω) gm(S) t (ps) 66 1 300 10 0.1 5 Rds() Ω Cds(fF) Cgb(fF) Rgb(Ω) Csb(fF) Rsb() Ω 450 260 5.6 110 11.2 60 Cdb(fF) Rdb(Ω) Rdsb(Ω) 11.2 60 98 52 Figure 5.21 and 5.22 show the comparison between the measured data and the simulation result from the extracted model. The discrepancy is within 5%, which is calculated from the following equation: 2''2211Re()Re()Im()Im()100ijijijijijijSSSSErrornS==⎡⎤−+−⎢=⎢⎢⎥⎣⎦ΣΣ ⎥⎥ (5.13) In summary, we developed a RF small signal model of FinFET from the extracted data, and good agreement between the model and the measurement is achieved up to 10 GHz. freq (45.00MHz to 10.05GHz)S12S22S11 Figure 5.21 Measured (dot) and modeled (line) Sparameters (Vgs=0.6V, Vds=1.2V). Figure 5.22 Measured (dashed) and modeled (solid line) S21 (Vgs=0.6V, Vds=1.2V). 53 5.3.2 FinFET BSIMSOI Model FinFET BSIMSOI Model was extracted by using Utmost, a Silvaco package [40]. A Semiconductor Analyzer (HP4155A) was used to measure the IV curve. Then the DC parameters were extracted by using DC routines in Utmost. A CapacitanceVoltage meter (Keithley CV590) was used to measure all capacitance and network analyzer (HP8720D) was utilized to do Sparameter measurement. Through AC routines in Utmost, AC and capacitance parameters have been extracted. In addition high temperature and noise measurement were done by my lab mates. After all these measurement and data analysis were finished, a complete FinFET BSIMSOI V3 model has been extracted. The detailed model parameters and simulation and measurement comparison are shown in Appendix B. 5.3.3 FinFET Model Summary Both smallsignal model and BSIMSOI model are presented in the previous sections. The smallsignal model demonstrates the feasibility of FinFET operated in velocity saturation region. The BSIMSOI model supplies the opportunity to simulate the RF circuits working in moderate inversion with Cadence RF spectre tools. But the threshold voltage is approximately 0.1 V, which is not practical for RF circuits design. It is a fabrication process problem. But the FinFET fabrication process is still improved. For example, Molybdenum gate technology has been applied to modify the threshold voltage of FinFET transistors, and it was successfully adjusted to 0.4 V [32]. In this work it is reasonable to justify the threshold voltage to 0.5 V. The selected model parameters are shown in Table 5.1. This model will be used in the later chapters to simulate the RF 54 receiver circuits in moderate inversion. The Figure 5.23 compares the measured ft to the modeled ft curves in moderate inversion. The good agreement is found between the measurement and model simulated ft curves. Table 5.1 The modified FinFET BSIM3SOI model. model NFIN b3soipd type=n + tnom=27 version=3.1 tox=2.4e9 + tsi=2e8 tbox=4.0e7 xj=1e8 + nch=4.46e14 vth0=0.5 nlx=1.468104e8 + dvt0=2.5477237 dvt1=0.542419 dvt2=1.416439e4 + u0=400 ua=2.35143e10 ub=1e18 + uc=1.232366e9 vsat=1e4 a0=1.0446036 + ags=0.5742591 b0=1e8 b1=1e7 + lint=1.683313e9 eta0=0.01 mobmod=1 + capmod=2 cjswg=2e10 cgdo=3e10 + cgso=3e10 rsh=600 + nrd=50 nrs=50 55 1E8 1E9 1E10 0 5 10 15 20 25 30 35 40 45 50 Current Gain (dB) Frequency (Hz) Frequency (Hz) Figure 5.23 Measured (dot) and modeled (line) h21 (50VmV Δ≈, Vds=1.2V). 5.4 Summary Based on the above measurement data and analysis we found the FinFET transistor is a promising deepsub micron device. The promising features of the FinFETs include high frequency, low supply voltage and low gate leakage current, making it an ideal candidate for the design of low power RF frontends. It has excellent performance in both strong and moderate inversion regime. Specifically, its ft is approxiamtely 20 GHz in moderate inversion regime, which makes it feasible to realize the ultralow power RF receiver frontend. The only problem of current FinFET transistors is the negative threshold which makes it hard to be biased. The threshold voltage of FinFET transistor model is assumed to be modifiable to a positive value. For an instance, the VTH0 is set to 0.5 V for long channel device. 56 57 Chapter 6 GPS Receiver Design 6.1 Introduction In Chapters 3 and 4 the passive devices, onchip inductors and varactors, were modeled. They will be used in the following chapters to design the RF circuits for the GPS receiver. In Chapter 5 FinFET transistors were measured and characterized. It did have good performance. Especially, the fT is around 20 GHZ at moderate inversion, which is enough to realize the circuits working below 2 GHz. The model developed was also valid for moderate inversion and it showed good agreement with the measurement. We will take advantage of the features of FinFET moderate inversion to realize the GPS receiver frontend circuits so that it can operate in ultralow current. As we know, the GPS is a satellitebased location/time finding system with 24 satellites orbiting the earth. It is a direct sequence spread spectrum (DSSS) functioning at two bands: L1 (1575.42 MHz) and L2 (1227.6 MHz) [41]. Most commercial GPS receivers use the L1 band only. The L1 band has two sets of codes, coarseacquisition (C/A) and precision (P). The original 50 bit/s data is spread over a 2 MHz bandwidth (BW) for the C/A code, as shown in Figure 6.1. 58 Figure 6.1 The GPS L1/L2 band signal spectrum [42]. At the antenna of a GPS receiver, the received signal power is typically 130 dBm. Since we are interested in the 2 MHz main lobe of the C/A code, the noise power is simply given by kTBW, which equal 111 dBm. Therefore, the received signaltonoise ratio (SNR) at the antenna is around 19 dB. By despreading and integrating over a long time period, a receiver can exploit the inherent spread sprectrum processing gain of the navigation signals to get the proper postcorrelation signaltonoise ratio (SNR). 6.2 GPS Receiver Architectures 6.2.1 Typical GPS Receiver Architectures There are two architectures widely used in commercial GPS receivers today. The first is the dualconversion architecture, which is used widely. In this architecture, the L1 band is translated to a moderate intermediate frequency (IF) of approximately 100200 MHz where it is filtered by offchip filter before a second downconversion to a lower IF of about 110 MHz. Finally, the signal is filtered again before being amplified to a detectable level, as shown in Figure 6.2. 59 1LOω2LOω Figure 6.2 Dualconversion GPS receiver. The second is the singleconversion architecture, as shown in Figure 6.3. Here only one mixer is used. The L1 is directly sampled and then converted to baseband in a subsequent digital step. BPFLNA1LOωOffchip Figure 6.3 Singleconversion GPS receiver. Both architectures have a common advantage. An offchip LNA or active antenna is used, which gives the freedom to remotely place the antenna from the receiver itself. But they also have disadvantages. Either dualdownconversion or singleconversion architecture needs offchip components which increase the power cost and foot print. In order to realize high integration and low power consumption, CMOS lowIF GPS receiver architecture has been presented next to minimize the usage of offchip components and realize singlechip solution. 60 6.2.2 LowIF Architecture In general the lowIF receiver architecture is based on the replacement of the lowpass filters of a zeroIF receiver by a bandpass filter. The LowIF receiver is insensitive to DC offsets and LO to RF crosstalk or feed through. But it suffers from the problem of limited image rejection due to the need for stringent matching of inphase (I) and quadrature (Q) channel [43]. This limitation makes the lowIF approach unsuitable for many applications. However, when we examine the GPS signal spectrum, an opportunity emerges [44]. Figure 6.4 (a) shows a lowIF architecture with an IF of 2 MHz. The choice of 2 MHz lowIF results in an image frequency within the Pcode 20 MHz bandwidth. Thermal noise dominates the 20 MHz Pcode band. With an IF of 2 MHz, since the image frequency of C/A code lies in the Pcode band, no other strong signals are present in this band, as shown in Figure 6.5. Thus, the receiver only need reject the noise of unwanted sideband. The required rejection is only about 15 dB, which is easily obtained with ordinary levels of component matching [45]. This consideration makes the lowIF architecture an attractive choice for highly integrated GPS receiver. /2π Figure 6.4 Block diagram of CMOS GPS receiver. 61 Figure 6.5 The GPS band signal spectrum after downconverted to 2 MHz IF [44]. The complete analog signal path is integrated, including the low noise amplifier (LNA), the mixer, I and Q local oscillator (LO) drivers, IF amplifier (IFA’s), active filters, limiting amplifier (LA), and analogtodigital (A/D) converters. Since most components are integrated, the power consumption can be reduced. In general, lowing the frequency gives an immediate return on power saving. As was reported in Shaeffer’s work [44], since the output intermediate frequency of mixer is around 2 MHz, most power is consumed before the IFA’s. Over 60% of the power is consumed by the LNA, VCO and mixer. Therefore, in this work low power LNA, Mixer and LO designs were concentrated, as shown in the gray shaded area of Figure 6.4. The final objective is to design ultralow power LNA, mixer and LO. 6.3 Receiver System Design With the architecture of the GPS receiver determined, the receiver system planning is discussed next. The key point is to trade off the gain, noise figure (NF), and linearity properly among all circuits, such that every block can be implemented to satisfy low power requirement. Conventional RF system uses 50 Ω matching network at input 62 and output ports. However, in a low power RF receiver frontend with a single chip solution, except the first stage input impedance need to match antenna impedance, the following stages do not need to match 50 Ω or 75 Ω impedance, because it consumes large amount of current [6]. Such system is presented in Figure 6.7. Figure 6.7 Cascaded stages of receiver system. It can be shown that the intermodulation grows and accumulates through the cascades, and could be described, 112123113333cascadeGGGIIPIIPIIPIIP≅+++⋅⋅⋅ (6.1) where IIP3n is the IIP3 of the nth stage and numeric value, Gn is the power gain of nth stage. As for the noise of a cascaded system, assuming the first input stage of the cascade is matching to a source impedance of RS, and the following stages all have high input impedance and NF of each stage is calculated with respect to the source impedance driving that stage, the cascaded noise factor can be expressed as, 321111211ncascadeNnnFFFFFGGGG− 1 −−−=+++⋅⋅⋅+Π (6.2) where Gn and Fn is the power gain and noise factor of nth stage, respectively. Here, we assume that the individual stage’s characterization can be directly used to derive the 63 overall system performance. Namely, the loading from subsequent stage will not alter the noise and gain performance of the previous stage. This is a reasonable assumption in this work since the interstage loadings are capacitive and can be treated as high impedance. It also can be found from the above equations, increasing the gain in early stages improves the total NF, but at the cost of worse IIP3. Since in this work there is no IIP3 or IIP2 problem we could try to pursue the gain of LNA as high as possible with low noise figure. 6.4 Receiver Implementation Requirements To satisfy the stringent power requirement, it is necessary to properly specify and optimize the receiver specifications. Unlike other wireless communications systems, the GPS requirements were not well defined and specified in the literature until recently [42]. There are three noticeable differences between GPS and a conventional wireless standard. Firstly, GPS has only one RF channel in each band. Secondly, there is no strong inband interferer as is common in a cellular system. All these differences offer a good opportunity to build a lowpower GPS receiver. In the following section the receiver specifications are derived. 6.4.1 Noise Figure Figure 6.8 Block diagram of the GPS receiver. 64 In this work, a CMOS GPS receiver frontend is followed by an ADC and digital correlator, as shown in Figure 6.8. The purpose of a GPS receiver is to extract the accurate position and time information from the weak satellite signal. There also exist various source of position error. Some of the errors are from the satellite and propagation delay. The others are from the receiver impairments, such as noise. In order to account for the radio impairment, an important signal quality metric, the signaltonoise ratio (SNR) will be reviewed next. However, the SNR of direct sequence spread spectrum (DSSS) scheme is function of the position in the receiver under consideration. The precorrelation SNRs are negative, whereas postcorrelation SNRs are positive. It is convenient to normalize the SNR to 1Hz bandwidth. This achieves a ratio of signal and noise which is bandwidthindependent. It is referred to as the “carriertonoise density” ratio [46]. The carriertonoise density can be readily converted into SNR (S/N) or bit error rate (Eb/No), bbooECSBRNNN⎛⎞⎛⎞==⎜⎟⎜⎟⎝⎠⎝⎠ (6.3) where B is the bandwidth (in Hz) of that stage of receiver, Rb is a raw data rate of 50 b/s for L1 C/A band. This equation is converted into decibels []()01010log()CNdBHzSNRB⎡⎤−=⎣⎦ (6.4) From the above equation, it can be found that C/N0 is a nominal figure. Received satellite signal power varies with user antenna gain, satellite elevation angle, and satellite age [47]. Typical C/No range from 3555 dBHz. 65 Once the minimum required C/No is presented or processed by a digital correlator to maintain the wanted tracking or acquisition performance, the receiver sensitivity is uniquely determined by (6.5) without any confusion caused by the bandwidth ambiguity. [][][]minooCdBmSensitivitydBmdBHzNNFdBNHz⎛⎞⎡⎤=−++⎜⎟⎢⎥⎣⎦⎝⎠ (6.5a) [][][]minooCdBmSensitivitydBmdBHzNNFdBNHz⎛⎞⎡⎤=−++⎜⎟⎢⎥⎣⎦⎝⎠ (6.5b) where No is the thermal noise power density at the antenna port which is equal to 174 dBm/Hz at typical room temperature and NF is the noise figure of the receiver. Assuming that a digital correlator requires a (C/No)min of 35 dBHz and the receiver sensitivity requires 133 dBm. Assuming a 2bit ADC the NF can be calculated to be 6 dB from equation (6.5). This NF includes both receiver front end and A/D converter (ADC)’s NF. As we know, both singlebit and multibit ADC are currently used in GPS receiver. Most lowcost commercial receivers employ 1bit sampling in narrow (i.e., 2 MHz) bandwidth. Highend receivers typically use anywhere from 1.5bit (3 level) to 3bit (8 level) sampling in bandwidth ranging from 220 MHz. Finitebit quantization degrades the signal [48]. The degradations of different bit ADC are listed in Table 6.1. Table 6.1 Signal degradation due to finite quantization in the ADC. 1bit ADC 2bit ADC 3bit ADC Narrow IF bandwidth 3.5 dB 1.2 dB 0.7 dB 6.4.2 Phase Noise 66 In previous section the carriertonoise ratio (C/No) has been used as a figure of merit for the GPS receiver frontend performance. There are several factors degrading C/No, such as finite image rejection ratio (IMRR), phase noise, filter bandwidth and ADC bit resolution. Since in this work we only emphasize on LNA, VCO and mixer design, the effects from IMRR, filter bandwidth and ADC bit resolution are also not considered. The relationship between phase noise and C/No is reviewed. The goal is to find the maximum tolerable phase noise for minimal C/No degradation. Figure 6.9 Reciprocal mixing of the inband thermal noise and phase noise [42]. The phase noise requirement comes from the reciprocal mixing of the phase noise spectrum by the inband thermal noise itself, as seen in Figure 6.9. Multiplication in the time domain corresponds to convolution in the frequency domain, and hence the added noise density due to the phase noise is calculated by [42] ()()()()()()''PNINLOINLOoLONNSNSdNS d ωωωωωωωω∞∞−∞−∞=∗=−=∫∫ ω (6.6) where ()LOSω is the phase noise of LO. The last integral term represents the absolute rms jitter of the local oscillator, normalized to its period, ()2,2LOrmsPNLOrmsoLOTNSdNTωωσ∞−∞Δ⎛⎞=≈⎜⎟⎝⎠∫ ≡ (6.7) The effective C/No at the mixer output can be written by 67 ()21111ooPNoormsoutininLOCCCCNNNNNSdσωω⎛⎞⎛⎛⎞⎛⎞⎛⎞⎜⎟==⋅=⋅⎜⎜⎟⎜⎟⎜⎟⎜⎜⎟+++⎝⎠⎝⎠⎝⎠⎝⎠⎝⎠∫ ⎞⎟⎟ (6.8) In order to obtain less than 0.1 dB loss on C/No, the averaged phase noise should be lower than 80 dBc/Hz [42]. From this limit, it can be inferred that smallsized ring voltage controlled oscillator (VCO) is promising low cost solution, as presented in [49]. However, when considering power consumption, the LC tank VCO is still advantageous since it uses fewer active devices. 6.4.3 Summary Based on the previous discussion, we can conclude the design specifications in Table 6.2. And the gain and noise distribution is summarized in Table 6.3. The parameters in tables will be updated along with the design. Table 6.2 Summary for GPS receiver frontend requirements. Parameters Specification Note Sensitivity 130 dBm At antenna Noise Figure < 9 dB From input of LNA to output of mixer Phase Noise @ <  80 dBc/Hz For VCO. C/No 35 dB For whole GPS receiver frontend ADC 2bit 1.2 dB signal loss Current < 4.5 mA Limited to LNA, VCO and mixers Power < 4.5 mW Limited to LNA, VCO and 68 mixers 69 Chapter 7 UltraLow Power Low Noise Amplifier (LNA) Design 7.1 Introduction The first stage of a RF receiver is a Lownoise amplifier (LNA), whose main purpose is to provide enough gain to overcome the noise of subsequent stages (such as mixer) and linearity while not degrading the signaltonoise ratio. Much valuable research on CMOS LNA design in submicron technologies has been done in recent years: from the topology investigation [50, [51, [52], and the design guidelines [53], to various new ideas on design improvement for low noise figure [54, [55, [56], high power gain [54], low power consumption [55], and high linearity [57]. The frequency range of these CMOS LNA designs is from 900 MHz to 5.2 GHz [58, [59], and the technologies in use is as small as 0.18 um or less. In this chapter, an ultralow power LNA is implemented using SOI deepsubmicron (SOIDSM) 80 nm FinFET technologies. As described in Chapter 5, the doublegate MOSFET (FinFET) is considered as one of the most attractive devices to succeed the planar MOSFET. With two gates controlling the channel, the shortchannel effects are greatly suppressed. The transition frequency of the characterized FinFET transistors is 42 GHz when working in velocity saturation region, and 20 GHz when working in moderate inversion. With the FinFET transistors operating in moderate inversion, the operation current will be several times smaller than that in saturation for a given transconductance. 70 As a result, the FinFET transistors open the door to realize micropower frontend applications. In chapter 6 the GPS receiver architecture, design methodologies, and implementation requirements were discussed. All of those are optimized to meet the low power requirement. In this chapter, the LNA topology choice is illustrated first. Then the ultralow power LNA is proposed. Finally, the performance is presented and compared with previous designs. 7.2 LNA Topology Choice The four most widely used topologies, shown in Figure 7.1, are reviewed. One will be selected for use in the low power GPS receiver. The first topology shown in Figure 7.1(a) uses resistive termination of the input port to provide 50 Ω impedance. The drawback of using of real resistors is that the added resistor contributes its own noise comparable to that of the source resistance [60]. According to the calculation [60], the noise figure will be above 6 dB. It does not satisfy our system requirement for noise figure. 71 Figure 7.1 Common LNA topologies. (a) Resistive termination, (b) 1/ termination, (c) shuntseries feed back, and (d) inductive degeneration. mg Figure 7.1 (b) shows the second topology which uses the source of MOSFET in a commongate (CG) configuration as the input termination. CG topology has good high frequency performance. The minimum theoretically achievable noise figures tends to be around 3 dB or greater in practice. Input impedance is determined by1/. mg Figure 7.1 (c) represents another topology, which utilizes shunt and series feedback to set the input and output impedances of the LNA [61]. It is a broadband amplifier, but it has very high power dissipation compared to others with similar noise performance. For a GPS receiver, a broadband front end is not required and it is desirable to use narrowband technology to save power and reduce interferers. 72 Figure 7.1 (d) employs inductive source degeneration to generate a real term in the input impedance. At the operational frequency, the source inductor provides a stable 50 Ω input impedance. It is the most prevalent topology used for LNA design. And it offers the possibility of achieving the best noise performance of any architecture [50]. Based on above analysis, it seems that the commongate LNA (CGLNA) and commonsource LNA (CSLNA) topology is good candidate for GPS receiver. The detailed analysis and comparison of CGLNA and CSLNA is reviewed below. 7.2.1 Commonsource LNA (CSLNA) The CSLNA is based on the commonsource with source inductive degeneration amplifier. Figure 7.2 shows the schematic of a popular cascade singleended CSLNA. At the operation frequency, the input inductors Ls provides stable 50 Ω input impedance. The input inductors Lg, Ls and input device gatetosource capacitance, Cgs provide the operational frequency for CSLNA. Figure 7.2 CSLNA Schematic Diagram. A simple analysis of the circuit depicted in Figure 7.2 shows that the input impedance of the circuit is given by (7.1) when neglecting the M1 draingate overlap 73 capacitance, and the inductor parasitic elements toward the substrate (Cox, Rsi and Csi in Figure 3.3(a)) ()1mingssgLgLsgsgsgZjLLLRRRjCCωω=++++++ (7.1) where Cgs amd gm are respectively the gatesource capacitance and the transconductance of M1 and Rg the gate resistance of M1. RLg and RLs represent the parasitic series resistance of Lg and Ls, respectively. At resonance, the imaginary term of Zin will be zero, which gives ()10gsgsLLCωω+−= (7.2) From (7.2) the center frequency can be derived, ()1ogsgsLLCω=+ (7.3) The real part of the input impedance is ,minrealgLgLssgLgLsTTgsgZRRRLRRRLsLsCωω=+++≈+++≈ (7.4) where Tω is an approximation of the transition frequency of M1. Using (7.4) the inductance of source inductor can be determined. Once Ls has been determined Lg can be calculated by (7.3). One of the most attractive advantages of this topology is that the inductor used to match the input impedance is noiseless, unlike the topology shown in Figure 7.1 (a), which employs a noisy resistor in the signal path to provide the 50 Ω termination resistance. This explains the low noise performance and popularity of the inductively degenerated CSLNA. 74 The effective smallsignal transconductance of the input transistor is a parameter which accounts for the transconductance for input transistor and input matching network. ()1mTmmogssTsTsossgGgQCRLLRRωωωωω===+⎛⎞+⎜⎟⎝⎠ (7.5) Note that the input matching circuit is a pure series RLC resonant circuit. At resonance the voltage across Cgs is enhanced by Q times, where Q is the quality factor of input matching RLC network. In other words, the Q enhancement mechanism provides a free gain of Q for both the input signal and the noise from the source resistance Rs. The added gain from the input matching circuit helps to suppress channel noise. If the input is matched to Rs, we have 12TmsoGRωω⎛=⎜⎝⎠ ⎞⎟ (7.6) It is worth noting that the effective transconductance Gm is only related to the ratio of Tω to oω and is independent on the MOSFET smallsignal transconductance. mg The gatetodrain capacitance Cgd provides a feedthrough path from input to output, decreasing the reverse isolation. In addition, the miller effect of Cgd provides a shunt current branch at the input, which further complicates the input matching. One should add a cascode stage to mitigate the Miller effect of Cgd and improve reverse isolation. Next, the noise performance of CSLNA is analyzed. Starting with the noise model of a MOSFET, as shown in Figure 7.3, we surmise that their main noise sources are the thermal channel noise and the induced gate noise. 75 Figure 7.3 MOSFET equivalent noise model. The channel thermal noise id shows a white power spectral density described by 204ddikTgγ= Δf (7.7) where is Boltzmann’s constant,is the zerobias drain conductance, k0dgfΔis the bandwidth of interest and γis a biasdependent factor that, for long channel devices, satisfies the inequality 213γ≤≤ (7.8) the value of 2/3 holds when the device is in saturation mode and the value of one is valid when the drainsource voltage is zero. For shortchannel devices, however, γis much greater than 2/3 for devices operating in saturation [50]. For the present there is no standard γ value for devices operating in moderate inversion. In addition to channel thermal noise id, a companion noise current ig at the gate of the MOSFET, which is known as induced gate noise, has been observed in both theory and experiment, 24gikTgδ=g f Δ (7.9) 76 ()205gsgdCggω= (7.10) where δ is another biasdependent empirical parameter, classically equal to 4/3 for longchannel devices. Unlike the white noise spectrum of the channel thermal noise, induced via the gate noise has blue spectrum frequency. The gate noise is partially correlated with the drain noise, with a correlation coefficient given by [62] *220.395gdgdiicii=≈ j (7.11) Figure 7.4 Smallsignal model for noise calculation of CSLNA. After determining the noise source of MOSFET, we will derive the noise factor of the CSLNA. To obtain the expression for noise factor, it is instructive to calculate the transfer functions of the different noise source in the CSLNA [63]. The smallsignal circuit used in the computation is shown in Figure 7.4. In this CSLNA noise model five noise sources are considered, input impedance noise, series resistance noise from gate inductor, gate resistance noise from input MOS device, channel thermal noise of MOS device and induced gate current noise. The noise factor is derived according to its definition, that is, the ratio of total output noise power to the output noise power due to input source impedance, as shown 77 ()222111155LggTRRFRsRsQγωδαδα Q 2 c αωγ γ ⎡⎤⎛⎞⎢⎥=++++++⎜⎟⎢⎥⎝⎠⎣⎦ (7.12) where 0mdggα≈ (7.13) For longchannel device, α= 1. For shortchannel device,1α≤. 7.2.2 Commongate LNA (CGLNA) Figure 7.5 shows a CGLNA where the gate terminal is shorted to an AC ground and the input signal is injected at the source terminal. The resistance looking into the source terminal is about 1mg, which provides the input 50 Ω match. Unlike CSLNA, there is no Miller effect associated with Cgd in CGLNA, which results better reverse isolation. RSVinZinVbiasM1Lload Figure 7.5 the CGLNA schematic diagram. The effective smallsignal transcondance of the input transistor of CGLNA is 12msGR= (7.14) 78 However, the CGLNA suffers from the presence of a noisy channel conductance in the signal path, which attenuates the noise performance. It can be shown that under perfect input matching, the CGLNA has the following noise factor [60] 215TFγδαωαω⎛⎞=++⎜⎟⎝⎠ (7.15) In the above equation, the third term is from the contribution of the induced gate noise, which is negligible compared to contribution of channel noise. Neglecting gate noise for a CGLNA is reasonable approximation since the gate noise is not amplified, unlike it in CSLNA. Therefore, the noise factor of CGLNA is approximated by 1Fγα=+ (7.16) In CSLNA we can not make this approximation since the gate noise is amplified and becomes comparable to channel noise. 7.2.3 Comparisons of CSLNA and CGLNA Based on the above discussion, the detailed comparison is listed in Table 7.1. Table 7.1 The comparison between CSLNA and CGLNA (“+” indicates better, “” indicates worse). CSLNA CGLNA Comments Gain + – 01122TCSLNACGLNAssGGRRωω⎛⎞=>=⎜⎟⎝⎠ Noise Figure + – Discussed above Input matching – + CGLNA has lower Q parallel resonant network. Reverse isolation – + Cgd in CSLNA provides a feedforward path between input and output. 79 In this work the NF for receiver frontend requirement is less than 6 dB in order to obtain the desired GPS receiver sensitivity, as discussed in Chapter 6. So the topology CSLNA is used to achieve low noise and low power GPS receiver front end. Once selecting the CSLNA topology, the next question is to take either a singleended or differential architecture. The signalended LNA architecture has at least one important shortcoming, and that is sensitivity to parasitic ground inductance. There are several advantages in using a differential LNAs. Firstly, the use of Gilbert mixers and the lowIF architecture requires a differential feed source. If the singleended is taken we need to add a Balun to generate the differential signal. The Balun itself has about 0.5 dB loss. Secondly, the virtual ground formed at the tail removes the sensitivity to parasitic ground inductance, which makes the real part of the input impedance purely controlled by the source degeneration inductance (Ls). Thirdly, the differential amplification of signal ensures attenuation of the common mode signal. But for equal total power consumption, the noise figure of differential LNA is higher than its singleended counterpart. Specifically, the power consumed is twice that of a singleended LNA to achieve the same noise figure. Since it is hard to tell which architecture is better for this application, both architectures will be taken to implement the ultralow power GPS receiver frontend circuits. Next the ultralow power FinFET differential LNA design is described. The singleended LNA is just the half circuit of differential LNA. It has the same NF but only consume half power of differential LNA. 80 7.3 Circuit Design The LNA design starts from noise optimization because of the tight noise requirement. The input devices are required to work in moderate inversion region to reduce amplifier drain current with the exception of the tail current source. All the formula used to estimate the noise is for MOSFET apply in moderate inversion. Starting from the noise analysis, we found the minimal transcondance to achieve the lowest noise figure. Once gm is found to be 20 mS, the drain current can be determined by referring the inversion coefficient curve with IC equal 0.1 to 1 in Figure 7.6. The curve in Figure 7.6 is drawn for 80 nm FinFET transistors with the description in 2.3.1. The mDgI of around 20 to 40 is achievable in this range. Taking the average value 30, we can get 30666DmIg==uA. The tail current will be twice the ID, 1.3 mA. The aspect ration of M1 and M2 can be calculated by choosing bias current: ()DtIWLIIC= (7.17) where IC is the desired inversion coefficient, which is about 0.15. It is specific current, (7.18) 22tnoxInCUμ= T which is about 1.46 uA for 80 nm device. The W/L is determined about 3000. Knowing channel length equal to 80 nm the width of input device is determined to be 240 um. 81 105104103102101100101102101100101102gm/IDInversion Coefficient (IC)L=0.08um Figure 7.6 gm/ID versus inversion coefficient curve. Knowing gm, device size and Cgs, the transition frequency of input device is mTgsgCω≈ (7.19) 82 VddLdLsLgM1M3LdLsLgM2M4Vbias1Vbias1Vbias2Vbias2IF+RF+RFIF Figure 7.7 Proposed differential LNA schematic. The source inductance can be determined once the source resistance Rs is set to 50 Ω. ssTRLω= (7.20) Lg can be determined by 201gsgsLCω=−L (7.21) Where 0ω is the center frequency of GPS L1 band. 83 The complete LNA schematic is shown in Figure 7.7. All passive components values in design are summarized in Table 7.2. All active devices are summarized in table 7.3. Table 7.2 Differential LNA passive components values. Ls Lg Ld 100 pH 20 nH 15 nH Table 7.3 Differential LNA active components values. Devices Threshold voltage Sizing (um/um) IC Overdrive Voltage M1 M4 0.33 V 250/0.08 0.12  15 mV 7.4 LNA Performance Periodic SteadyState (PSS) and SParameter (SP) simulation are adopted to measure the gain, noise and linearity performance separately. In SP simulation, the voltage gain of LNA is determined by plotting S21 versus frequency. Figure 7.8 shows the maximum voltage is 21 dB at 1.57 GHz. And the S12, S11 and S22 are 30 dB, 15 dB and 4 dB, respectively, as shown in Figure 7.9 and Figure 7.10. The noise performance is measured by NF shown in Figure 7.11, which is about 2.6 dB at 1.57 GHz. If the gate induced noise is counted it will reach 3.4 dB which is dependent on device model used. Stability measurement of LNA is presented in Figure 7.12. 84 The LNA’s linearity can be measured by 1dB compression point, as shown in Figure 7.13. The 1dB compression point is 35 dBm. The performance summary for proposed LNA is listed in Table 7.4. Compared with the differential LNA designs previously published, the resulting LNA consumes only 1.08 mW with 1 V supply voltage. Figure 7.8 Voltage gain of differential LNA. Figure 7.9 S12 of differential LNA. 85 Figure 7.10 S11 and S22 of LNA. Figure 7.11 Noise Figure of LNA. 86 Figure 7.12 Stability measurement of LNA Figure 7.13 1dB compression point measurement of LNA 87 Table 7.4 Ultralow power LNA performance summary Technology 0.08 um FinFET Supply Voltage (Vdd) 1 V DC Current 1.44 mA Power Consumption 1.44 mW Threshold Voltage 0.33 V Transition frequency 18 GHz Operation Frequency 1.57 GHz S21, S11, S22 20 dB, 15 dB, 4 dB Noise Figure 3.4 dB 1dB compression 35 dBm Power Consumption 1.44 mW 88 Chapter 8 Micropower RF Voltage Controlled Oscillator Design 8.1 Introduction Voltage controlled oscillators (VCOs) are essential building blocks of modern communication systems and are worked with other building blocks to establish phase lock loop (PLL) to generate stable local oscillation signal, which is provided to the ports of mixer in a typical transceiver architecture to translate data between baseband and frequencies suitable for wireless transmission. In a PLL, all building blocks such as VCO, phase detector and loop filter contribute phase noise at the output. For a well designed PLL, the phase noise of VCO is the dominant source of phase noise [64]. Therefore, in the following discussion, the phase noise of VCO is emphasized. The basic LC oscillator topology is widely used in RF receiver design due to its superior phase noise performance. Consequently, we focus our discussion on LC oscillators. In this chapter, following the oscillation fundamental of oscillator, the topologies of oscillators are compared. Then the proposed VCO design procedures are presented. Finally, the performance of VCO is shown in figures and summarized in table. 8.2 Oscillators Fundamental 8.2.1 Feedback Oscillator Model 89 An oscillator can be viewed as a feedback system as shown in Figure 8.1 where the transfer function from Vin(s) to Vout(s) is ()()()1()outinVsHsVsHs=+ (8.1) For the oscillation to begin, a loop gain of unity or greater is necessary. Oscillation occurs for the condition0()Hjω 1 =. Even without an input, i.e., Vin(s) = 0, the oscillation is selfsustained. To maintain constant amplitude, there are two necessary conditions that must be met at0ω. 00()1()180oHjHjωω=∠= (8.2) Known as Barkhausen’s criteria, these conditions are necessary but not sufficient [65]. In order to ensure oscillation in the presence of temperature and process variations, we typically choose the loop gain to be at least twice or three times the required value. Figure 8.1 oscillator viewed as feedback system. An LC resonant tank is an integral component of LC oscillator circuit in Figure 8.1. It functions as a frequency selective network to eliminate highorder harmonics and thus to stabilize the oscillation frequency, as shown in Figure 8.2. 90 Figure 8.2 Feedback model for oscillator with LC resonant tank. 8.2.2 OnePort Oscillator Model Most oscillators employed in RF applications use LC resonators. They are known to provide high spectral purity and lower phase noise than other types such as ring oscillators, etc. [66]. Monolithic inductors have gradually appeared in bipolar and CMOS technologies in the last decade, which makes it possible to design oscillators based on passive resonant circuits. As shown in Figure 8.3. An inductor L placed in parallel with a capacitor C, building a parallel resonance LC tank, which resonates at a frequency 1LCω= (8.3) Since the LC tank network is composed only of reactive components, the oscillating signal ideally maintains its oscillation amplitude without attenuation. The energy in the LC resonator transfers back and forth between the inductor and the capacitor in the form of the magnetic and electric energy without loss due to power dissipation. In practice, however, the quality factors of the inductor and the capacitor are 91 finite. As a result, this leads to a practical parallel RLC network as shown in Figure 8.3(b). Quality factor Q of this network is defined as: 00RQRL Cωω== (8.4) At this frequency, the impedance of the inductor,jLω, and the capacitor, ()1jCω, are equal and opposite, thereby, yielding an infinite impedance, in theory. The circuit in Figure 8.3 (a) has an infinite quality factor, Q. In practice, inductors (and capacitors) suffer from resistive component, Rp. In order to sustain the oscillation, a practical tank network needs an active circuit that provides a negative resistance, Ra, to cancel out the positive loss resistance of the tank. Such a topology is called oneport oscillator. (a) ideal (b)practical (c) negative R Figure 8.3 LC tank. 8.3 Oscillator Topology Comparison In this section, several oscillator topologies will be compared with an emphasis on their phase noise and power consumption. 92 Figure 8.4 the typical crosscouple oscillator. Figure 8.4 shows the NMOSonly crosscoupled oscillator topology, widely used in highfrequency integrated circuits due to the ease of implementation and differential operation [67, [68, [69]. It can be shown that the smallsignal impedance looking into the drains of M1 and M2 is 2mg−assuming the parasitic capacitance is neglected. To enable oscillation, the negative smallsignal conductance added by the crosscoupled transistor pair should overcome the loss in Rp, that is 1mpgR> or 1mpgR> (8.5) Figure 8.5 shows the complementary version using both NMOS and PMOS transistors. This topology provides a larger tank amplitude for a given tail current in the current limited regime defined in [68]. Since the PMOS is used in this topology, the 93 oscillation frequency is limited by the PMOS. In this work pchannel FinFET transistors can not provide enough bandwidth in moderate inversion. Thus this topology is not considered. Figure 8.5 The complementary crosscoupled oscillator. Figure 8.6 depicts the singleended Colpitts oscillator topology. Compared to crosscoupled VCO, the Colpitts topology features superior phase noise because noise current from the active devices is injected into the LC tank during the tank voltage when the impulse sensitivity is low [70, [71]. The negative conductance is formed using transistor M1 and capacitive divider C1 and C2 in a positive feedback arrangement. Its smallsignal impedance looking into the drain of M1 is calculated using test voltage divided by test current. It can be shown that the negative conductance loading the tank is ()12212mgCCCC−+. Therefore, the startup condition for Colpitts oscillator is 94 ()122121mpgCCRCC>+ or ()21212mpCCgRCC+> (8.6) For a typical case, (8.6) becomes. Comparing to (8.5), we conclude that Colpitts oscillator has more difficult startup condition than the conventional crosscoupled LC oscillator for a given transconductance, i.e., higher power consumption is needed to ensure reliable startup in the presence of process, voltage or temperature variations. And the lack of differential outputs needed to suppress commonmode coupling has hindered its usage in CMOS. 2CC= 1 4mpgR> Figure 8.6 The typical Colpitts oscillator. Figure 8.7 shows a differential Colpitts VCO. With a smallsignal analysis, the startup condition for the differential Colpitts oscillator is given by ()212122mpCCgRCC+> (8.7) 95 Compared to (8.6), the effective smallsignal transcondance is doubled, the startup condition is also relaxed by a factor of two. In a conventional Colpitts oscillator, the tail current is always ON. To reduce power consumption, a switching current source can be employed [72]. Power consumptions is reduced at the expense of added noise from the tail device. The idea is that since in a Colpitts oscillator the MOSFET is on for less than half of a cycle, two switches can be used to steer one current source to the two MOSFETs while sustaining oscillation, shown in Figure 8.8 [73]. Figure 8.7 The typical differential Colpitts oscillator. Although differential Colpitts oscillator has superior phase noise performance than crosscouple differential, it has greater power than crosscouple differential oscillator [72]. Since in this work low power consumption is our research goal and the crosscoupled oscillator already supplies enough phase noise and cost less power than differential Colpitts oscillator, the crosscoupled oscillator is taken to implement the ultralow power VCO. 96 Figure 8.8 The differential Colpitts oscillator with currentswitching technique. 8.4 Oscillator Circuit Design With the VCO topology selected, the design procedures are described in this section. The proposed VCO schematic diagram is shown in Figure 8. 10. Starting with the oscillation frequency equation given in (8.1), we take 1.57 GHz as the target frequency. In Chapter 3, a monolithic model was developed for the onchip inductor with substrate removed. The model is valid for the number of turns as large as 4.5. In this design we will use the complete inductor model for accuracy, where all substrate losses are taken into account. As described in Section 8.2, the crosscoupled pair must provide enough negative resistance to cancel the tank losses and allow oscillation to start up. This negative resistance equals 1,21mg− for half crosscoupled pair. The required for startup sets a lower limit on the current consumption of oscillator. To determine the necessary for startup, the tank losses (RmgmgP) must be calculated from the inductor model. In Chapter 3, the calculated QL was shown to be 97 approximately 10 at 1.5 GHz for an inductor with a substrate. At the resonant frequency, the LC tank may be modeled as depicted in Figure 8.3, where the tank losses are included in the resistance Rp. The equivalent parallel resistance at resonance may be calculated by taking the capacitor as lossless and calculating the parallel resistance Rp for an inductor with finite Q given by the overall tank quality factor, 2pL s RQR≈ (8.8) The required for startup is mg 1mpgR≥ (8.9) For a given operating frequency, it is desirable to use the inductor in the LC tank which has largest pR value. The Table 8.1 shows the inductance, series resistance and Q of inductors with different number of turns at 1.5 GHz. Table 8.1 Onchip inductors specifications at 1.5 GHz. No. turns L (nH) Rs (Ω) Q 1.5 1.34 1.8 7.28 2.5 2.83 3.34 8.39 3.5 6.4 6.15 10.36 4.5 11.52 9.65 11.88 With Table 8.1, the 4.5 turn inductor is taken since it has largest RP value. In practice, the size of the inductor is usually limited by the difficulty of implementing large spiral coils onchip. On the other hand, the critical transconductance is inversely proportional to tank 98 quality factor, so an improvement in inductor Q reduces startup current requirements and lowers power consumption. As described in Chapter 3, inductors large than 12 nH are not normally integrated on chip. RP is approximately 1000 Ohm at 1.57 GHz for 4.5 turns inductor. Therefore, the minimal requirement of is approximately 1 mS. In order to ensure reliable startup, the transconductance is set to 2 mS. mg105104103102101100101102101100101102gm/IDInversion Coefficient (IC)L=0.08um Figure 8.9 Inversion coefficient for L=80 nm FinFET transistor. To optimize the transcondance for minimal bias current, devices M1 and M2 are designed to operate with inversion coefficient between 0.1 and 1. This is the moderate inversion for transistors. Referring to Figure 8.9, mDgI of around 20 to 40 is achievable in this range. Taking the average value 30, we can get 3066DmIg==uA. The tail current will be twice the ID, or 132 uA. The aspect ration of M1 and M2 can be calculated by choosing bias current: ()DtIWLIIC= (8.10) 99 where IC is the desired inversion coefficient, which is about 0.15. It is specific current, which is about 1.46 uA for 80 nm device. So the W/L ratio is determined around 350. The total bias current sourced by M3 is approximately 130 uA. In order to maintain stable tail current a longchannel device is chosen and operation in saturation region is selected for accuracy. The width of M3 is calculated to be about 20 um. All the devices sizing and IC is shown in table 8.2. Table 8.2 Device sizing and IC for oscillator transistor. Device Threshold voltage Sizing (um/um) IC Overdrive voltage M1, M2 0.33 V 30/0.08 0.12 25 mV M3 0.5 V 20/1 10 0.2 V Next, the voltage controlled capacitor design is selected. In this work, the FinFET varactors are used to achieve frequency sweep. All the varactors are nchannel FinFET transistors that have a steplike CV characteristic. Referring to Figure C.3 in Appendix C: “CV characteristic of FinFET”, the FinFET capacitance changes from 2 fF/um2 to 13 fF/um2 with gate voltage swept from 0.5 V to 0.5 V. In order to center the oscillation frequency at 1.57 GHz two varactors are connected in parallel which has width 45 um and length 1um. Its capacitance at zero bias is around 470 fF, and its swept capacitance ratio is 6.5. 8.4 VCO Performance 100 Figure 8.10 Micropower VCO schematics. The completed VCO design is shown in Figure 8.10. Its tuning range is 720 MHz wide around the center frequency of 1.57 GHz (i.e., 45.7%) without considering process, voltage and temperature (PVT) variation, as shown in Figure 8.11. Figure 8.12 shows that the differential output oscillation signal amplitude is around 700 mV, that is, around 350 mV peaktopeaks for single end output. With power supply voltage of 1 V, the phase noise of the VCO is 112 dBc at 1 MHz offset from 1.57 GHz, shown in Figure 8.13. Compared with the VCO design published before, this VCO consumes only 128 uW with 1 supply voltage. 101 0.50.40.30.20.10.00.10.20.30.40.51.31.41.51.61.71.81.92.02.12.2 Output Frequency (GHz)Vcont (V) Figure 8.11 Simulated tuning characteristics of the VCO. Figure 8.12 Output LO signal magnitude versus frequency. 102 Figure 8.13 VCO Phase noise versus frequency. Table 8.3 Summary of VCO performance. Parameters Value Supply voltage 1 V Power Consumption 128 uW Frequency tuning range 1.382.1 GHz LO Vpp 350 mV Phase Noise 111 dBc/Hz @1 MHz offset 103 Chapter 9 Ultralow Power Mixer Design 9.1 Introduction The rapid growth of portable wireless communication systems, such as wireless (cordless and cellular) phones, GPS, wireless local area network (LAN), etc., has increased the demand for lowcost and high performance frontend receivers. Mixers are used for frequency conversion and are the critical components in modern radio frequency (RF) systems which are commonly used to down convert frequencies to achieve frequency translation. The motivation for this translation stems from the fact that filtering out a particular RF signal channel centered among many densely populated, narrowly spaced neighboring channels would require extremely high Q filters. A mixer converts an RF signal at a high frequency into a signal at lower frequency to make signal processing easier and less power consumptive. One of the best known architectures is the downconversion heterodyne receiver, schematically depicted in Figure. 9.1. Here the received RF signal after preamplification in a lownoise amplifier is supplied to a mixer. It is then mixed with local oscillator (LO) frequencyLOf. The signal obtained after the mixer contains the frequenciesRFLOff±, as well as the input signals at RFf andLOf. 104 With a lowpass filter (LPF) or bandpass filter (BPF), the lower frequency componentRFLOff−, known as the intermediate frequency (IF), is selected for further processing. RFLOff±RFfLOfIFf Figure 9.1 The heterodyne receiver system with a mixer. In this chapter, following the fundamentals of mixing, the mixer topology choice is made based on our application. Then the design procedure is discussed to achieve lowpower consumption. Finally, the proposed mixer performance is presented. 9.2 Mixer Fundamentals The ideal mixer is a device which multiplies two input signals. If the inputs are sinusoids, the ideal mixer output is a signal that contains both the sum and difference frequencies given by ()((cos)(cos)coscos2RFLORFLORFLOABAtBttωωωωωω )t ⎡⎤=−++⎣⎦ (9.1) Typically, either the sum or the difference frequency is removed with a filter. If the LO amplitude is constant, any amplitude modulation in the RF signal is also transferred to the IF signal. Having recognized the fundamental role of multiplication, the most important characteristics of mixers are discussed next. 9.2.1 Conversion Gain 105 The gain of mixers must be carefully defined to avoid confusion. The voltage conversion gain of a mixer is defined as the ratio of the root mean square (rms) voltage of the IF signal to the rms voltage of the RF signal. The power conversion gain of a mixer is defined as the IF power delivered to the load divided by the available RF power from the source. If the input impedance and the load impedance of the mixer are both equal to the source impedance, then the voltage conversion gain is equal to power conversion gain in decibels. In this work the LNA output impedance is not matched to source impedance. Thus, the voltage
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Title  Ultralow Power Rf Receiver Based on Doublegate Cmos Finfet Technology 
Date  20060501 
Author  Wang, Jianning 
Department  Electrical Engineering 
Document Type  
Full Text Type  Open Access 
Abstract  In this research, design approaches and methodologies were presented to realize the ultralow power RF receiver frontend circuits. Moderate inversion operation was explored as a possible method of reducing power consumption along with the use of low supply voltage. The research is firstly concentrated on passive and active devices modeling. One of the most commonly used passive devices is onchip inductor. Onchip spiral inductor model was developed firstly. Compared to the model developed by others, this model can predict the behavior of the inductors with different structural parameters over a board frequency range (from 0.1 to 10 GHz). Then the SOI varactor model was developed based on our measurement and extraction. Besides the passive devices modeling, a new most promising MOSFET candidate, FinFET, was characterized at GHz frequency range. Based on the measurement results, we found the FinFET transistors did have superior performance over bulkSi CMOS technology. And an RF circuit model of FinFET was developed followed that, which was published in Electronics Letters. To my best knowledge, this was the first RF FinFET model published world wide at that time. It provides the basic idea about how to model this new structure MOSFET. Based on the passive and active device models developed, Global Positioning System (GPS) receiver front end circuits were designed and measured. Comparing to the previous designs with the same constrains, the ultralow power GPS receiver building block circuits in this research have much less power consumption than the best design published before. 
Note  Dissertation 
Rights  © Oklahoma Agricultural and Mechanical Board of Regents 
Transcript  AN ULTRALOW POWER RF RECEIVER BASED ON DOUBLEGATE CMOS (FINFET) TECHNOLOGY By JIANNING WANG Bachelor of Science Beijing University of Aeronautics & Astronautics Beijing, China 1997 Master of Science Beijing University of Aeronautics & Astronautics Beijing, China 2000 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY May, 2006 AN ULTRALOW POWER RF RECEIVER BASED ON DOUBLEGATE CMOS (FINFET) TECHNOLOGY Thesis Approved: Dr. Chris Hutchens Thesis Advisor Dr. Yumin Zhang Dr. Weili Zhang Dr. Jack Cartinhour Dr. Gordon Emslie Dean of the Graduate College ii ACKNOWLEDGMENTS The completion of this dissertation marks the end of my formal education. Throughout my life, there were numerous supports that are given to me unconditionally and lovingly. At this moment, I will take this opportunity to express my sincere gratitude to who have supported and loved me all along. To begin, I thank my parents for their deep love and full supports. Their caring always extends to the deepest of my heart. I would not be able to achieve this milestone of my life without them. Especially, I would like to express my deep appreciation to my wife, Beining Nie, who has accompanied and encouraged me in many aspects of my life these years. Her supports were the driving force for the writeup of this dissertation. Being in MixedSignal VLSI Lab has definitely been a lot of fun, and an unforgettable part of my experience. I learned as much in the MSVLSI Lab as I did in the classroom. I would like to thank all the past and present members of the MSVLSI Lab, especially Dr. Liu. He gave me a lot of supports in the lab. I’ll never forget all these labmates, Narendra, Venket, Vijay, Vanay, Barad, Srini, Vamsi, Henry, Lisa, and Shooi. I would also like to thank the faculty of the ECEN Department at OSU, especially Dr. Weili Zhang, and Dr. Jack Cartinghour of Electrical Engineering Technology for being on my Graduate Committee. In addition, I thank Space and Warfare iii (SPAWAR) Systems Center (formerly NRaD), San Diego, CA for its support of this project. Last and foremost, I would like to thank Dr. Chris Hutchens and Dr. Yumin Zhang. I appreciate all the opportunities and assistance they have provided me over the past three years. Their numerous guidance and advice have deeply enhanced my chances for success at OSU and my subsequent career and life. Thank you! iv TABLE OF CONTENTS Chapter Page CHAPTER 1.......................................................................................................................1 OBJECTIVE......................................................................................................................1 1.1 Motivation.....................................................................................................................1 1.2 Overview.......................................................................................................................1 CHAPTER 2.......................................................................................................................3 LOW POWER TECHNIQUES..........................................................................................3 2.1 Introduction...................................................................................................................3 2.2 Low Supply Voltage Technique...................................................................................3 2.1.1 Opportunities for Reduced Supply Voltage...........................................................4 2.2.2 Challenges for Low Power Supply........................................................................5 2.3 Subthreshold Operation Technique...............................................................................5 2.3.1 Fundamental of Subthreshold Operation...............................................................6 2.3.2 Advantages of Subthreshold Operation.................................................................8 2.3.3 The challenges of Subthreshold Operation............................................................9 CHAPTER 3.....................................................................................................................13 INTEGRATED INDUCTORS.........................................................................................13 3.1 Introduction.................................................................................................................13 3.2 Structure and Layout...................................................................................................13 3.3 Inductor Model and Parameterextraction Method.....................................................15 3.4 Results and Model Verification..................................................................................18 3.4.1 Series Inductance (Ls)..........................................................................................18 3.4.2 Series Resistance (Rs)..........................................................................................18 3.4.3 Series Capacitance (Cs).......................................................................................19 v 3.4.4 Model Verification...............................................................................................19 3.5 Conclusion..................................................................................................................23 CHAPTER 4.....................................................................................................................24 INTEGRATED VARACTOR..........................................................................................24 4.1 Introduction.................................................................................................................24 4.2 Structure and Layout...................................................................................................25 4.3 Model Parameter Extraction and Model Verification.................................................27 4.4 Layout Summary and Usage.......................................................................................32 4.4.1 Capacitance Calculation and Length choice.................................................33 4.4.2 Resistance Estimation...................................................................................34 4.4.3 Inductance Estimation...................................................................................35 4.5 Conclusion..................................................................................................................35 CHAPTER 5.....................................................................................................................37 FINFET TRANSISTORS AND MODELING.................................................................37 5.1 Introduction.................................................................................................................37 5.2 Performance of FinFET Transistors............................................................................40 5.2.1 DC Measurements................................................................................................41 5.2.2 AC Measurement.................................................................................................45 5.2.3 Noise Measurement.............................................................................................47 5.2.4 Capacitance Measurement...................................................................................47 5.3 FinFET Model.............................................................................................................48 5.3.1 FinFET SmallSignal Model................................................................................48 5.3.2 FinFET BSIMSOI Model....................................................................................54 5.3.3 FinFET Model Summary.....................................................................................54 5.4 Summary.....................................................................................................................56 CHAPTER 6.....................................................................................................................58 vi GPS RECEIVER DESIGN...............................................................................................58 6.1 Introduction.................................................................................................................58 6.2 GPS Receiver Architectures.......................................................................................59 6.2.1 Typical GPS Receiver Architectures...................................................................59 6.2.2 LowIF Architecture............................................................................................61 6.3 Receiver System Design.............................................................................................62 6.4 Receiver Implementation Requirements.....................................................................64 6.4.1 Noise Figure.........................................................................................................64 6.4.2 Phase Noise..........................................................................................................66 6.4.3 Summary..............................................................................................................68 CHAPTER 7.....................................................................................................................70 ULTRALOW POWER LOW NOISE AMPLIFIER (LNA) DESIGN...........................70 7.1 Introduction.................................................................................................................70 7.2 LNA Topology Choice...............................................................................................71 7.2.1 Commonsource LNA (CSLNA).........................................................................73 7.2.2 Commongate LNA (CGLNA)............................................................................78 7.2.3 Comparisons of CSLNA and CGLNA................................................................79 7.3 Circuit Design.............................................................................................................81 7.4 LNA Performance.......................................................................................................84 CHAPTER 8.....................................................................................................................89 MICROPOWER RF VOLTAGE CONTROLLED OSCILLATOR DESIGN...............89 8.1 Introduction.................................................................................................................89 8.2 Oscillators Fundamental.............................................................................................89 8.2.1 Feedback Oscillator Model..................................................................................89 8.2.2 OnePort Oscillator Model...................................................................................91 8.3 Oscillator Topology Comparison................................................................................92 vii 8.4 Oscillator Circuit Design............................................................................................97 8.4 VCO Performance.....................................................................................................100 CHAPTER 9...................................................................................................................104 ULTRALOW POWER MIXER DESIGN....................................................................104 9.1 Introduction...............................................................................................................104 9.2 Mixer Fundamentals.................................................................................................105 9.2.1 Conversion Gain................................................................................................105 9.2.2 SSB and DSB Noise Figure...............................................................................106 9.2.3 Isolation and Linearity.......................................................................................107 9.3 Mixer Topology Comparison....................................................................................107 9.3.1 Passive Mixer.....................................................................................................108 9.3.2 Active Mixer......................................................................................................109 9.4 Circuit Design...........................................................................................................111 9.5 Mixer Performance...................................................................................................113 CHAPTER 10.................................................................................................................116 CONCLUSIONS.............................................................................................................116 10.1 Research Summary.................................................................................................116 10.2 Future Work............................................................................................................122 APPENDIX A.................................................................................................................125 INTEGRATED DIFFERENTIAL INDUCTORS AND TRANSFORMERS................125 APPENDIX B.................................................................................................................128 FINFET BSIMSOI MODEL EXTRACTION................................................................128 APPENDIX C.................................................................................................................132 viii GATECHANNEL CAPACITANCE CHARACTERISTICS IN NANOSCALE FINFET........................................................................................................................................132 ix LIST OF FIGURES Figure Page Figure 2.1 Schematic of low power supply LO..................................................................5 Figure 2.2 gm/ID and fT for a modern CMOS 0.13um process[Pletcher, 2004 #78]..........11 Figure 2.3 Comparision of Tf with technology scaling[Pletcher, 2004 #78]..................11 Figure 3.1 (a) Structural parameters of an onchip spiral inductor, (b) Die photograph of the spiral inductor.............................................................................................................15 Figure 3.2 Crosssection of inductor.................................................................................15 Figure 3.3 Equivalent circuit for models: (a) with substrate, (b) without substrate, (c) equivalent circuit at low frequency...................................................................................16 Figure 3.4 (a) Measured (dot) and simulated (line) sparameter, n=2.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................20 Figure 3.4 (b) Measured inductance as a function of frequency. n=2.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................21 Figure 3.5 (a) Measured (dot) and simulated (line) sparameter, n=4.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................21 Figure 3.5 (b) Measured inductance as a function of frequency. n=4.5, w=25um, s=3um, and IDOD=0.5..................................................................................................................21 Figure 3.6 Comparison between measurement data and model simulation......................22 Figure 3.7 Measured (dot) and simulated (line) sparameter, n=5.5, w=25um, s=3um, and IDOD=0.5.........................................................................................................................23 Figure 4.1 The crosssection of the single varactor..........................................................25 Figure 4.2 The micrograph of the varactor under test......................................................26 Figure 4.3 (a) Capacitance versus frequency and (b) quality factor versus frequency.....27 Figure 4.4 The equivalent varactor circuit........................................................................28 Figure 4.5 Capacitance versus length at VG=0V..............................................................28 Figure 4.6 Capacitance and Resistance change verse gate bias voltage as extracted from the varactor parametrics....................................................................................................30 Figure 4.7 L=0.8um Vg=0V symbol is measured data and line is the simulated.............31 Figure 4.8 L=1um Vg=0V symbol is measured data and line is the simulated...............32 Figure 4.9 Comparison of the measured (symbol) and simulated (solidline) CV characteristics for the L=0.8um and L=1um devices........................................................32 Figure 5.1 Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or: GAA structure); 5) Pigate MOSFET. [Park, 2001 #48]..........................................................................................................................................37 Figure 5.2 The possible Doublegate MOSFET orientations on silicon[Wong, 1997 #49]...........................................................................................................................................38 Figure 5.3 The 3D FinFET..............................................................................................39 x Figure 5.4 Scanning electron microscope picture of the cross section of FinFET (compliments of SPAWAR SC San Diego)......................................................................39 Figure 5.5 FinFET Process steps; from [Hisamoto, 2000 #45]........................................40 Figure 5.6 FinFET drain current versus drain voltage at various gate voltages...............41 Figure 5.7 FinFET drain current versus gate voltage with drain voltage equal 50mV.....42 Figure 5.8 FinFET drain current versus gate voltage with drain voltage equal 1.4V.......42 Figure 5.9 FinFET mg versus gate voltage with drain voltage equal 1.4V......................43 Figure 5.10 FinFET drain current versus gate voltage at various drain voltages............44 Figure 5.11 FinFET transistor power gain versus frequency (0.7V V Δ≈, VDS=1.2V).....45 Figure 5.12 FinFET transistor current gain versus frequency (0.7V V Δ≈, VDS=1.2V)...45 Figure 5.13 FinFET transistor current gain versus frequency (50VmV Δ≈, VDS=1.2V). 46 Figure 5.14 The low frequency noise of the FinFET for L=120nm, W=4.2um[Zhu, 2005 #77]..................................................................................................................................47 Figure 5.15 Equilibrium high frequency CV curve.........................................................48 Figure 5.16 The 3D FinFET. Tbox=400nm, Hfin=50nm, Tsi=20 nm.................................49 Figure 5.17 Die picture of the circuit with test frame.......................................................49 Figure 5.18 FinFET transistor characteristics (W=72 um, L=80 nm)..............................49 Figure 5.19 The FinFET smallsignal equivalent model..................................................51 Figure 5.20 Zero bias smallsignal equivalent model.......................................................51 Figure 5.21 Measured (dot) and modeled (line) Sparameters (Vgs=0.6V, Vds=1.2V)..53 Figure 5.22 Measured (dashed) and modeled (solid line) S21 (Vgs=0.6V, Vds=1.2V)....53 Figure 5.23 Measured (dot) and modeled (line) h21 (50VmV Δ≈, Vds=1.2V).................56 Figure 6.1 The GPS L1/L2 band signal spectrum[Ko, 2005 #88]....................................59 Figure 6.2 Dualconversion GPS receiver........................................................................60 Figure 6.3 Singleconversion GPS receiver......................................................................60 Figure 6.4 Block diagram of CMOS GPS receiver...........................................................61 Figure 6.5 The GPS band signal spectrum after downconverted to 2 MHz IF[Shaeffer, 1998 #86]..........................................................................................................................62 Figure 6.7 Cascaded stages of receiver system.................................................................63 Figure 6.8 Block diagram of the GPS receiver.................................................................64 Figure 6.9 Reciprocal mixing of the inband thermal noise and phase noise[Ko, 2005 #88]..................................................................................................................................67 Figure 7.1 Common LNA topologies. (a) Resistive termination, (b) 1/mg termination, (c) shuntseries feed back, and (d) inductive degeneration....................................................72 Figure 7.2 CSLNA Schematic Diagram...........................................................................73 Figure 7.3 MOSFET equivalent noise model...................................................................76 Figure 7.4 Smallsignal model for noise calculation of CSLNA......................................77 Figure 7.5 the CGLNA schematic diagram......................................................................78 Figure 7.6 gm/ID versus inversion coefficient curve..........................................................82 Figure 7.7 Proposed differential LNA schematic.............................................................83 xi Figure 7.8 Voltage gain of differential LNA....................................................................85 Figure 7.9 S12 of differential LNA...................................................................................85 Figure 7.10 S11 and S22 of LNA.....................................................................................86 Figure 7.11 Noise Figure of LNA.....................................................................................86 Figure 7.12 Stability measurement of LNA......................................................................87 Figure 7.13 1dB compression point measurement of LNA.............................................87 Figure 8.1 oscillator viewed as feedback system..............................................................90 Figure 8.2 Feedback model for oscillator with LC resonant tank.....................................91 Figure 8.3 LC tank............................................................................................................92 Figure 8.4 the typical crosscouple oscillator...................................................................93 Figure 8.5 The complementary crosscoupled oscillator..................................................94 Figure 8.6 The typical Colpitts oscillator.........................................................................95 Figure 8.7 The typical differential Colpitts oscillator.......................................................96 Figure 8.8 The differential Colpitts oscillator with currentswitching technique.............97 Figure 8.9 Inversion coefficient for L=80 nm FinFET transistor.....................................99 Figure 8.10 Micropower VCO schematics....................................................................101 Figure 8.11 Simulated tuning characteristics of the VCO..............................................102 Figure 8.12 Output LO signal magnitude versus frequency...........................................102 Figure 8.13 VCO Phase noise versus frequency............................................................103 Figure 9.1 The heterodyne receiver system with a mixer...............................................105 Figure 9.2 Simple doublebalanced passive mixer.........................................................108 Figure 9.3 A active doublebalanced mixer....................................................................110 Figure 9.4 Minimum supplyheadroom doublebalanced mixer....................................112 Figure 9.5 Conversion gain versus frequency.................................................................113 Figure 9.6 Noise figure versus frequency.......................................................................114 Figure 9.7 1dB compression point of mixer..................................................................114 Figure 10.1 The diagram of system simulation of GPS receiver frontend subblocking circuits............................................................................................................................117 Figure 10.8 A typical commonsource amplifier with inductor load..............................123 Figure A.1 Microstrip inductor physical layouts for differential inputs[Danesh, 2002 #33]. (a) Two asymmetric spiral conductors. (b) Symmetrical microstrip inductor................125 Figure A.2 (a) Lumped equivalentcircuit model of a microstrip inductor, and circuit equivalents for (b) singleended (port 2 grounded) and (c) differential excitation.........126 Figure A.3 The test structures of differential inductors and transformers[Long, 2000 #34]. (a) 1:1 transformer. (b) differential inductor. (c) Rabjon Balun. (d) 1:2.5 transformer..127 Figure C.1 The 3D FinFET structure.............................................................................132 Figure C.2 Scheme of capacitance measurements for FinFET.......................................133 Figure C.3 Equilibrium high frequency CV curve........................................................134 Figure C.4 (a) Potential profile and (b) band diagram of FinFET..................................136 xii xiii LIST OF TABLES Table Page Table 3.1 Extracted circuit model parameters..................................................................20 Table 4.1 Extracted parameter values for 200 finger (Wf = 5um) varactors for L equal 1 um and 0.8 um respectively..............................................................................................30 Table 5.1 Extracted Model Parameters.............................................................................52 Table 5.1 The modified FinFET BSIM3SOI model.........................................................55 Table 6.1 Signal degradation due to finite quantization in the ADC................................66 Table 6.2 Summary for GPS receiver frontend requirements.........................................68 Table 7.1 The comparison between CSLNA and CGLNA (“+” indicates better, “” indicates worse)................................................................................................................79 Table 7.2 Differential LNA passive components values..................................................84 Table 7.3 Differential LNA active components values....................................................84 Table 7.4 Ultralow power LNA performance summary..................................................88 Table 8.1 Onchip inductors specifications at 1.5 GHz....................................................98 Table 8.2 Device sizing and IC for oscillator transistor.................................................100 Table 8.3 Summary of VCO performance......................................................................103 Table 9.1 Active doublebalanced mixer performance summary...................................115 Table 10.1 Summary of GPS receiver frontend subblocking circuits of plan A..........119 Table 10.2 Summary of GPS receiver frontend subblocking circuits of plan B..........121 Table 10.3 Comparison of GPS receiver subblocking circuit performance..................122 xiv LIST OF DEFINITIONS Subthreshold region: include weak and moderate inversion Moderate inversion: Gatetosource voltage is close to threshold voltage. Weak inversion: Gatetosource voltage is far below threshold voltage. Inversion coefficient: parameter describing the transistor’s working region, for example, weak, moderate and strong inversion xv Chapter 1 Objective 1.1 Motivation In the past 40 years, many kinds of electronic circuits were developed at an amazing speed. The low power integrated circuit (IC) is one of the targets designers are pursuing. Among the applications of low power ICs, wireless RF transceivers are new emerging application that requires small size, low cost and low power. One of the most critical components in wireless transceiver is the wireless receiver. The objective of this research is to study and realize an ultralow power RF receiver based on doublegate CMOS (FinFET) technology. In this work, tradeoffs and strategies for low power receiver design are investigated. A low power global position system (GPS) receiver is taken as an example to test our study. 1.2 Overview This dissertation is organized as follows. Chapter 2 describes techniques for the design of analog circuits for low power. It focuses on the importance of moderate inversion usage in this design, which is the main method to reduce the power consumption of RF receiver. Chapter 3 and 4 focuses on the design, test and model integrated passive devices, such as inductors and varactors. Chapter 5 introduces a new doublegate CMOS architecture, FinFET. We characterized the FinFETs with IV, CV, 1 and Sparameter measurements at GHz frequency range. A BSIM3SOI model is developed for further implementation and validation of the FinFET transistor RF circuits in moderate inversion. Starting from Chapter 6, we apply the passive and active devices to the GPS receiver frontend circuit design. In Chapter 6, the GPS receiver’s architecture, system design and implementation requirement are described. Chapters 7 to 9 describe the GPS receiver frontend subblocks, such as ultralow power LNA, VCO and mixer design, respectively. The performances and trade offs of each building blocks are summarized at the end of each chapter. Chapter 10 concludes the dissertation with a brief summary of results and discussion of future research directions. 2 Chapter 2 Low Power Techniques 2.1 Introduction The silicon CMOS technology has become dominant in integrated circuits. CMOS gate lengths have reduced from 10um in the 1970’s to the present day geometries of less than 90 nm. According to the 2004 International Technology Roadmap for Semiconductors (ITRS), by 2006, MOS transistors with a physical gate length of 80 nm will become widely available. Its scalability provides decreased power consumption at enhanced performance levels. When the CMOS devices are scaled into the sub100nm dimension, the deep submicron CMOS opens up new frontiers in low voltage and current circuit design. In this chapter, design techniques are outlined first, and the advantages of modern CMOS devices are analyzed and the ultra low power consumption for RF front end circuits is investigated. 2.2 Low Supply Voltage Technique Conventional CMOS technology has, for over 3 decades, been locked into designing processes with high performance digital circuits as the objective. Analog/RF designers basically just used discrete solutions or hybrid blocks of bipolar GaAs, and more recently BiCMOS and Heterojunction Bipolar Transistors (HBT). Not only are digital device models not sufficient for the accurate circuit simulation, the analog/RF designer must face a constantly shrinking design space. One of the most difficult 3 problems is the constantly decreasing supply voltage for modern CMOS processes, causing reduced voltage headroom and dynamic range for analog and RF application [1]. 2.1.1 Opportunities for Reduced Supply Voltage Here a typical differential local oscillator (LO) is shown in Figure 2.1. It is an example capable of operating with a very low supply voltage. It contains two stacked transistors. The inductors comprising the resonant load do not consume additional voltage headroom, additionally the output is allowed to swing above the supply voltage, VDD. Theoretically, the LO may operate on a supply voltage as low as VDsat1+VDsat3, where VDsat is the MOSFET saturation voltage. Furthermore, if the devices M1 and M2 are designed to operate in the subthreshold regime, VGS and VDsat may be quite small. The main challenge in operating under a low VDD is the reduction in output voltage swing. Generally, system level considerations are critical when designing low voltage circuits and choosing the optimal power supply voltage. Supply voltage is not typically considered a variable parameter available to the designer, because it is impractical from an integration perspective if each component requires its own unique supply. However, it is entirely reasonable that two supply voltages will be available in a network environment: e.g. high voltage for active mode and low voltage for sleep mode. Recent research in low voltage digital design has shown that significant savings in memory leakage power may be achieved by reducing the supply to a few hundred mill volts during standby periods [2]. If a lower voltage supply is made available for use in digital standby mode, it may also be available for analog circuits [3]. 4 Figure 2.1 Schematic of low power supply LO. 2.2.2 Challenges for Low Power Supply For analogue circuits, downscaling supply voltage and process feature size will not automatically reduce power consumption and, in fact, usually it often has the opposite effect in analog design. In analogue chips, power is consumed to maintain the signal energy above the thermal noise floor in order to achieve the desired signaltonoise ratio or dynamic range. Since minimum power consumption is related to the ratio between supply voltages and signal amplitude, powerefficient analogue circuits should be designed to maximize the voltage swing. Reducing the supply voltage, while maintaining the signaltonoise ratio and bandwidth, therefore requires that the transconductance be increased. This is normally done at the expense of power or by reduced channel length. Therefore the approach for analogue designs must therefore be different. 2.3 Subthreshold Operation Technique 5 2.3.1 Fundamental of Subthreshold Operation For gatesource voltage (VGS) less than the extrapolated threshold voltage but high enough to create an inversion region at the surface of the silicon, the device operates in the subthreshold region. In this work, both weak and moderate inversion are considered as subthreshold operation even we know VtVGS may larger than Vt in moderate inversion. Later in this chapter we will point out this work is based on moderate inversion because of the bandwidth limitation. In subthreshold region, the channel charge is much less than the fixed charge in the depletion region and the drain current arising from the drift process is negligible. The drain current is caused by a gradient in minoritycarrier concentration, i.e. diffusion current. In subthreshold operation, the surface potential is approximately a linear function of the gatesource voltage [4]. Assume that the charge stored at the oxidesilicon interface is independent of the surface potential in the subthreshold region, and then changes in the surface potential sψΔare controlled by changes in the gatesource voltage through a voltage divider between the oxide capacitance and the depletionregion capacitanceGSVΔoxCjsC. Therefore, 1soxGSjsoxdCdVCCnψ=+ = (2.1) where n is called subthreshold slope factor and takes on a values from 1 to 2. The drain current equation in the subthreshold region is exp1expGStDSDtTTVVVWIILnUU⎡⎤⎛⎞⎛−=− ⎞ − ⎢⎥⎜⎟⎜ ⎟ ⎢⎥⎝⎠⎝ ⎠ ⎣⎦ (2.2) 6 where is the thermal voltage. is the gate to source threshold voltage. is intrinsic or specific current. TUtVtI 202toxInCUμ= T (2.3) Physically, represents the characteristic current for the device in the center of the moderate inversion region, providing a convenient normalization factor. The drain current of a given device may be normalized to, producing the inversion coefficient, tItIDtIICWIL= (2.4) The inversion coefficient provides a very useful way of identifying the operation region and level of inversion [5] of MOS transistors, 1IC<<: Weak inversion 1:IC≈Moderate inversion 1:IC>>Strong inversion Unlike in strong inversion, the minimum drainsource voltage required to force the transistor to operate as a current source in the subthreshold region is independent of the overdrive [4]. Calculating DGSIV∂∂from (2.4) and using (2.3) gives exp1exptGStDSoxDDmtTTTToxIVVVCIIWgLnUnUUnUUCC⎡⎤⎛⎞⎛⎞−=−−==⎢⎥⎜⎟⎜⎟+⎢⎥⎝⎠⎝⎠⎣⎦ js (2.5) The ratio of the transconductance to the current of an MOS transistor in subthreshold region is 1mDTgInU= (2.6) 7 The Equation above predicts that this ratio is independent of the overdrive, . For the transistor in the strong inversion, theVΔmDgIratios is 2mDgIV=Δ (2.7) where is the overdrive voltage. Comparing (2.6) to (2.7), we find the VΔmDgI of subthreshold region may 4 to 8 times higher than in strong inversion. 2.3.2 Advantages of Subthreshold Operation Motivated by the needs for low power narrowband wireless communication systems, the micropower RFIC frontend, a LNA combined with a downconversion mixer, has been designed using weak inversion CMOS techniques [6]. Within the active (saturation) region a device may be biased in the moderate or weak inversion region. The available transcondance per amp may 4 to 8 times higher than in strong inversion. This can be a big benefit for wireless applications where power consumption is much concerned if the bandwidth is available. The second advantage of subthreshold operation is the relatively low drain saturation voltage VDsat, which is typically around 3 to 4 UT (about 78mV) [7] at room temperatuer. More practically as a result of anticipated temperature variation VDsat, must be greater than 120mV. Compared with strong inversion, the value of VDsat in weak inversion is independence of gate voltage. The low saturation voltage implies that transistors operating in weak or moderate inversion require less overhead resulting in greater headroom than do devices in strong inversion. Therefore subthreshold operation is a natural choice for circuits operating with reduced supply voltage when the bandwidth is available. 8 The third advantage of subthreshold operation is low flicker noise achieved in moderate inversion since the flicker noise is reduced with less current flow [8, [9]. A detailed explanation follows in chapter 5. Finally, nonlinearity is not a problem. In subthreshold region the third order intercept point voltage () is approximately [10] 3IIPV (2.11) mVUVTIIP12010043−≈= If the system signal is much less than 100 mV we could ignore the effects os VIIP3. The second order intercept point voltage () is inversely proportion to input offset voltage () [10] 2IIPVosV ()OSTIIPVUV224= (2.12) For 80 nm FinFET the VOS is approximately 4.8 mV per square root of finger numbers [11]. For a 200 um device it has 2000 fingers. The VOS is calculated 0.1 V. Thus the VIIP2 is 25 V. Since for this work the amplitude of signal is on the order of microvolts, the effects of IP2 and IP3 could be ignored. 2.3.3 The challenges of Subthreshold Operation Although there are many advantages obtained in weak inversion region there are drawbacks as well. The first and obvious problem is the reduced bandwidth. Traditionally, transistors for high frequency applications are operated in strong inversion to take advantage of the high device transit frequency (Tf) in this regime. Transit frequency is defined as the frequency where the current gain of the device falls to unity and is normally given by: 9 ()2mTgsgdgfCCπ=+ (2.9) Since gm in weak or moderate inversion may be ten or more times smaller than that in strong inversion mode, Tf in the weak inversion is several orders of magnitude below that in the strong inversion although the Cgs in subthreshold may several times smaller than that in strong inversion shown in Figure 5.15 in Chapter 5. In the past, this speed limitation prohibits the applications in RF design. However, technology scaling is beginning to provide the solution since in the weak or moderate inversion, Tf is inversely proportional to the square of the channel length in (2.10) 2TVnUtToxIefLCΔ≈ (2.10) The present deep submicron CMOS technology makes this feasible. As shown in Figure 2.2 [3], the peak Tf is around 100GHz, decreasing sharply at lower inversion coefficient. At the center of moderate inversion, indicated by the vertical line at IC equal 1, Tf is approximately 5 GHz for the 130nm process. The bandwidth is adequate to implement circuits operating in the hundreds of MHz or above. In the Figure 2.3, device Tf is simulated across inversion level for three generations of submicron CMOS. At the center of moderate inversion, Tf is approximately 6 GHz for 180 nm, 12 GHz for 130 nm, and 21 GHz for 90 nm node. The current state of the art, 90nm CMOS device, can provide sufficient bandwidth for subthreshold circuits up to the low GHz range, such as GPS receiver front end which works at 1.5 GHz. From now on, we will only concentrate on the moderate inversion since it can provide enough bandwidth for low GHz application. 10 As a result the expected gm efficient improvement is only expected to be 2 to 4 greater than square law. Figure 2.2 gm/ID and fT for a modern CMOS 0.13um process [3]. Figure 2.3 Comparision of Tf with technology scaling [3]. In addition to the reduceTf, the current mismatch is another problem. In subthreshold region the drain current has an exponential relationship with the gate 11 voltage. As a result any small change in the gate to source voltage will have a larger change in drain current, which makes it unpredictable for the circuit. Fortunately, with the device area increase the current mismatch will decrease since [12] 22211.25SiISiTLWToxAkLWTToxfinΔ⎛⎞ΔΔΔΔ⎛⎞⎛⎞⎛⎞=±⋅+++⎜⎟⎜⎟⎜⎟⎜⎟⋅⎝⎠⎝⎠⎝⎠⎝⎠ 2 (2.10) Where IAΔ is the ratio of current mismatch. 12 Chapter 3 Integrated Inductors 3.1 Introduction The inductor is a key component in high RF frequency circuits. In the past a few years there was a great drive to improve the quality factor of integrated inductors so that a radioonchip system can be readily realized [13]. Bulk silicon inductors generally have peak Q’s of less than 10 with low selfresonant frequencies [14]. These values are typically not satisfactory for high performance, voltagecontrolled oscillator (VCO) designed to meet the stringent phase noise and low power constraints. In this chapter, the inductor structure and layout were discussed first. Then the inductor model and model parameters extraction methods were presented. Finally, the model simulation results were compared with the measurement for some typical inductor and the conclusion was drawn. 3.2 Structure and Layout High quality factor integrated circular spiral inductors were fabricated in SPAWAR Systems Center’s novel 0.5 μm TSOI CMOS technology with a stacked 1.7 μmthick aluminum metal. The geometry of the spiral inductors can be described by the following parameters: number of turns (n), turn width (w), turn spacing (s), inner diameter (d) or inner to outer radius ratio (IDOD). These parameters are shown in Figure 13 3.1(a). The die photo is shown in Figure 3.1(b). The width of the spiral metal is from 15 um to 50 um. The innertoouter diameter ratio is from 0.3 to 0.7. And the number of turns is from 1.5 to 10.5. Figure 3.2 shows a crosssection of an integrated inductor fabricated in this technology. The test frame with groundsignalground pad was laid out for shielding. The inductors we investigated can be grouped in the following classes: 1) Same IDOD, but different n and w; 2) Same w, but different IDOD and n; 3) Same n, but different IDOD and w. All the inductors have a fixed spacing between the turns, s = 3 μm. In this case, the inner radius (Ri) can be derived analytically from the parameters set (n, w, IDOD), Ri=IDOD*n*(w+s)/(1IDOD). Three families of inductors were characterized by sparameter measurement with HP 8720D network analyzer and Cascade Microtech coplanar groundsignalground (GSG) probes. Deembedding was carried out to remove the parasitic components. (a) 14 (b) Figure 3.1 (a) Structural parameters of an onchip spiral inductor, (b) Die photograph of the spiral inductor. Figure 3.2 Crosssection of inductor. 3.3 Inductor Model and Parameterextraction Method (a) 15 (b) (c) Figure 3.3 Equivalent circuit for models: (a) with substrate, (b) without substrate, (c) equivalent circuit at low frequency. The equivalent circuit for the inductor is shown in Figure 3.3, where Ls is the inductance and Rs is the parasitic series resistance of the metal wire. The overlap between the spiral and the underpass allows direct capacitive coupling between the two terminals of the inductor. This path is modeled by the series capacitance Cs. In a conventional inductor structure, the oxide capacitance between the inductor and the silicon substrate has to be taken into account, as well as the subcircuit of the substrate, which are shown in Figure 3.3(a). However, including these parasitic circuit elements makes the extraction of the important intrinsic inductor parameters very tricky and inaccurate. In order to improve the inductor performance the silicon substrate has been etched away. As a result, the self resonance frequency and quality factor Q of the inductor increase. The resulting circuit model can be simplified to the one shown in Figure 3.3(b). The meaning of Cox in this circuit is no longer the capacitance between the 16 inductor and the substrate; instead, it models the remaining parasitic capacitive coupling between the inductor and the surrounding grounded structures. At low frequency, 100MHz, both the coupling capacitor Cs and the parasitic capacitor Cox can be neglected, thus the circuit model is further reduced to the one in Figure 3.3(c). For this series RL circuit, the two components can be easily extracted from the Yparameter: 2111ImLsYω⎛⎞=−⎜⎟⎝⎠ (3.1) 211ReRsY⎛⎞=−⎜⎟⎝⎠ (3.2) However, as the Yparameters cannot be measured accurately, they are obtained by the transformation from the measured sparameters. The overall capacitance can found from the selfresonance frequency: 201CLsω= (3.3) where C includes Cox and Cs. All parameters (L, R and C) in the inductor model are functions of the number of turns (n), the turn width (w), the turn spacing (s), and one from the following: the outer diameter dout, the inner diameter din, the average diameter davg = 0.5*(din+dout), or the inner and outer diameter ratio (IDOD). By fitting the data, expressions for Ls, Rs and Cs were determined. We have successfully obtained these parameters for inductors in a broad range: the number of turns from 1.5 to 5.5, turn width from 15 um to 50 um, and inner and outer diameter ratio from 0.1 to 0.7. 17 Due to large amount of data collected, computer software was employed to find the dependence on the geometric parameters. However the selected software (Origin 7) can only fit two independent variables, therefore, the following three approach was used: a) Ls = f (w, n), while IDOD is fixed, b) Ls = f (n, IDOD), while w is fixed. c) Ls = f (IDOD, w), while n is fixed, As the approach c) is not practical, the approaches a) and b) were adopted. 3.4 Results and Model Verification 3.4.1 Series Inductance (Ls) The empiric expression of the series inductance is based on the data fitting technique in reference [15]. For fix IDOD, the expression is 321PPLsPnw= (3.4a) Taking the logarithm of Eq. (4a) we can get the following monomial relation: 123loglogloglogLsPPnP=++ w (3.4b) For the inductors with IDOD = 0.5, the fitted the parameters are found: P1 = 0.26591, P2 = 2.21235 and P3 = 0.72121. Therefore, the inductance can be modeled as: 2.212350.721210.26591Lsnw= (3.4c) In a same way, the inductor model can be fitted following the approach b). As an example, inductors with w = 25 can be modeled as: (3.5) 1.548630.511541.07185LsnIDOD= 3.4.2 Series Resistance (Rs) 18 The series resistance of the inductor can be expressed as [16]: effrstwlR⋅=ρ (3.6) where rρ is the resistivity of the metal; l is the overall length of spiral, which equals avgdnπ; w is the line width; is the effective thickness. With the consideration of the skin effect, the effective thickness can be calculated as efft)1(δδteffet−−⋅=; where t is the physical thickness of the metal and δis the skin depth. At 1 GHz, the skin depth of Al and Cu is 2.8 um and 2.5 um, respectively. 3.4.3 Series Capacitance (Cs) The Series capacitance Cs models the parasitic capacitance coupling between the inductor and the underpath. It can be approximated as a parallelplate capacitor [17]. 223oxsMMkCnwtε−⋅= (3.7) Where 23MMt− is the oxide thickness between spiral and the under path, which is 0.9 um in our sample; = 0.7 is a fitting parameter. k 3.4.4 Model Verification With the method described above, the parameters of the series resistance, inductance and capacitance can be extracted; the results from two samples are shown in Table 1. The measured and simulated Sparameters have been compared in Figure 3.4 and Figure 3.5, where the numbers of turns are 2.5 and 4.5, respectively. The measured inductances as the function of frequency are plotted in Figure 3.4(b) and Figure 3.5(b). 19 The total error [18] between the measured and the simulated sparameter calculated as follows by (3.8) is less than 3% over the frequency range from 0.1 to 10 GHz. 221()1004ijijtot 1 freqijfreqijmeasSsimSSNmeasSε⎧⎫−⎪=⋅⋅⎨⎪⎪⎩⎭ΣΣ ⎪⎬ (3.8) The simulation is carried out with ADS. We also compared the results from inductors with other structural parameters, they consistently have good agreement. Table 3.1 Extracted circuit model parameters. Turn w (μm) IDOD Ls(nH) Rs (Ω) Cs(fF) 2.5 25 0.5 2.8 0.13 41.48 4.5 25 0.5 12 0.36 75 freq (100.0MHz to 10.00GHz)S(2,1)inductor_mod..S(2,1) Figure 3.4 (a) Measured (dot) and simulated (line) sparameter, n=2.5, w=25um, s=3um, and IDOD=0.5. 20 Figure 3.4 (b) Measured inductance as a function of frequency. n=2.5, w=25um, s=3um, and IDOD=0.5. freq (100.0MHz to 10.00GHz)S(2,1)inductor_mod..S(2,1) Figure 3.5 (a) Measured (dot) and simulated (line) sparameter, n=4.5, w=25um, s=3um, and IDOD=0.5. Figure 3.5 (b) Measured inductance as a function of frequency. n=4.5, w=25um, s=3um, and IDOD=0.5. 21 A typical fit of the VerilogA model vs. the measurement data for two inductor instances is shown in Figure 3.6. Figure 3.6 shows that a 6.5 nH inductor has a peak Q of 18, which is higher than the best Q of 15 reported in [19] for a 5.5 nH inductor in a silicononsapphire (SOS) technology with a thicker 2.5μm aluminum metal. The 6.5 nH inductor has a selfresonant frequency at about 10 GHz, which is about twice the selfresonant frequency reported in [19]. Figure 3.6 Comparison between measurement data and model simulation. We also find the model developed is accurate for inductors with the number of turns less than 5.5, fortunately most practical onchip spiral inductors fall in this range. When the number of turns is larger than 5.5, the error becomes larger and more circuit elements must to be included in the model. As shown in Figure 3.7, the model can not predict the behavior for frequency higher than 7 GHz. 22 freq (100.0MHz to 10.00GHz)S(2,1)inductor_mod..S(2,1) Figure 3.7 Measured (dot) and simulated (line) sparameter, n=5.5, w=25um, s=3um, and IDOD=0.5. 3.5 Conclusion Based on the above analysis, we found that small IDOD ratio inductors were turnrestricted. For example, if IDOD equals to 0.1and 0.2, n should be maintained less than 2, and 3 respectively. Generally IDODs of 0.4 to 0.5, w of 15 um to 30 um and s of 3 provide a better model fit. The obtained equivalent Spice circuit model shows good agreement between the simulated and measured sparameters over a wide frequency range. 23 Chapter 4 Integrated Varactor 4.1 Introduction Integrated voltagecontrolled capacitors (varactors) are widely used as frequency tuning elements for RF applications [20, [21], such as voltage controlled oscillators (VCOs). The core of a VCO is the LC tank circuit, composed of a varactor and an inductor. Several RF models for the MOS varactor have been reported [21, [22, [23, [24]. The physical model proposed in [21] was derived by considering the device structure but consisted of separate models for different operating regions of the device, i.e. in accumulation and in depletion, respectively. The theoretical model reported in [22] includes the physicsbased equations. The SPICE compatible models exploiting a subcircuit based on the BSIM3v3 model were presented in [23] and [24]. This chapter presents a RF model of an accumulationmode MOS varactor with a high capacitance tuning range in a multifinger layout, and it is based on physical parameters. The model describes the voltage dependent capacitances and resistances along with the parasitic inductance, capacitance and resistance terms. A single topology with the lumped elements derived from the device has been proposed for easy integration into common circuit simulator as well as direct linkage to a pcell. Good agreements between measured data and simulation results were obtain in the frequency range of 0.1 to 25 GHz by deembedding the test frame inductance. 24 4.2 Structure and Layout Accumulationmode MOS varactors were fabricated in SPAWAR Systems Center’s Integrated Circuit Fabrication Facility in their 0.5 um CMOSSOI technology where the substrate has been removed. This process has low parasitic capacitance which facilitates fabricating high quality, high frequency RF varactors by decreasing the losses normally associated with bulk silicon processes. The varactors designed, fabricated and tested employ a multifingered layout with finger lengths of 0.5 um, 0.8 um, and 1.0 um, finger widths of 5 um and 10 um, and total widths of 1000 um. A representative crosssection of the device is shown in Figure 4.1 with a micrograph for a typical layout shown in Figure 4.2. Figure 4.1 The crosssection of the single varactor. Measurements confirm that the varactors have a tuning ratio that varies from 1.7 for the 0.5 um device to 2.6 for the 1.0 um device. The worst case selfresonant frequency of 21.5 GHz was observed for the W = 2005mμ×, L = 1.0 um device at its maximum capacitance of about 2.13 pF at 500 MHz, as shown in Figure 4.3(a). As observed in 25 Figure 4.3(b), the quality factor remains satisfactory (above 8) up to 12.8 GHz. These figures are significant compared to other varactors which have been created recently [23]. Figure 4.2 The micrograph of the varactor under test. (a) 26 (b) Figure 4.3 (a) Capacitance versus frequency and (b) quality factor versus frequency. 4.3 Model Parameter Extraction and Model Verification To verify and parameterize the proposed equivalent circuit show in Figure 4.4, the fabricated accumulationmode MOS varactors were laid out and extracted. Direct parameter extraction was performed with Yparameter analysis based on Sparameter data using an HP8720D network analyzer. Cs was extracted out at 1 GHz, with the Rs and L extracted at selfresonance. Deembedding was carried out to remove parasitics, which consisted primarily of an inductance term. Rm1 and Rg and Rs/dcnt (≈ 0) represent the metal1, the gate and gate contact resistance and source/drain contact resistance respectively. In order to model the gate bias dependence of CVar’, varactors capacitance per unit width was described as follows, GGoxavgfCGCGCVarVVLCCCPVPVPCβ+++=++=1''1'321. (4.1) Where 27 , oxCLCP=1 β=CP2, and ''3avgfCCCP+=. Figure 4.4 The equivalent varactor circuit. Figure 4.5 Capacitance versus length at VG=0V. The fringe capacitance per micrometer of varactor width, Cf’ , was obtained by plotting the varactor capacitance at VG equal zero and extrapolating to find the fixed capacitance 28 term or the P3C component of equation (1). All three test devices with gate lengths of 0.5 μm, 0.8 μm and 1 μm respectively, are plotted as shown in Figure 4.5. Cf’ is found to equal 0.24 fF/μm. Equation (4.1) is based on the data fitting and accurately describes the nonlinear characteristic of CVar as a function of the varying gate bias, as shown in Figure 4.6. For the 5_200_p8 (finger width_finger number_gate length) varactor, P1C =1.64 fF/μm, P2C =2.99 V1, P3C =1.23 fF/μm and for 5_200_1 varactor, P1C =2.89 fF/μm P2C =3.63 V1, P3C =1.58 fF/μm. Using the P3C data and Cf’ from Fig 4.5. and solving for CoxAvg and δL, respectively, result in CoxAvg equal 1.765 fF/μm2 and 0.117 μm or Leff = L – 0.234 μm. Varactor resistance consists of both a channel term and the gate poly term. The channel resistance is modeled as follows; (4.2) paccschRRRR//+= In (3.2), is the gate bias independent or static resistance term of RsRch. Racc represents the resistance of the accumulation layer formed in the channel region. Rp is the nwell resistance in parallel with Racc. ,,1(),,accGGchGGchchKVdVifVdVRelsewhere−>⎧=⎨∞⎩ (4.3) In (3.3), is a parametric coefficient that is related to the mobility of electrons in the accumulation layer, and is relevant to the flatband voltage. As VaccKchGdV,G decreases below the flatband voltage, Racc can be considered as being infinite and Rch approaches a constant value of Rs + Rp. When VG increases above the flatband voltage, Racc dominates Rch. As a result, Rch decrease, finally approaching a constant value of Rs, as shown in Figure 4.6. 29 Figure 4.6 Capacitance and Resistance change verse gate bias voltage as extracted from the varactor parametrics. Similarly, a data fitting equation is used to describe the voltage dependence of resistance: RGRGRsPVPVPR3211++=, (4.4) From the extracted resistance data for the 5_200_p8 varactor; P1R = 0.138 V1 P2R = 0.191 V1, P3R = 2.72 Ω and for the 52001 varactor; P1R = 0.0805 V1, P2R = 0.0354 V1, P3R = 2.65Ω. The extracted parameter values for the series resistance and inductance are summarized in Table I for VG =0 V. Table 4.1 Extracted parameter values for 200 finger (Wf = 5um) varactors for L equal 1 um and 0.8 um respectively. L(pH) Rm1(Ohm) Rg(Ohm) Cf(pF) Cs(pF) Rch(ohm) 5_200_0.8 35 0.05 0.078 0.24 0.958 0.658 30 5_200_1 35 0.05 0.0625 0.24 1.20 0.6415 Figure 4.7 and 4.8 compare the measured and simulated Sparameters at 0=GVV for the devices of Table 4.1. Note, the methods for determining L, Rm1, and Rg are presented in section 4. The total error between the measured and the simulated Sparameter with the proposed equivalent circuit was calculated to be in less than 1% over the frequency range from 1 to 25 GHz. Figure 4.9 shows measured and simulated CV characteristics for the L=0.8 μm and L=1 μm devices. freq (1.000GHz to 10.00GHz)S21S11 Figure 4.7 L=0.8um Vg=0V symbol is measured data and line is the simulated. 31 freq (1.000GHz to 10.00GHz)S11S21 Figure 4.8 L=1um Vg=0V symbol is measured data and line is the simulated. Figure 4.9 Comparison of the measured (symbol) and simulated (solidline) CV characteristics for the L=0.8um and L=1um devices. 4.4 Layout Summary and Usage In the circuit design process the designer is given the option to select L in the range of 0.7 um to 1.1 um at fixed finger width Wf of 10 um. The designer selects the varactor channel length L and provides the desired value of C (VG =0) for the varactor at 32 simulation/layout. The number of fingers n, along with the number of rows (r) and columns (c) will then be computed by the pcell generator and modeled for simulation by the Verilog code. It is strongly suggested that all fingers be wired with 10 um wide or wider m1 line with at least two gate contacts per finger for reliability. The pcell and VerilogA model are restricted to Wf=10 um and m1 interconnects that are 10 um in width. 4.4.1 Capacitance Calculation and Length choice The total capacitance of a varactor is modeled as the sum of a strongly bias dependent intrinsic capacitance (Cint) component and a weakly bias dependent fringe capacitance (Cf). The latter is equal to 0.24 fF/um. a. L was selected such that L approached being LCox >> Cf. Note this includes CGDO. The minimum L has been selected to be greater than 0.8um. b. Wf was selected such that Rg << Rch . The gate resistance is propotional to Wf but channel resistance is inversely proportional to Wf. Proper Wf choice will reduce the gate resistance. Thus, it can reduce the gate resistance noise. c. WTotal ≈ CAvg/(LCox + Cf’). Where CAvg is the average or zero bias value of the varactor capacitance and approximately equal: CAvg ≈ WTotal(L2δL) CoxAvg /2 (4.5) At VG equal to 0 V the zero bias value of the capacitance equals: CVar (VG =0) ≈ WT(L2δL) CoxAvg /2 + Cf’ WT. (4.6) Additionally, CMin ≈ WCf’ (4.7) 33 CMax ≈ WLCoxMax + WCfringe’ (4.8) The varactor with longer channel (L=1 um) provides a greater dynamic capacitance range with a reduced Qeff, while a shorter channel length varactor (L=0.8 um) provides a higher Qeff with a reduced dynamic capacitance range. a. nf the number of fingers equals WT/Wf. b. For a square varactor layout i. c (L + 1.6um) = r (Wf+12um) (4.9) ii. c x r = n fingers (4.10) iii. )12(6.1umWumLnrf++= (4.11) where )'(fringefAvgCCoxLWCn+⋅= then rnc= where the row value is rounded to the nearest integer and the column value solved for. 4.4.2 Resistance Estimation The metal1, gate and contact resistance can be written as: 1)2/)((1 10um1.6um)c(L)2/)((1 10um1.6um)c(L1+⎥⎦⎤⎢⎣⎡++⎥⎦⎤⎢⎣⎡+=rRoundRshmrRoundRshmRm (4.12) where Rm1 = 50 mohms. 3fgWRshpolyRLn=⋅ (4.13) 34 For L =1 μm, Wf = 5 μm, and n = 200, it is approximately equal to 20 mΩ. Where Rshpoly = 2.5 . Ω021/≈⋅=nIsRmRDcntS (4.14) Where Rm1Is = 5 ohms. 4.4.3 Inductance Estimation With the interconnect wiring set by the square feature of the varactor the inductance is better controlled and better estimated. The basic unit of inductance is estimated as follows: ⎥⎦⎤⎢⎣⎡−+⋅+⎥⎦⎤⎢⎣⎡−⋅=−−75.02ln)12/(10275.02ln)2/(1021717mmwlcRoundlwlcRoundlLp (4.15) where is set to 10 μm and l equal r(L+1.6 μm). This is an approximation. Due to the lack of separation between the fingers for W1mwf equal 5 or 10 μm it will have limited value above 5 to 10 GHz. Note the centertocenter m1 separation of the gate m1 and S/D m1 will be Wf +10 μm (m1) +2 μm (recommended m1 separation) in the pcell. 4.5 Conclusion In summary an equivalent RF model of an accumulationmode MOS varactor with high capacitance tuning range in a multifinger layout is constructed, which is composed of the following physical parameters: 1. Cf ‘ the total equivalent per um fringe capacitance – 0.24 fF/μm. 2. CoxAvg the equivalent oxide sheet capacitance  1.765 fF/μm2. 35 3. δL the channel foreshortening distance  0.117 μm or Leff = L – 0.234 μm. These parameters along with the fitting equations (4.1) and (4.4) and their coefficients can reliably be used to model the varactor capacitance, CVar’ and its voltage controlled channel resistance Rch. Finally, the inductance and gate resistance parasitics are modeled by equations (4.12) through (4.14). The varactor model is valid for finger widths of 10 μm and lengths from 0.7 to 1.2 μm where the total width is not expected to exceed 2000 μm or 200 fingers. The accompanying pcell and VerilogA model are restricted to finger widths of 10 μm and m1 interconnection width of 10 μm. 36 Chapter 5 FinFET transistors and Modeling 5.1 Introduction As the microelectronic industry is fast approaching the limit of bulk CMOS scaling, there are extensive research activities on advanced CMOS structures to extend CMOS scaling to less than 100 nm gate length. The FinFET is an innovative design of MOSFET, which is built on an SOI structure. The body of the transistor is etched into "fin"like structure, which is wrapped by the gate on both sides. The double gate (DG) MOSFET is a popular choice, because this structure is scalable and the short channel effects can be suppressed for a given equivalent gate oxide thickness . As shown in Figure 5.1, several rectangular multigated structures have been proposed recently, such as FinFET [25], trigate [26], Omegagate [27], pigate [28], etc. The FinFET has emerged as the most popular device because of its ease of babrication with the wellunderstood bulkMOSFET process. Figure 5.1 Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or: GAA structure); 5) Pigate MOSFET. [28] 37 The key challenges in the fabrication of doublegate devices are (a) selfalignment of the two gates, and (b) formation of an ultrathin silicon film. Figure 5.2 shows the different orientations possible for a doublegate device. Several selfaligned planar devices have been proposed [29], however, the process is usually complex and the contact to the bottom gate is very challenging. Devices with ultrathin film are generally considered incompatible with traditional processes. The FinFET is derived from the vertical MOSFET by reducing its height and converting it into a quasiplanar device. Figure 5.2 The possible Doublegate MOSFET orientations on silicon [29]. 38 Figure 5.3 The 3D FinFET. Figure 5.4 Scanning electron microscope picture of the cross section of FinFET (compliments of SPAWAR SC San Diego). Figure 5.4 depicts the geometry of the FinEFT. The fin is a narrow channel of silicon patterned on an SOI wafer. The gate wraps around the fin on three faces. The top insulator (nitride) is usually thicker than the side insulator (oxide), hence the device has effictively two channels. The thickness of the fin represents the body thickness (Tsi) of the doublegate structure, while its hight (Hfin) represents the channel width. 39 Figure 5.5 FinFET Process steps; from [25] Figure 5.5 shows the basic processsteps involved in the fabrication of the FinFET. Since it was first proposed [25], refinements have been reported consistently [30, [31]. 5.2 Performance of FinFET Transistors The FinFET transistors were fabricated using SOI deep submicro (DSM) technology at SPAWAR system center, San Diego. There were two wafers made using the same mask. For the first run there are only four dies working on the whole wafer and 40 most measurements were made with these transistors there. For the second run the finger yield is low. Although transistors seemed to be working but their drain current much is less than expected. Some measurements were also made on this wafer. The discussion is that follows is an attempted to explain the problem. 5.2.1 DC Measurements HP4155A semiconductor analyzer was used to make the DC measurement. Figures 5.6 to Figure 5.9 show FinFET (10 um width, 56 nm length) IV characteristics. Figure 5.6 FinFET drain current versus drain voltage at various gate voltages. 41 Figure 5.7 FinFET drain current versus gate voltage with drain voltage equal 50mV. Figure 5.8 FinFET drain current versus gate voltage with drain voltage equal 1.4V. 42 Figure 5.9 FinFET versus gate voltage with drain voltage equal 1.4V. mg In saturation, the ideal drain current has a squarelaw dependence on the gatetosource voltage for long channel devices. But from the drain current curves shown in Figure 5.6 we find that it has a linear relationship with the gate voltage. This occurs as a result of velocity saturation. The highfield effects become prominent at moderate drain voltage with continued device scaling. The primary highfield effect is velocity saturation. In silicon, as the electric field approaches aboutV/m, the electron drift velocity shows a weak dependence on the field strength and eventually saturates at a value of about 106410×5 m/s. For an 80 nm gate length device, velocity saturation begins to kick in at 320 mV. With the gate voltage above threshold voltage and draintosource voltage above 320 mV the device enters velocity saturation region. In the velocity saturation the drain current can be rewritten as ()2noxDGStsatCIVV E μ=− (5.1) 43 The values of all smallsignal parameters can change significantly in the presence of shortchannel effects. The limiting transconductance of shortchannel MOS device in velocity saturation, 2noxDmGSCI sat gWEVμ∂≡≈∂ (5.2) Figure 5.7 indicates the threshold voltage of the FinFET is around 0.1V. It is difficult to design RF and analog circuits with negative threshold voltage device. Molybdenum gate technology has been applied to modify the threshold voltage of FinFET transistors, and it was successfully adjusted to 0.4 V [32]. Figure 5.10 shows FinFET drain current versus gate voltage at different drain voltages. The subthreshold slope is about 80mV/dec for drain voltage equal 50mV, and n is 1.33. 56 nm (Gate Length) FinFET IV Characteristics10x0.056 (WxL) FinFET, Wafer 2751401.00E101.00E091.00E081.00E071.00E061.00E051.00E041.00E031.00E021.00E011.00E+0010.500.511.5VGS (V)Log ID (A)Vds=0.05 Vvd=1.4v Figure 5.10 FinFET drain current versus gate voltage at various drain voltages. 44 5.2.2 AC Measurement HP8720D network analyzer was used to make Sparameter measurement on FinFET transistor (W=72um, L=80nm). The maxfwas extracted when the power gain equal to unity, that is 2211S=, as shown in Figure 5.11. Convert Sparameters to Hparameter. The fT can be extracted at 211h=. With the transistor working in velocity saturation region (, V0.7VΔ≈ Vt=0.1V, VDS=1.2V), maxfof FinFET is approximately 100 GHz, as shown in Figure 11; And fT is approximately 42 GHz, as shown in Figure 12. 1E81E91E101E111E1251015202530 Power Gain (dB)Frequency (Hz)1 Figure 5.11 FinFET transistor power gain versus frequency (0.7V V Δ≈, VDS=1.2V). 1E81E91E101E111020304050 Current Gain (dB)Frequency (Hz)1 Figure 5.12 FinFET transistor current gain versus frequency (0.7V V Δ≈, VDS=1.2V). 45 With the transistor working in moderate inversion region (, V50VmΔ≈ Vt=0.1V, VDS=1.2V), tf is approximately 20 GHz, as shown in Figure 5.13. Antf of 20GHz is adequate to design low GHz applications when transistor works in moderate inversion region. 1E81E91E101E11510152025303540 Current Gain (dB)Frequency (Hz)1 Figure 5.13 FinFET transistor current gain versus frequency (50VmV Δ≈, VDS=1.2V). Since the FinFET with 80nm channel length works in velocity saturation region, the transition frequency, tf can be rewritten as, ()132243noxsatmnTgsoxCWEgECLWLCμμω≈≈= sat (5.3) In the velocity saturation region the transit frequency is inversely proportional to the channel length, which is different from that in the strong inversion region. The maximum frequency of unit power gain can be rewritten as [33], ()2TMaxfringegSgsffCRRgmC=⎛⎞+⋅⋅⎜⎟⎜⎟⎝⎠ (5.4) 46 5.2.3 Noise Measurement Figure 5.14 shows noise measurement made on FinFET transistor. It also demonstrated less lowfrequency noise in moderate inversion than in the strong inversion [34]. It further supports FinFET use in moderate inversion operation in the design of RF circuits. Figure 5.14 The low frequency noise of the FinFET for L=120nm, W=4.2um [9]. 5.2.4 Capacitance Measurement Measurements were performed on a Keithley 590 CVmeter and Keithley 4200 semiconductor characteristics analyzer. All measurements were performed in the dark chamber. For the equilibrium CV measurement, the hold time and delay were set to 5 sec and 1.5 sec, respectively. The gate voltage sweep rate can be calculated as (bias range)/(total sweep time). The source and drain are shorted together, i.e. Vd = Vs = 0 V. Figure 5.15 shows the high frequency gatetochannel capacitance (hfCgc) curve of an n 47 channel FinFET. The hfCgc reaches its maximum value when the channel is in strong inversion and exhibits a minimum with reverse gate bias. Figure 5.15 Equilibrium high frequency CV curve. The CV measurement is a valuable diagnostic tool to characterize MOSFET. Therefore, if the influence of gate depletion capacitance can be neglected, the measured maximum gatechannel capacitance is equal to oxide capacitance. The extracted oxide thickness found is 2.4 nm, which is different from the designed 2 nm thickness [35]. 5.3 FinFET Model 5.3.1 FinFET SmallSignal Model The framework for generic physics based doublegate MOSEFT modeling has been recently reported [36]. However, to our best knowledge there is no FinFET smallsignal model describes its behavior in GHz region. The FinFET structure investigated is depicted in Figure 5.16, where key geometry parameters are defined. The fabricated 48 transistor is shown in Figure 5.17. Based on the measurement results from this device, we developed a high frequency small signalmodel. Figure 5.16 The 3D FinFET. Tbox=400nm, Hfin=50nm, Tsi=20 nm. Figure 5.17 Die picture of the circuit with test frame. Figure 5.18 FinFET transistor characteristics (W=72 um, L=80 nm). 49 The FinFETs were fabricated at SPAWAR system center, San Diego. The gates of the FinFET were ebeam written at Berkeley with a range of 50 to 200 nm, and the overall gate width is 72 um. There are 720 fins in this transistor, and the gate width (2Hfin) for each fin is 100 nm. The DC IDVDS curves are shown in Figure 5.18. The Sparameters were measured with an Agilent 8510 Network Analyzer and Cascade RF1 probe station using GSG probes. The data was collected from 45 MHz to 10 GHz. The equivalent circuit shown in Figure 5.19 is based on a quasistatic approximation, which is found to be adequate in the GHz range if the extrinsic components are properly modeled [37]. This model includes the complete intrinsic quasistatic MOS model, the series parasitic impedance of the gate, source and drain, as well as a substrate coupling network. The extrinsic part includes the parasitic series resistors Rg, Rd and Rs, and the parasitic series inductors Lg, Ld and Ls. The intrinsic model is composed of the voltagecontrolled current source, the output resistance and the gate to channel impedance, as well as the intrinsic capacitors Cgs, Cgd and Cds. 50 Figure 5.19 The FinFET smallsignal equivalent model. Figure 5.20 Zero bias smallsignal equivalent model. The parasitic resistance is extracted at low frequency with the device biased at VGS=VDS=0V. Under this bias condition the contribution from the intrinsic circuit vanishes except the three capacitors between the intrinsic nodes. In addition, in the low frequency region the parasitic inductors and the substrate coupling can be neglected. The schematic of the zero bias equivalent circuit at low frequency is shown in Figure 5.20, from which the parasitic resistors can be extracted by the Zmatrix components: 11Re()gsZRR=+ (5.5) 22Re()d s ZRR=+ (5.6) 1221Re()Re()sZZR== (5.7) After the parasitic resistors have been extracted, the parasitic inductors can be modeled separately by means of the transmission line equations [38]. With the knowledge of the parasitic resistance and inductance, the intrinsic model can be determined. First, the Sparameters measured at low frequency and under the bias condition of Vgs=0.6V and Vds=1.2V are converted to the Zparameters. Next the parasitic resistance terms are deducted, which is shown in Equation (5.8)(5.11), in this way the intrinsic Zparameters are obtained. In the intrinsic model most of the 51 components are in shunt connection to the internal source node, so the Zparameters are converted to the Yparameters, and then the circuit elements in the intrinsic model have been extracted. The circuit elements in the substrate network are fitted with the high frequency measurement results from inductor model extraction [39]. In Table 5.1 we list the extracted model parameters. '1111( ) gsZZRR=−+ (5.8) '2222(ds) ZZRR=−+ (5.9) '1212sZZR=− (5.10) '2121sZZR=− (5.11) '' (5.12) Z →Y Table 5.1 Extracted Model Parameters Lg(pH) Rg(Ω) Rd(Ω) Ld(pH) Rs(Ω) Ls(pH) 100 4.6 10 50 10 50 Cf(fF) Cdep(pF) Cgs(fF) Rch(Ω) gm(S) t (ps) 66 1 300 10 0.1 5 Rds() Ω Cds(fF) Cgb(fF) Rgb(Ω) Csb(fF) Rsb() Ω 450 260 5.6 110 11.2 60 Cdb(fF) Rdb(Ω) Rdsb(Ω) 11.2 60 98 52 Figure 5.21 and 5.22 show the comparison between the measured data and the simulation result from the extracted model. The discrepancy is within 5%, which is calculated from the following equation: 2''2211Re()Re()Im()Im()100ijijijijijijSSSSErrornS==⎡⎤−+−⎢=⎢⎢⎥⎣⎦ΣΣ ⎥⎥ (5.13) In summary, we developed a RF small signal model of FinFET from the extracted data, and good agreement between the model and the measurement is achieved up to 10 GHz. freq (45.00MHz to 10.05GHz)S12S22S11 Figure 5.21 Measured (dot) and modeled (line) Sparameters (Vgs=0.6V, Vds=1.2V). Figure 5.22 Measured (dashed) and modeled (solid line) S21 (Vgs=0.6V, Vds=1.2V). 53 5.3.2 FinFET BSIMSOI Model FinFET BSIMSOI Model was extracted by using Utmost, a Silvaco package [40]. A Semiconductor Analyzer (HP4155A) was used to measure the IV curve. Then the DC parameters were extracted by using DC routines in Utmost. A CapacitanceVoltage meter (Keithley CV590) was used to measure all capacitance and network analyzer (HP8720D) was utilized to do Sparameter measurement. Through AC routines in Utmost, AC and capacitance parameters have been extracted. In addition high temperature and noise measurement were done by my lab mates. After all these measurement and data analysis were finished, a complete FinFET BSIMSOI V3 model has been extracted. The detailed model parameters and simulation and measurement comparison are shown in Appendix B. 5.3.3 FinFET Model Summary Both smallsignal model and BSIMSOI model are presented in the previous sections. The smallsignal model demonstrates the feasibility of FinFET operated in velocity saturation region. The BSIMSOI model supplies the opportunity to simulate the RF circuits working in moderate inversion with Cadence RF spectre tools. But the threshold voltage is approximately 0.1 V, which is not practical for RF circuits design. It is a fabrication process problem. But the FinFET fabrication process is still improved. For example, Molybdenum gate technology has been applied to modify the threshold voltage of FinFET transistors, and it was successfully adjusted to 0.4 V [32]. In this work it is reasonable to justify the threshold voltage to 0.5 V. The selected model parameters are shown in Table 5.1. This model will be used in the later chapters to simulate the RF 54 receiver circuits in moderate inversion. The Figure 5.23 compares the measured ft to the modeled ft curves in moderate inversion. The good agreement is found between the measurement and model simulated ft curves. Table 5.1 The modified FinFET BSIM3SOI model. model NFIN b3soipd type=n + tnom=27 version=3.1 tox=2.4e9 + tsi=2e8 tbox=4.0e7 xj=1e8 + nch=4.46e14 vth0=0.5 nlx=1.468104e8 + dvt0=2.5477237 dvt1=0.542419 dvt2=1.416439e4 + u0=400 ua=2.35143e10 ub=1e18 + uc=1.232366e9 vsat=1e4 a0=1.0446036 + ags=0.5742591 b0=1e8 b1=1e7 + lint=1.683313e9 eta0=0.01 mobmod=1 + capmod=2 cjswg=2e10 cgdo=3e10 + cgso=3e10 rsh=600 + nrd=50 nrs=50 55 1E8 1E9 1E10 0 5 10 15 20 25 30 35 40 45 50 Current Gain (dB) Frequency (Hz) Frequency (Hz) Figure 5.23 Measured (dot) and modeled (line) h21 (50VmV Δ≈, Vds=1.2V). 5.4 Summary Based on the above measurement data and analysis we found the FinFET transistor is a promising deepsub micron device. The promising features of the FinFETs include high frequency, low supply voltage and low gate leakage current, making it an ideal candidate for the design of low power RF frontends. It has excellent performance in both strong and moderate inversion regime. Specifically, its ft is approxiamtely 20 GHz in moderate inversion regime, which makes it feasible to realize the ultralow power RF receiver frontend. The only problem of current FinFET transistors is the negative threshold which makes it hard to be biased. The threshold voltage of FinFET transistor model is assumed to be modifiable to a positive value. For an instance, the VTH0 is set to 0.5 V for long channel device. 56 57 Chapter 6 GPS Receiver Design 6.1 Introduction In Chapters 3 and 4 the passive devices, onchip inductors and varactors, were modeled. They will be used in the following chapters to design the RF circuits for the GPS receiver. In Chapter 5 FinFET transistors were measured and characterized. It did have good performance. Especially, the fT is around 20 GHZ at moderate inversion, which is enough to realize the circuits working below 2 GHz. The model developed was also valid for moderate inversion and it showed good agreement with the measurement. We will take advantage of the features of FinFET moderate inversion to realize the GPS receiver frontend circuits so that it can operate in ultralow current. As we know, the GPS is a satellitebased location/time finding system with 24 satellites orbiting the earth. It is a direct sequence spread spectrum (DSSS) functioning at two bands: L1 (1575.42 MHz) and L2 (1227.6 MHz) [41]. Most commercial GPS receivers use the L1 band only. The L1 band has two sets of codes, coarseacquisition (C/A) and precision (P). The original 50 bit/s data is spread over a 2 MHz bandwidth (BW) for the C/A code, as shown in Figure 6.1. 58 Figure 6.1 The GPS L1/L2 band signal spectrum [42]. At the antenna of a GPS receiver, the received signal power is typically 130 dBm. Since we are interested in the 2 MHz main lobe of the C/A code, the noise power is simply given by kTBW, which equal 111 dBm. Therefore, the received signaltonoise ratio (SNR) at the antenna is around 19 dB. By despreading and integrating over a long time period, a receiver can exploit the inherent spread sprectrum processing gain of the navigation signals to get the proper postcorrelation signaltonoise ratio (SNR). 6.2 GPS Receiver Architectures 6.2.1 Typical GPS Receiver Architectures There are two architectures widely used in commercial GPS receivers today. The first is the dualconversion architecture, which is used widely. In this architecture, the L1 band is translated to a moderate intermediate frequency (IF) of approximately 100200 MHz where it is filtered by offchip filter before a second downconversion to a lower IF of about 110 MHz. Finally, the signal is filtered again before being amplified to a detectable level, as shown in Figure 6.2. 59 1LOω2LOω Figure 6.2 Dualconversion GPS receiver. The second is the singleconversion architecture, as shown in Figure 6.3. Here only one mixer is used. The L1 is directly sampled and then converted to baseband in a subsequent digital step. BPFLNA1LOωOffchip Figure 6.3 Singleconversion GPS receiver. Both architectures have a common advantage. An offchip LNA or active antenna is used, which gives the freedom to remotely place the antenna from the receiver itself. But they also have disadvantages. Either dualdownconversion or singleconversion architecture needs offchip components which increase the power cost and foot print. In order to realize high integration and low power consumption, CMOS lowIF GPS receiver architecture has been presented next to minimize the usage of offchip components and realize singlechip solution. 60 6.2.2 LowIF Architecture In general the lowIF receiver architecture is based on the replacement of the lowpass filters of a zeroIF receiver by a bandpass filter. The LowIF receiver is insensitive to DC offsets and LO to RF crosstalk or feed through. But it suffers from the problem of limited image rejection due to the need for stringent matching of inphase (I) and quadrature (Q) channel [43]. This limitation makes the lowIF approach unsuitable for many applications. However, when we examine the GPS signal spectrum, an opportunity emerges [44]. Figure 6.4 (a) shows a lowIF architecture with an IF of 2 MHz. The choice of 2 MHz lowIF results in an image frequency within the Pcode 20 MHz bandwidth. Thermal noise dominates the 20 MHz Pcode band. With an IF of 2 MHz, since the image frequency of C/A code lies in the Pcode band, no other strong signals are present in this band, as shown in Figure 6.5. Thus, the receiver only need reject the noise of unwanted sideband. The required rejection is only about 15 dB, which is easily obtained with ordinary levels of component matching [45]. This consideration makes the lowIF architecture an attractive choice for highly integrated GPS receiver. /2π Figure 6.4 Block diagram of CMOS GPS receiver. 61 Figure 6.5 The GPS band signal spectrum after downconverted to 2 MHz IF [44]. The complete analog signal path is integrated, including the low noise amplifier (LNA), the mixer, I and Q local oscillator (LO) drivers, IF amplifier (IFA’s), active filters, limiting amplifier (LA), and analogtodigital (A/D) converters. Since most components are integrated, the power consumption can be reduced. In general, lowing the frequency gives an immediate return on power saving. As was reported in Shaeffer’s work [44], since the output intermediate frequency of mixer is around 2 MHz, most power is consumed before the IFA’s. Over 60% of the power is consumed by the LNA, VCO and mixer. Therefore, in this work low power LNA, Mixer and LO designs were concentrated, as shown in the gray shaded area of Figure 6.4. The final objective is to design ultralow power LNA, mixer and LO. 6.3 Receiver System Design With the architecture of the GPS receiver determined, the receiver system planning is discussed next. The key point is to trade off the gain, noise figure (NF), and linearity properly among all circuits, such that every block can be implemented to satisfy low power requirement. Conventional RF system uses 50 Ω matching network at input 62 and output ports. However, in a low power RF receiver frontend with a single chip solution, except the first stage input impedance need to match antenna impedance, the following stages do not need to match 50 Ω or 75 Ω impedance, because it consumes large amount of current [6]. Such system is presented in Figure 6.7. Figure 6.7 Cascaded stages of receiver system. It can be shown that the intermodulation grows and accumulates through the cascades, and could be described, 112123113333cascadeGGGIIPIIPIIPIIP≅+++⋅⋅⋅ (6.1) where IIP3n is the IIP3 of the nth stage and numeric value, Gn is the power gain of nth stage. As for the noise of a cascaded system, assuming the first input stage of the cascade is matching to a source impedance of RS, and the following stages all have high input impedance and NF of each stage is calculated with respect to the source impedance driving that stage, the cascaded noise factor can be expressed as, 321111211ncascadeNnnFFFFFGGGG− 1 −−−=+++⋅⋅⋅+Π (6.2) where Gn and Fn is the power gain and noise factor of nth stage, respectively. Here, we assume that the individual stage’s characterization can be directly used to derive the 63 overall system performance. Namely, the loading from subsequent stage will not alter the noise and gain performance of the previous stage. This is a reasonable assumption in this work since the interstage loadings are capacitive and can be treated as high impedance. It also can be found from the above equations, increasing the gain in early stages improves the total NF, but at the cost of worse IIP3. Since in this work there is no IIP3 or IIP2 problem we could try to pursue the gain of LNA as high as possible with low noise figure. 6.4 Receiver Implementation Requirements To satisfy the stringent power requirement, it is necessary to properly specify and optimize the receiver specifications. Unlike other wireless communications systems, the GPS requirements were not well defined and specified in the literature until recently [42]. There are three noticeable differences between GPS and a conventional wireless standard. Firstly, GPS has only one RF channel in each band. Secondly, there is no strong inband interferer as is common in a cellular system. All these differences offer a good opportunity to build a lowpower GPS receiver. In the following section the receiver specifications are derived. 6.4.1 Noise Figure Figure 6.8 Block diagram of the GPS receiver. 64 In this work, a CMOS GPS receiver frontend is followed by an ADC and digital correlator, as shown in Figure 6.8. The purpose of a GPS receiver is to extract the accurate position and time information from the weak satellite signal. There also exist various source of position error. Some of the errors are from the satellite and propagation delay. The others are from the receiver impairments, such as noise. In order to account for the radio impairment, an important signal quality metric, the signaltonoise ratio (SNR) will be reviewed next. However, the SNR of direct sequence spread spectrum (DSSS) scheme is function of the position in the receiver under consideration. The precorrelation SNRs are negative, whereas postcorrelation SNRs are positive. It is convenient to normalize the SNR to 1Hz bandwidth. This achieves a ratio of signal and noise which is bandwidthindependent. It is referred to as the “carriertonoise density” ratio [46]. The carriertonoise density can be readily converted into SNR (S/N) or bit error rate (Eb/No), bbooECSBRNNN⎛⎞⎛⎞==⎜⎟⎜⎟⎝⎠⎝⎠ (6.3) where B is the bandwidth (in Hz) of that stage of receiver, Rb is a raw data rate of 50 b/s for L1 C/A band. This equation is converted into decibels []()01010log()CNdBHzSNRB⎡⎤−=⎣⎦ (6.4) From the above equation, it can be found that C/N0 is a nominal figure. Received satellite signal power varies with user antenna gain, satellite elevation angle, and satellite age [47]. Typical C/No range from 3555 dBHz. 65 Once the minimum required C/No is presented or processed by a digital correlator to maintain the wanted tracking or acquisition performance, the receiver sensitivity is uniquely determined by (6.5) without any confusion caused by the bandwidth ambiguity. [][][]minooCdBmSensitivitydBmdBHzNNFdBNHz⎛⎞⎡⎤=−++⎜⎟⎢⎥⎣⎦⎝⎠ (6.5a) [][][]minooCdBmSensitivitydBmdBHzNNFdBNHz⎛⎞⎡⎤=−++⎜⎟⎢⎥⎣⎦⎝⎠ (6.5b) where No is the thermal noise power density at the antenna port which is equal to 174 dBm/Hz at typical room temperature and NF is the noise figure of the receiver. Assuming that a digital correlator requires a (C/No)min of 35 dBHz and the receiver sensitivity requires 133 dBm. Assuming a 2bit ADC the NF can be calculated to be 6 dB from equation (6.5). This NF includes both receiver front end and A/D converter (ADC)’s NF. As we know, both singlebit and multibit ADC are currently used in GPS receiver. Most lowcost commercial receivers employ 1bit sampling in narrow (i.e., 2 MHz) bandwidth. Highend receivers typically use anywhere from 1.5bit (3 level) to 3bit (8 level) sampling in bandwidth ranging from 220 MHz. Finitebit quantization degrades the signal [48]. The degradations of different bit ADC are listed in Table 6.1. Table 6.1 Signal degradation due to finite quantization in the ADC. 1bit ADC 2bit ADC 3bit ADC Narrow IF bandwidth 3.5 dB 1.2 dB 0.7 dB 6.4.2 Phase Noise 66 In previous section the carriertonoise ratio (C/No) has been used as a figure of merit for the GPS receiver frontend performance. There are several factors degrading C/No, such as finite image rejection ratio (IMRR), phase noise, filter bandwidth and ADC bit resolution. Since in this work we only emphasize on LNA, VCO and mixer design, the effects from IMRR, filter bandwidth and ADC bit resolution are also not considered. The relationship between phase noise and C/No is reviewed. The goal is to find the maximum tolerable phase noise for minimal C/No degradation. Figure 6.9 Reciprocal mixing of the inband thermal noise and phase noise [42]. The phase noise requirement comes from the reciprocal mixing of the phase noise spectrum by the inband thermal noise itself, as seen in Figure 6.9. Multiplication in the time domain corresponds to convolution in the frequency domain, and hence the added noise density due to the phase noise is calculated by [42] ()()()()()()''PNINLOINLOoLONNSNSdNS d ωωωωωωωω∞∞−∞−∞=∗=−=∫∫ ω (6.6) where ()LOSω is the phase noise of LO. The last integral term represents the absolute rms jitter of the local oscillator, normalized to its period, ()2,2LOrmsPNLOrmsoLOTNSdNTωωσ∞−∞Δ⎛⎞=≈⎜⎟⎝⎠∫ ≡ (6.7) The effective C/No at the mixer output can be written by 67 ()21111ooPNoormsoutininLOCCCCNNNNNSdσωω⎛⎞⎛⎛⎞⎛⎞⎛⎞⎜⎟==⋅=⋅⎜⎜⎟⎜⎟⎜⎟⎜⎜⎟+++⎝⎠⎝⎠⎝⎠⎝⎠⎝⎠∫ ⎞⎟⎟ (6.8) In order to obtain less than 0.1 dB loss on C/No, the averaged phase noise should be lower than 80 dBc/Hz [42]. From this limit, it can be inferred that smallsized ring voltage controlled oscillator (VCO) is promising low cost solution, as presented in [49]. However, when considering power consumption, the LC tank VCO is still advantageous since it uses fewer active devices. 6.4.3 Summary Based on the previous discussion, we can conclude the design specifications in Table 6.2. And the gain and noise distribution is summarized in Table 6.3. The parameters in tables will be updated along with the design. Table 6.2 Summary for GPS receiver frontend requirements. Parameters Specification Note Sensitivity 130 dBm At antenna Noise Figure < 9 dB From input of LNA to output of mixer Phase Noise @ <  80 dBc/Hz For VCO. C/No 35 dB For whole GPS receiver frontend ADC 2bit 1.2 dB signal loss Current < 4.5 mA Limited to LNA, VCO and mixers Power < 4.5 mW Limited to LNA, VCO and 68 mixers 69 Chapter 7 UltraLow Power Low Noise Amplifier (LNA) Design 7.1 Introduction The first stage of a RF receiver is a Lownoise amplifier (LNA), whose main purpose is to provide enough gain to overcome the noise of subsequent stages (such as mixer) and linearity while not degrading the signaltonoise ratio. Much valuable research on CMOS LNA design in submicron technologies has been done in recent years: from the topology investigation [50, [51, [52], and the design guidelines [53], to various new ideas on design improvement for low noise figure [54, [55, [56], high power gain [54], low power consumption [55], and high linearity [57]. The frequency range of these CMOS LNA designs is from 900 MHz to 5.2 GHz [58, [59], and the technologies in use is as small as 0.18 um or less. In this chapter, an ultralow power LNA is implemented using SOI deepsubmicron (SOIDSM) 80 nm FinFET technologies. As described in Chapter 5, the doublegate MOSFET (FinFET) is considered as one of the most attractive devices to succeed the planar MOSFET. With two gates controlling the channel, the shortchannel effects are greatly suppressed. The transition frequency of the characterized FinFET transistors is 42 GHz when working in velocity saturation region, and 20 GHz when working in moderate inversion. With the FinFET transistors operating in moderate inversion, the operation current will be several times smaller than that in saturation for a given transconductance. 70 As a result, the FinFET transistors open the door to realize micropower frontend applications. In chapter 6 the GPS receiver architecture, design methodologies, and implementation requirements were discussed. All of those are optimized to meet the low power requirement. In this chapter, the LNA topology choice is illustrated first. Then the ultralow power LNA is proposed. Finally, the performance is presented and compared with previous designs. 7.2 LNA Topology Choice The four most widely used topologies, shown in Figure 7.1, are reviewed. One will be selected for use in the low power GPS receiver. The first topology shown in Figure 7.1(a) uses resistive termination of the input port to provide 50 Ω impedance. The drawback of using of real resistors is that the added resistor contributes its own noise comparable to that of the source resistance [60]. According to the calculation [60], the noise figure will be above 6 dB. It does not satisfy our system requirement for noise figure. 71 Figure 7.1 Common LNA topologies. (a) Resistive termination, (b) 1/ termination, (c) shuntseries feed back, and (d) inductive degeneration. mg Figure 7.1 (b) shows the second topology which uses the source of MOSFET in a commongate (CG) configuration as the input termination. CG topology has good high frequency performance. The minimum theoretically achievable noise figures tends to be around 3 dB or greater in practice. Input impedance is determined by1/. mg Figure 7.1 (c) represents another topology, which utilizes shunt and series feedback to set the input and output impedances of the LNA [61]. It is a broadband amplifier, but it has very high power dissipation compared to others with similar noise performance. For a GPS receiver, a broadband front end is not required and it is desirable to use narrowband technology to save power and reduce interferers. 72 Figure 7.1 (d) employs inductive source degeneration to generate a real term in the input impedance. At the operational frequency, the source inductor provides a stable 50 Ω input impedance. It is the most prevalent topology used for LNA design. And it offers the possibility of achieving the best noise performance of any architecture [50]. Based on above analysis, it seems that the commongate LNA (CGLNA) and commonsource LNA (CSLNA) topology is good candidate for GPS receiver. The detailed analysis and comparison of CGLNA and CSLNA is reviewed below. 7.2.1 Commonsource LNA (CSLNA) The CSLNA is based on the commonsource with source inductive degeneration amplifier. Figure 7.2 shows the schematic of a popular cascade singleended CSLNA. At the operation frequency, the input inductors Ls provides stable 50 Ω input impedance. The input inductors Lg, Ls and input device gatetosource capacitance, Cgs provide the operational frequency for CSLNA. Figure 7.2 CSLNA Schematic Diagram. A simple analysis of the circuit depicted in Figure 7.2 shows that the input impedance of the circuit is given by (7.1) when neglecting the M1 draingate overlap 73 capacitance, and the inductor parasitic elements toward the substrate (Cox, Rsi and Csi in Figure 3.3(a)) ()1mingssgLgLsgsgsgZjLLLRRRjCCωω=++++++ (7.1) where Cgs amd gm are respectively the gatesource capacitance and the transconductance of M1 and Rg the gate resistance of M1. RLg and RLs represent the parasitic series resistance of Lg and Ls, respectively. At resonance, the imaginary term of Zin will be zero, which gives ()10gsgsLLCωω+−= (7.2) From (7.2) the center frequency can be derived, ()1ogsgsLLCω=+ (7.3) The real part of the input impedance is ,minrealgLgLssgLgLsTTgsgZRRRLRRRLsLsCωω=+++≈+++≈ (7.4) where Tω is an approximation of the transition frequency of M1. Using (7.4) the inductance of source inductor can be determined. Once Ls has been determined Lg can be calculated by (7.3). One of the most attractive advantages of this topology is that the inductor used to match the input impedance is noiseless, unlike the topology shown in Figure 7.1 (a), which employs a noisy resistor in the signal path to provide the 50 Ω termination resistance. This explains the low noise performance and popularity of the inductively degenerated CSLNA. 74 The effective smallsignal transconductance of the input transistor is a parameter which accounts for the transconductance for input transistor and input matching network. ()1mTmmogssTsTsossgGgQCRLLRRωωωωω===+⎛⎞+⎜⎟⎝⎠ (7.5) Note that the input matching circuit is a pure series RLC resonant circuit. At resonance the voltage across Cgs is enhanced by Q times, where Q is the quality factor of input matching RLC network. In other words, the Q enhancement mechanism provides a free gain of Q for both the input signal and the noise from the source resistance Rs. The added gain from the input matching circuit helps to suppress channel noise. If the input is matched to Rs, we have 12TmsoGRωω⎛=⎜⎝⎠ ⎞⎟ (7.6) It is worth noting that the effective transconductance Gm is only related to the ratio of Tω to oω and is independent on the MOSFET smallsignal transconductance. mg The gatetodrain capacitance Cgd provides a feedthrough path from input to output, decreasing the reverse isolation. In addition, the miller effect of Cgd provides a shunt current branch at the input, which further complicates the input matching. One should add a cascode stage to mitigate the Miller effect of Cgd and improve reverse isolation. Next, the noise performance of CSLNA is analyzed. Starting with the noise model of a MOSFET, as shown in Figure 7.3, we surmise that their main noise sources are the thermal channel noise and the induced gate noise. 75 Figure 7.3 MOSFET equivalent noise model. The channel thermal noise id shows a white power spectral density described by 204ddikTgγ= Δf (7.7) where is Boltzmann’s constant,is the zerobias drain conductance, k0dgfΔis the bandwidth of interest and γis a biasdependent factor that, for long channel devices, satisfies the inequality 213γ≤≤ (7.8) the value of 2/3 holds when the device is in saturation mode and the value of one is valid when the drainsource voltage is zero. For shortchannel devices, however, γis much greater than 2/3 for devices operating in saturation [50]. For the present there is no standard γ value for devices operating in moderate inversion. In addition to channel thermal noise id, a companion noise current ig at the gate of the MOSFET, which is known as induced gate noise, has been observed in both theory and experiment, 24gikTgδ=g f Δ (7.9) 76 ()205gsgdCggω= (7.10) where δ is another biasdependent empirical parameter, classically equal to 4/3 for longchannel devices. Unlike the white noise spectrum of the channel thermal noise, induced via the gate noise has blue spectrum frequency. The gate noise is partially correlated with the drain noise, with a correlation coefficient given by [62] *220.395gdgdiicii=≈ j (7.11) Figure 7.4 Smallsignal model for noise calculation of CSLNA. After determining the noise source of MOSFET, we will derive the noise factor of the CSLNA. To obtain the expression for noise factor, it is instructive to calculate the transfer functions of the different noise source in the CSLNA [63]. The smallsignal circuit used in the computation is shown in Figure 7.4. In this CSLNA noise model five noise sources are considered, input impedance noise, series resistance noise from gate inductor, gate resistance noise from input MOS device, channel thermal noise of MOS device and induced gate current noise. The noise factor is derived according to its definition, that is, the ratio of total output noise power to the output noise power due to input source impedance, as shown 77 ()222111155LggTRRFRsRsQγωδαδα Q 2 c αωγ γ ⎡⎤⎛⎞⎢⎥=++++++⎜⎟⎢⎥⎝⎠⎣⎦ (7.12) where 0mdggα≈ (7.13) For longchannel device, α= 1. For shortchannel device,1α≤. 7.2.2 Commongate LNA (CGLNA) Figure 7.5 shows a CGLNA where the gate terminal is shorted to an AC ground and the input signal is injected at the source terminal. The resistance looking into the source terminal is about 1mg, which provides the input 50 Ω match. Unlike CSLNA, there is no Miller effect associated with Cgd in CGLNA, which results better reverse isolation. RSVinZinVbiasM1Lload Figure 7.5 the CGLNA schematic diagram. The effective smallsignal transcondance of the input transistor of CGLNA is 12msGR= (7.14) 78 However, the CGLNA suffers from the presence of a noisy channel conductance in the signal path, which attenuates the noise performance. It can be shown that under perfect input matching, the CGLNA has the following noise factor [60] 215TFγδαωαω⎛⎞=++⎜⎟⎝⎠ (7.15) In the above equation, the third term is from the contribution of the induced gate noise, which is negligible compared to contribution of channel noise. Neglecting gate noise for a CGLNA is reasonable approximation since the gate noise is not amplified, unlike it in CSLNA. Therefore, the noise factor of CGLNA is approximated by 1Fγα=+ (7.16) In CSLNA we can not make this approximation since the gate noise is amplified and becomes comparable to channel noise. 7.2.3 Comparisons of CSLNA and CGLNA Based on the above discussion, the detailed comparison is listed in Table 7.1. Table 7.1 The comparison between CSLNA and CGLNA (“+” indicates better, “” indicates worse). CSLNA CGLNA Comments Gain + – 01122TCSLNACGLNAssGGRRωω⎛⎞=>=⎜⎟⎝⎠ Noise Figure + – Discussed above Input matching – + CGLNA has lower Q parallel resonant network. Reverse isolation – + Cgd in CSLNA provides a feedforward path between input and output. 79 In this work the NF for receiver frontend requirement is less than 6 dB in order to obtain the desired GPS receiver sensitivity, as discussed in Chapter 6. So the topology CSLNA is used to achieve low noise and low power GPS receiver front end. Once selecting the CSLNA topology, the next question is to take either a singleended or differential architecture. The signalended LNA architecture has at least one important shortcoming, and that is sensitivity to parasitic ground inductance. There are several advantages in using a differential LNAs. Firstly, the use of Gilbert mixers and the lowIF architecture requires a differential feed source. If the singleended is taken we need to add a Balun to generate the differential signal. The Balun itself has about 0.5 dB loss. Secondly, the virtual ground formed at the tail removes the sensitivity to parasitic ground inductance, which makes the real part of the input impedance purely controlled by the source degeneration inductance (Ls). Thirdly, the differential amplification of signal ensures attenuation of the common mode signal. But for equal total power consumption, the noise figure of differential LNA is higher than its singleended counterpart. Specifically, the power consumed is twice that of a singleended LNA to achieve the same noise figure. Since it is hard to tell which architecture is better for this application, both architectures will be taken to implement the ultralow power GPS receiver frontend circuits. Next the ultralow power FinFET differential LNA design is described. The singleended LNA is just the half circuit of differential LNA. It has the same NF but only consume half power of differential LNA. 80 7.3 Circuit Design The LNA design starts from noise optimization because of the tight noise requirement. The input devices are required to work in moderate inversion region to reduce amplifier drain current with the exception of the tail current source. All the formula used to estimate the noise is for MOSFET apply in moderate inversion. Starting from the noise analysis, we found the minimal transcondance to achieve the lowest noise figure. Once gm is found to be 20 mS, the drain current can be determined by referring the inversion coefficient curve with IC equal 0.1 to 1 in Figure 7.6. The curve in Figure 7.6 is drawn for 80 nm FinFET transistors with the description in 2.3.1. The mDgI of around 20 to 40 is achievable in this range. Taking the average value 30, we can get 30666DmIg==uA. The tail current will be twice the ID, 1.3 mA. The aspect ration of M1 and M2 can be calculated by choosing bias current: ()DtIWLIIC= (7.17) where IC is the desired inversion coefficient, which is about 0.15. It is specific current, (7.18) 22tnoxInCUμ= T which is about 1.46 uA for 80 nm device. The W/L is determined about 3000. Knowing channel length equal to 80 nm the width of input device is determined to be 240 um. 81 105104103102101100101102101100101102gm/IDInversion Coefficient (IC)L=0.08um Figure 7.6 gm/ID versus inversion coefficient curve. Knowing gm, device size and Cgs, the transition frequency of input device is mTgsgCω≈ (7.19) 82 VddLdLsLgM1M3LdLsLgM2M4Vbias1Vbias1Vbias2Vbias2IF+RF+RFIF Figure 7.7 Proposed differential LNA schematic. The source inductance can be determined once the source resistance Rs is set to 50 Ω. ssTRLω= (7.20) Lg can be determined by 201gsgsLCω=−L (7.21) Where 0ω is the center frequency of GPS L1 band. 83 The complete LNA schematic is shown in Figure 7.7. All passive components values in design are summarized in Table 7.2. All active devices are summarized in table 7.3. Table 7.2 Differential LNA passive components values. Ls Lg Ld 100 pH 20 nH 15 nH Table 7.3 Differential LNA active components values. Devices Threshold voltage Sizing (um/um) IC Overdrive Voltage M1 M4 0.33 V 250/0.08 0.12  15 mV 7.4 LNA Performance Periodic SteadyState (PSS) and SParameter (SP) simulation are adopted to measure the gain, noise and linearity performance separately. In SP simulation, the voltage gain of LNA is determined by plotting S21 versus frequency. Figure 7.8 shows the maximum voltage is 21 dB at 1.57 GHz. And the S12, S11 and S22 are 30 dB, 15 dB and 4 dB, respectively, as shown in Figure 7.9 and Figure 7.10. The noise performance is measured by NF shown in Figure 7.11, which is about 2.6 dB at 1.57 GHz. If the gate induced noise is counted it will reach 3.4 dB which is dependent on device model used. Stability measurement of LNA is presented in Figure 7.12. 84 The LNA’s linearity can be measured by 1dB compression point, as shown in Figure 7.13. The 1dB compression point is 35 dBm. The performance summary for proposed LNA is listed in Table 7.4. Compared with the differential LNA designs previously published, the resulting LNA consumes only 1.08 mW with 1 V supply voltage. Figure 7.8 Voltage gain of differential LNA. Figure 7.9 S12 of differential LNA. 85 Figure 7.10 S11 and S22 of LNA. Figure 7.11 Noise Figure of LNA. 86 Figure 7.12 Stability measurement of LNA Figure 7.13 1dB compression point measurement of LNA 87 Table 7.4 Ultralow power LNA performance summary Technology 0.08 um FinFET Supply Voltage (Vdd) 1 V DC Current 1.44 mA Power Consumption 1.44 mW Threshold Voltage 0.33 V Transition frequency 18 GHz Operation Frequency 1.57 GHz S21, S11, S22 20 dB, 15 dB, 4 dB Noise Figure 3.4 dB 1dB compression 35 dBm Power Consumption 1.44 mW 88 Chapter 8 Micropower RF Voltage Controlled Oscillator Design 8.1 Introduction Voltage controlled oscillators (VCOs) are essential building blocks of modern communication systems and are worked with other building blocks to establish phase lock loop (PLL) to generate stable local oscillation signal, which is provided to the ports of mixer in a typical transceiver architecture to translate data between baseband and frequencies suitable for wireless transmission. In a PLL, all building blocks such as VCO, phase detector and loop filter contribute phase noise at the output. For a well designed PLL, the phase noise of VCO is the dominant source of phase noise [64]. Therefore, in the following discussion, the phase noise of VCO is emphasized. The basic LC oscillator topology is widely used in RF receiver design due to its superior phase noise performance. Consequently, we focus our discussion on LC oscillators. In this chapter, following the oscillation fundamental of oscillator, the topologies of oscillators are compared. Then the proposed VCO design procedures are presented. Finally, the performance of VCO is shown in figures and summarized in table. 8.2 Oscillators Fundamental 8.2.1 Feedback Oscillator Model 89 An oscillator can be viewed as a feedback system as shown in Figure 8.1 where the transfer function from Vin(s) to Vout(s) is ()()()1()outinVsHsVsHs=+ (8.1) For the oscillation to begin, a loop gain of unity or greater is necessary. Oscillation occurs for the condition0()Hjω 1 =. Even without an input, i.e., Vin(s) = 0, the oscillation is selfsustained. To maintain constant amplitude, there are two necessary conditions that must be met at0ω. 00()1()180oHjHjωω=∠= (8.2) Known as Barkhausen’s criteria, these conditions are necessary but not sufficient [65]. In order to ensure oscillation in the presence of temperature and process variations, we typically choose the loop gain to be at least twice or three times the required value. Figure 8.1 oscillator viewed as feedback system. An LC resonant tank is an integral component of LC oscillator circuit in Figure 8.1. It functions as a frequency selective network to eliminate highorder harmonics and thus to stabilize the oscillation frequency, as shown in Figure 8.2. 90 Figure 8.2 Feedback model for oscillator with LC resonant tank. 8.2.2 OnePort Oscillator Model Most oscillators employed in RF applications use LC resonators. They are known to provide high spectral purity and lower phase noise than other types such as ring oscillators, etc. [66]. Monolithic inductors have gradually appeared in bipolar and CMOS technologies in the last decade, which makes it possible to design oscillators based on passive resonant circuits. As shown in Figure 8.3. An inductor L placed in parallel with a capacitor C, building a parallel resonance LC tank, which resonates at a frequency 1LCω= (8.3) Since the LC tank network is composed only of reactive components, the oscillating signal ideally maintains its oscillation amplitude without attenuation. The energy in the LC resonator transfers back and forth between the inductor and the capacitor in the form of the magnetic and electric energy without loss due to power dissipation. In practice, however, the quality factors of the inductor and the capacitor are 91 finite. As a result, this leads to a practical parallel RLC network as shown in Figure 8.3(b). Quality factor Q of this network is defined as: 00RQRL Cωω== (8.4) At this frequency, the impedance of the inductor,jLω, and the capacitor, ()1jCω, are equal and opposite, thereby, yielding an infinite impedance, in theory. The circuit in Figure 8.3 (a) has an infinite quality factor, Q. In practice, inductors (and capacitors) suffer from resistive component, Rp. In order to sustain the oscillation, a practical tank network needs an active circuit that provides a negative resistance, Ra, to cancel out the positive loss resistance of the tank. Such a topology is called oneport oscillator. (a) ideal (b)practical (c) negative R Figure 8.3 LC tank. 8.3 Oscillator Topology Comparison In this section, several oscillator topologies will be compared with an emphasis on their phase noise and power consumption. 92 Figure 8.4 the typical crosscouple oscillator. Figure 8.4 shows the NMOSonly crosscoupled oscillator topology, widely used in highfrequency integrated circuits due to the ease of implementation and differential operation [67, [68, [69]. It can be shown that the smallsignal impedance looking into the drains of M1 and M2 is 2mg−assuming the parasitic capacitance is neglected. To enable oscillation, the negative smallsignal conductance added by the crosscoupled transistor pair should overcome the loss in Rp, that is 1mpgR> or 1mpgR> (8.5) Figure 8.5 shows the complementary version using both NMOS and PMOS transistors. This topology provides a larger tank amplitude for a given tail current in the current limited regime defined in [68]. Since the PMOS is used in this topology, the 93 oscillation frequency is limited by the PMOS. In this work pchannel FinFET transistors can not provide enough bandwidth in moderate inversion. Thus this topology is not considered. Figure 8.5 The complementary crosscoupled oscillator. Figure 8.6 depicts the singleended Colpitts oscillator topology. Compared to crosscoupled VCO, the Colpitts topology features superior phase noise because noise current from the active devices is injected into the LC tank during the tank voltage when the impulse sensitivity is low [70, [71]. The negative conductance is formed using transistor M1 and capacitive divider C1 and C2 in a positive feedback arrangement. Its smallsignal impedance looking into the drain of M1 is calculated using test voltage divided by test current. It can be shown that the negative conductance loading the tank is ()12212mgCCCC−+. Therefore, the startup condition for Colpitts oscillator is 94 ()122121mpgCCRCC>+ or ()21212mpCCgRCC+> (8.6) For a typical case, (8.6) becomes. Comparing to (8.5), we conclude that Colpitts oscillator has more difficult startup condition than the conventional crosscoupled LC oscillator for a given transconductance, i.e., higher power consumption is needed to ensure reliable startup in the presence of process, voltage or temperature variations. And the lack of differential outputs needed to suppress commonmode coupling has hindered its usage in CMOS. 2CC= 1 4mpgR> Figure 8.6 The typical Colpitts oscillator. Figure 8.7 shows a differential Colpitts VCO. With a smallsignal analysis, the startup condition for the differential Colpitts oscillator is given by ()212122mpCCgRCC+> (8.7) 95 Compared to (8.6), the effective smallsignal transcondance is doubled, the startup condition is also relaxed by a factor of two. In a conventional Colpitts oscillator, the tail current is always ON. To reduce power consumption, a switching current source can be employed [72]. Power consumptions is reduced at the expense of added noise from the tail device. The idea is that since in a Colpitts oscillator the MOSFET is on for less than half of a cycle, two switches can be used to steer one current source to the two MOSFETs while sustaining oscillation, shown in Figure 8.8 [73]. Figure 8.7 The typical differential Colpitts oscillator. Although differential Colpitts oscillator has superior phase noise performance than crosscouple differential, it has greater power than crosscouple differential oscillator [72]. Since in this work low power consumption is our research goal and the crosscoupled oscillator already supplies enough phase noise and cost less power than differential Colpitts oscillator, the crosscoupled oscillator is taken to implement the ultralow power VCO. 96 Figure 8.8 The differential Colpitts oscillator with currentswitching technique. 8.4 Oscillator Circuit Design With the VCO topology selected, the design procedures are described in this section. The proposed VCO schematic diagram is shown in Figure 8. 10. Starting with the oscillation frequency equation given in (8.1), we take 1.57 GHz as the target frequency. In Chapter 3, a monolithic model was developed for the onchip inductor with substrate removed. The model is valid for the number of turns as large as 4.5. In this design we will use the complete inductor model for accuracy, where all substrate losses are taken into account. As described in Section 8.2, the crosscoupled pair must provide enough negative resistance to cancel the tank losses and allow oscillation to start up. This negative resistance equals 1,21mg− for half crosscoupled pair. The required for startup sets a lower limit on the current consumption of oscillator. To determine the necessary for startup, the tank losses (RmgmgP) must be calculated from the inductor model. In Chapter 3, the calculated QL was shown to be 97 approximately 10 at 1.5 GHz for an inductor with a substrate. At the resonant frequency, the LC tank may be modeled as depicted in Figure 8.3, where the tank losses are included in the resistance Rp. The equivalent parallel resistance at resonance may be calculated by taking the capacitor as lossless and calculating the parallel resistance Rp for an inductor with finite Q given by the overall tank quality factor, 2pL s RQR≈ (8.8) The required for startup is mg 1mpgR≥ (8.9) For a given operating frequency, it is desirable to use the inductor in the LC tank which has largest pR value. The Table 8.1 shows the inductance, series resistance and Q of inductors with different number of turns at 1.5 GHz. Table 8.1 Onchip inductors specifications at 1.5 GHz. No. turns L (nH) Rs (Ω) Q 1.5 1.34 1.8 7.28 2.5 2.83 3.34 8.39 3.5 6.4 6.15 10.36 4.5 11.52 9.65 11.88 With Table 8.1, the 4.5 turn inductor is taken since it has largest RP value. In practice, the size of the inductor is usually limited by the difficulty of implementing large spiral coils onchip. On the other hand, the critical transconductance is inversely proportional to tank 98 quality factor, so an improvement in inductor Q reduces startup current requirements and lowers power consumption. As described in Chapter 3, inductors large than 12 nH are not normally integrated on chip. RP is approximately 1000 Ohm at 1.57 GHz for 4.5 turns inductor. Therefore, the minimal requirement of is approximately 1 mS. In order to ensure reliable startup, the transconductance is set to 2 mS. mg105104103102101100101102101100101102gm/IDInversion Coefficient (IC)L=0.08um Figure 8.9 Inversion coefficient for L=80 nm FinFET transistor. To optimize the transcondance for minimal bias current, devices M1 and M2 are designed to operate with inversion coefficient between 0.1 and 1. This is the moderate inversion for transistors. Referring to Figure 8.9, mDgI of around 20 to 40 is achievable in this range. Taking the average value 30, we can get 3066DmIg==uA. The tail current will be twice the ID, or 132 uA. The aspect ration of M1 and M2 can be calculated by choosing bias current: ()DtIWLIIC= (8.10) 99 where IC is the desired inversion coefficient, which is about 0.15. It is specific current, which is about 1.46 uA for 80 nm device. So the W/L ratio is determined around 350. The total bias current sourced by M3 is approximately 130 uA. In order to maintain stable tail current a longchannel device is chosen and operation in saturation region is selected for accuracy. The width of M3 is calculated to be about 20 um. All the devices sizing and IC is shown in table 8.2. Table 8.2 Device sizing and IC for oscillator transistor. Device Threshold voltage Sizing (um/um) IC Overdrive voltage M1, M2 0.33 V 30/0.08 0.12 25 mV M3 0.5 V 20/1 10 0.2 V Next, the voltage controlled capacitor design is selected. In this work, the FinFET varactors are used to achieve frequency sweep. All the varactors are nchannel FinFET transistors that have a steplike CV characteristic. Referring to Figure C.3 in Appendix C: “CV characteristic of FinFET”, the FinFET capacitance changes from 2 fF/um2 to 13 fF/um2 with gate voltage swept from 0.5 V to 0.5 V. In order to center the oscillation frequency at 1.57 GHz two varactors are connected in parallel which has width 45 um and length 1um. Its capacitance at zero bias is around 470 fF, and its swept capacitance ratio is 6.5. 8.4 VCO Performance 100 Figure 8.10 Micropower VCO schematics. The completed VCO design is shown in Figure 8.10. Its tuning range is 720 MHz wide around the center frequency of 1.57 GHz (i.e., 45.7%) without considering process, voltage and temperature (PVT) variation, as shown in Figure 8.11. Figure 8.12 shows that the differential output oscillation signal amplitude is around 700 mV, that is, around 350 mV peaktopeaks for single end output. With power supply voltage of 1 V, the phase noise of the VCO is 112 dBc at 1 MHz offset from 1.57 GHz, shown in Figure 8.13. Compared with the VCO design published before, this VCO consumes only 128 uW with 1 supply voltage. 101 0.50.40.30.20.10.00.10.20.30.40.51.31.41.51.61.71.81.92.02.12.2 Output Frequency (GHz)Vcont (V) Figure 8.11 Simulated tuning characteristics of the VCO. Figure 8.12 Output LO signal magnitude versus frequency. 102 Figure 8.13 VCO Phase noise versus frequency. Table 8.3 Summary of VCO performance. Parameters Value Supply voltage 1 V Power Consumption 128 uW Frequency tuning range 1.382.1 GHz LO Vpp 350 mV Phase Noise 111 dBc/Hz @1 MHz offset 103 Chapter 9 Ultralow Power Mixer Design 9.1 Introduction The rapid growth of portable wireless communication systems, such as wireless (cordless and cellular) phones, GPS, wireless local area network (LAN), etc., has increased the demand for lowcost and high performance frontend receivers. Mixers are used for frequency conversion and are the critical components in modern radio frequency (RF) systems which are commonly used to down convert frequencies to achieve frequency translation. The motivation for this translation stems from the fact that filtering out a particular RF signal channel centered among many densely populated, narrowly spaced neighboring channels would require extremely high Q filters. A mixer converts an RF signal at a high frequency into a signal at lower frequency to make signal processing easier and less power consumptive. One of the best known architectures is the downconversion heterodyne receiver, schematically depicted in Figure. 9.1. Here the received RF signal after preamplification in a lownoise amplifier is supplied to a mixer. It is then mixed with local oscillator (LO) frequencyLOf. The signal obtained after the mixer contains the frequenciesRFLOff±, as well as the input signals at RFf andLOf. 104 With a lowpass filter (LPF) or bandpass filter (BPF), the lower frequency componentRFLOff−, known as the intermediate frequency (IF), is selected for further processing. RFLOff±RFfLOfIFf Figure 9.1 The heterodyne receiver system with a mixer. In this chapter, following the fundamentals of mixing, the mixer topology choice is made based on our application. Then the design procedure is discussed to achieve lowpower consumption. Finally, the proposed mixer performance is presented. 9.2 Mixer Fundamentals The ideal mixer is a device which multiplies two input signals. If the inputs are sinusoids, the ideal mixer output is a signal that contains both the sum and difference frequencies given by ()((cos)(cos)coscos2RFLORFLORFLOABAtBttωωωωωω )t ⎡⎤=−++⎣⎦ (9.1) Typically, either the sum or the difference frequency is removed with a filter. If the LO amplitude is constant, any amplitude modulation in the RF signal is also transferred to the IF signal. Having recognized the fundamental role of multiplication, the most important characteristics of mixers are discussed next. 9.2.1 Conversion Gain 105 The gain of mixers must be carefully defined to avoid confusion. The voltage conversion gain of a mixer is defined as the ratio of the root mean square (rms) voltage of the IF signal to the rms voltage of the RF signal. The power conversion gain of a mixer is defined as the IF power delivered to the load divided by the available RF power from the source. If the input impedance and the load impedance of the mixer are both equal to the source impedance, then the voltage conversion gain is equal to power conversion gain in decibels. In this work the LNA output impedance is not matched to source impedance. Thus, the voltage 



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