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POWER MODELING OF CMOS DIGITAL CIRCUITS WITH A PIECEWISE LINEAR MODEL By CHENG CHIH LIU Bachelor of Science Pittsburg State University Pittsburg, Kansas 1999 Master of Science Oklahoma State University Stillwater, Oklahoma 2001 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY May, 2007 ii POWER MODELING OF CMOS DIGITAL CIRCUITS WITH A PIECEWISE LINEAR MODEL Dissertation Approved: Dr. Louis G. Johnson Dissertation Adviser Dr. R. G. Ramakumar Dr. Yumin Zhang Dr. H.K. Dai Dr. A. Gordon Emslie Dean of the Graduate College iii ACKNOWLEDGMENTS I would like to express my gratitude to Dr. Louis G. Johnson for his fiveyear guidance and supports for this dissertation. Without his abundant experiences in the area of CMOS integrated circuits, I could not possibly discover this research topic and the theory behind it. Moreover, I am appreciative of his many helpful advices from design to fabrication of a working prototype of analog integrated circuit for neural recoding application. I also would like thank Dr. R.G. Ramakumar, Dr. Yumin Zhang, and Dr. H.K. Dai for their busy time and valuable feedback with their expertise while serving as members in my committee. Their suggestions and ideas helped me complete this dissertation. A special appreciation goes to Jian Chang, now in the Texas Instruments, in my research group for verifying the piecewise linear delay model. I am also thankful to all the members in our digital VLSI research group, and to Sameer, for discussing many questions in an energy conserving MOSFET model. Last but not least; I appreciate my Dad, Mom, brother, and sister for their supports and encouragements. Without their support, I would not be motivated to pursue a doctoral degree. Especially, I am indebted to my wife, ChinHuey, for her unconditional love and supports throughout my school years, and also my children, John and Amy, being good companies during my studies. iv TABLE OF CONTENTS CHAPTER Page 1. INTRODUCTION .....................................................................................................1 1.0 Purpose of the study...........................................................................................1 1.1 Significance of the study....................................................................................2 1.2 Limitation of the proposed model......................................................................3 1.3 Introduction to the CMOS logic families...........................................................3 1.4 Organization.......................................................................................................5 2. CONVENTIONAL TRANSISTOR MODELS FOR POWER EVALUATION......6 2.0 Definition: Energy or Power..............................................................................6 2.1 Sources of CMOS Power dissipation.................................................................7 2.1.1 Offstate leakage power of the transistor ..................................................8 2.1.2 Switching transient power in CMOS transistors.....................................10 2.1.3 Glitch power dissipation in CMOS transistors .......................................15 2.2 Summary..........................................................................................................15 3. A PIECEWISE LINEAR TRANSISTOR MODEL ................................................17 3.0 Background......................................................................................................17 3.1 Evaluation of average power dissipation with the piecewise linear model .....18 3.1.1 Piecewise linear current model ...............................................................20 3.1.2 Channel storage charge model ................................................................24 3.2 Ramp input approximation ..............................................................................31 3.3 Approximate solution for circuit voltage.........................................................33 3.3.1 Resistive connected region .....................................................................33 3.3.2 Approximate solution for circuit voltage with nonsingular G matrix.....34 3.4 Average turnoff energy evaluation with the piecewise linear current model..37 3.4.1 Zeroorder turnoff current in ohmic region ...........................................38 3.4.2 Zeroorder turnoff current in saturation region .....................................39 3.4.3 Zeroorder turnoff current in cutoff region............................................40 3.5 Average turnon energy evaluation with the piecewise linear current model ..40 3.5.1 Zeroorder turnon current in cutoff region ............................................41 3.5.2 Zeroorder turnon current in saturation region ......................................41 3.5.3 Zeroorder turnon current in ohmic region............................................42 3.5.4 Resistive connected region with steady state input.................................42 v 3.5.4.1 Zeroorder turnon current in saturation region .........................42 3.5.4.2 Zeroorder turnon current in ohmic region...............................43 3.6 Switching energy in the Transistor parasitic capacitances ..............................45 3.7 Summary ..........................................................................................................47 4. AVERAGE POWER ANALYSIS OF INVERTER WITH THE PWLMODEL...49 4.0 Introduction......................................................................................................49 4.1 Energy per cycle analysis of inverter driving load capacitance.......................49 4.1.1 Turnoff energy analysis .........................................................................51 4.1.2 Turnon energy analysis..........................................................................53 4.1.3 Switching energy in the transistor parasitic capacitances.......................54 4.2 Energy per cycle calculation............................................................................55 4.2.1 Energy per cycle evaluation from the model .........................................55 4.2.2 Energy per cycle simulation from SPICE..............................................57 4.3 Model accuracy of inverter driving load capacitance ......................................57 4.3.1 Model accuracy in AMI CMOS 0.5μm process .....................................58 4.3.2 Model accuracy in TSMC CMOS 0.18μm process ................................60 4.4 Model accuracy of inverter driving inverter gate load.....................................62 4.4.1 Model accuracy in AMI CMOS 0.5μm process .....................................62 4.4.2 Model accuracy in TSMC CMOS 0.18μm process ................................63 4.5 Summary..........................................................................................................64 5. COMPLEX GATES ANALYSIS WITH A PIECEWISE LINEAR MODEL.....66 5.0 Introduction......................................................................................................66 5.1 Average power analysis of twoinput NAND gate ..........................................66 5.1.1 Twoinput NAND gate driving capacitance load ...................................67 5.1.2 Model accuracy in NAND gate in AMI 0.5μm process .........................68 5.1.3 Model accuracy in NAND gate in TSMC 0.18μm process ....................70 5.2 Average power analysis of OAI gate ...............................................................73 5.2.1 Average power analysis of OAI gate driving capacitance load..............74 5.2.1.1 Accuracy of model in OAI gate in AMI 0.5μm process...................74 5.2.1.2 Model accuracy in OAI gate in TSMC 0.18μm process...................76 5.2.2 Average power analysis of OAI gate driving an inverter load ...............78 5.2.2.1 Model accuracy in OAI gate in AMI 0.5μm process........................79 5.2.2.2 Model accuracy in OAI gate in TSMC 0.18μm process...................81 6. CONCLUSION....................................................................................................82 BIBLIOGRAPHY........................................................................................................86 vi APPENDICES APPENDIX Page A Average power simulation in the SPICE SPECTRE ..............................................91 B Model parameter extractions for AMI 0.5μm and TSMC 0.18μm Process………. .......................................................................................................96 C Coding and implementation ..................................................................................106 vii LIST OF TABLES TABLE Page 1 Linearized parasitic transistor capacitance with overlap capacitance.................29 2 Average power simulation of inverter in Fig.4.5 using PWL model for various input transition time from 1000ps to 20ps ..........................................................56 3 Comparisons of average power predictions in SPICE and PWL model with various input slopes from 1000ps to 90ps...........................................................57 B.1 Falling input PMOS parameters for AMI 0.5μm process ...............................99 B.2 Rising input PMOS parameters for AMI 0.5μm process ................................99 B.3 Falling input NMOS parameters for AMI 0.5μm process ............................100 B.4 Rising input NMOS parameters for AMI 0.5μm process. ............................100 B.5 Falling input PMOS parameters for TSMC 0.18μm process ........................101 B.6 Rising input PMOS parameters for TSMC 0.18μm process.........................101 B.7 Falling input NMOS parameters for TSMC 0.18μm process .......................102 B.8 Rising input NMOS parameters for TSMC 0.18μm process ........................102 viii LIST OF FIGURES FIGURES Page 1.1 CMOS inverter.........................................................................................................4 1.2 CMOS two input NAND gate..................................................................................4 1.3 CMOS OAI gate ......................................................................................................5 2.1 Four terminal MOSFET device and its parasitic capacitances ................................8 2.2 Offstate currents from the transistor gate to its conducting channel. .....................9 2.3 Veendrick’s shortcircuit current model of an inverter without load. ...................13 3.1 Average power measurement from the power supply current ...............................20 3.2 Transistor switchlevel models in ohmic, saturation, and cutoff region................21 3.3 Accuracy of the PWL switching current model for 2.4μm/0.6μm nFET. .............23 3.4 Accuracy of the PWL switching current model for 4.8um/0.6um pFET...............23 3.5 Sign convention for zeroorder piecewise linear switching current ......................24 3.6 Channel storage charge model ...............................................................................25 3.7 Sign convention for channel capacitive currents in transistors..............................26 3.8 Gate overlap capacitances for FETs ......................................................................30 3.9 Input ramp approximation......................................................................................31 3.10 Piecewise linear approximation of input ramps in resistance connected region .32 3.11 Notation of transistor number ‘m’ and circuit node names .................................34 4.1 Inverter driving load capacitance with rising input ramp approximation..............50 4.2 Inverter transient analysis with boundaries and operation regions with rising input ramp approximation....................................................................51 4.3 Inverter driving load capacitance with falling input ramp approximation ............53 4.4 Inverter transient analysis with boundaries and operation regions with falling input ramp approximation ..................................................................53 4.5 Average power calculation by the model for TSMC 0.18μm process...................56 4.6 Accuracy of the PWL model in inverter (K = 4, 0.5μm) driving 100fF load........59 4.7 Accuracy of the PWL model in inverter (K = 2, 0.5μm) driving 100fF load........59 4.8 Accuracy of the PWL model in inverter (K = 1, 0.5μm) driving 100fF load........60 4.9 Accuracy of the PWL model in inverter (K = 4, 0.18μm) driving 100fF load......60 4.10 Accuracy of the PWL model in inverter (K = 2, 0.18μm) driving 100fF load ....61 4.11 Inverter driving gate load capacitance .................................................................62 4.12 Accuracy of the PWL model in inverter (K = 2, 0.5μm) driving inverter load ...62 4.13 Accuracy of the PWL model in inverter (K = 1, 0.5μm) driving inverter load ...63 ix 4.14 Accuracy of the PWL model in inverter (K = 4, 0.18μm) driving inverter load .63 4.15 Accuracy of the PWL model in inverter (K = 2, 0.18μm) driving inverter load .64 4.16 Accuracy of the PWL model in inverter (K = 1, 0.18μm) driving inverter load .64 5.1 Twoinput NAND driving load capacitance .........................................................67 5.2 Accuracy of the PWL model in twoinput NAND gate (K = 4, 0.5μm) driving 100fF load ..............................................................................................................68 5.3 Accuracy of the PWL model in twoinput NAND gate (K = 2, 0.5μm) driving 100fF load ..............................................................................................................69 5.4 Accuracy of the PWL model in twoinput NAND gate (K = 2, 0.5μm) driving inverter gate load....................................................................................................69 5.5 Accuracy of the PWL model in twoinput NAND gate (K = 1, 0.5μm) driving inverter gate load....................................................................................................70 5.6 Accuracy of the PWL model in twoinput NAND gate (K = 4, 0.18μm) driving 100fF load ..............................................................................................................70 5.7 Accuracy of the PWL model in twoinput NAND gate (K = 2, 0.18μm) driving 100fF load ..............................................................................................................71 5.8 Accuracy of the PWL model in twoinput NAND gate (K = 1, 0.18μm) driving 100fF load ..............................................................................................................71 5.9 Accuracy of the PWL model in twoinput NAND gates (K = 4, 0.18μm) driving inverter gate load....................................................................................................72 5.10 Accuracy of PWL model for a twoinput NAND gate (K = 2, 0.18μm) driving inverter gate load..................................................................................................72 5.11 Accuracy of the PWL model in twoinput NAND gate (K = 1, 0.18μm) driving inverter gate load..................................................................................................73 5.12 OAI Gates driving a 100fF Load .........................................................................74 5.13 Accuracy of the PWL model in OAI gate (K = 4, 0.5μm) driving 100fF load....75 5.14 Accuracy of the PWL model in OAI gate (K = 2, 0.5μm) driving 100fF load....75 5.15 Accuracy of the PWL model in OAI gate (K = 1, 0.5μm) driving 100fF load....76 5.16 Accuracy of the PWL model in OAI gate (K = 1, 0.18μm) driving 100fF load..77 5.17 Accuracy of the PWL model in OAI gate (K = 2, 0.18μm) driving100fF load...77 5.18 Accuracy of the PWL model in OAI gate (K = 1, 0.18μm) driving100fF load...78 5.19 OAI gate driving different inverter gate loads.....................................................79 5.20 Accuracy of the PWL model in OAI gate (K = 4, 0.5μm) driving inverter.........79 5.21 Accuracy of the PWL model in OAI gate (K = 2, 0.5μm) driving inverter.........80 5.22 Accuracy of the PWL model in OAI gate (K = 1, 0.5μm) driving inverter.........80 5.23 Accuracy of the PWL model in OAI gate (K = 4, 0.18μm) driving inverter.......81 5.24 Accuracy of the PWL model in OAI gate (K = 2, 0.18μm) driving inverter ......81 A.1 Average power simulation of inverter in SPICE ..................................................92 A.2 SPICE power waveform/cycle with 1ns input slope: dot in red: total device power; solid green line: supply power dashdot in blue: supply current. ...........93 A.3 Average power simulation in power supply in SPECTRE ...................................94 A.4 Average device power simulation in SPECTRE...................................................95 B.1 Threshold voltage extraction from high VDSN curves in 0.5μm process ...............97 x B.2 Threshold voltage extraction from low VDSN curves in 0.5μm process ................97 B.3 Transistor diffusion capacitance model...............................................................103 B.4 Source junction capacitance versus body bias ....................................................104 xi LIST OF PHYSICAL CONSTANTS AND PROCESS PARAMETERS ε0 = 8.85 10 14 Fm × − ox ε = 3.97 for silicon dioxide k = 0 1.3803 10 23 Joule K × − kT = 4.1409 × 10−21 Joule for room temp. at 270 q = 1.6 × 10−19 Coulomb Cox = ox 0 tox ε ⋅ε = 11 ox 3.51 10 Fm (for the gate oxide on silicon) t (m) × − n β = μn ⋅Cox p β = μp ⋅Cox xii LIST OF SYMBOLS Symbol Meaning Unit an Ratio of conductance and transconductance for the nMOS transistor ap Ratio of conductance and transconductance for the pMOS transistor β Effective transistor strength A.V2 C Capacitance matrix F Cd Depletion layer capacitance F GG C Linearized parasitic capacitance on the gate of the transistor F GS C Linearized parasitic capacitance on the gatesource of the transistor F Cgdo Voltage independent gatedrain overlap capacitance per unit gate width F.m1 Cgso Voltage independent gatesource overlap capacitance per unit gate width F.m1 OX C Oxide capacitance per unit area F.m2 EIvdd Energy dissipation due to the shortcircuit current and dynamic current J Eivdd Energy dissipation due to the firstorder channel capacitive currents J Gm Conductance of the mth transistor S G Conductance matrix S E T Energy dissipation per switching cycle J/S 0 ε Permittivity of vacuum F.m1 ox ε Relative permittivity of oxide Ivdd Zeroorder power supply current in the piecewise linear transistor model A ivdd Firstorder power supply current in the piecewise linear transistor model A ISm Zeroorder piecewise linear switching source current of the mth transistor A iSm Firstorder piecewise linear switching source current of the mth transistor A IDm Zeroorder piecewise linear switching drain current of the mth transistor A iDm Firstorder piecewise linear switching drain current of the mth transistor A ISC Shortcircuit current A xiii k Boltzman’s constant J.K1 τ Delay time second or s r τ Delay time for rising signal second or s f τ Delay time for falling signal second or s n μ Channel electron mobility m2 V1 s1 P μ Channel hole mobility m2 V1 s1 Pavg Average power dissipation W Pdynamic Dynamic power dissipation W PSC Short circuit power dissipation W POFF Offstate leakage power dissipation W T I Zeroorder quasistatic current in the transistor channel A iT Firstorder quasistatic current in the transistor channel A DS V sat Drainsource saturation voltage of the transistor V T V Transistor threshold voltage V V% Approximated output voltage in the steady state V V&% Firstorder terms for the approximated output voltage V V&%& Secondorder terms for the approximated output voltage V V Output voltage of the resistive connected node V S Subthreshold slope mV/decade TTin Input transition time s tox Gate oxide thickness m xPart Parameter for the channel charge partition φB Builtin potential of the bottom wall junction capacitance V φBSW Builtin potential of the isolation side sidewall junction capacitance V φBSWG Builtin potential of the gate side sidewall junction capacitance V 1 CHAPTER 1 INTRODUCTION 1.0 Purpose of the Study Power dissipation is one of the major concerns for high speed very large scale integrated circuits (VLSI) design. Power dissipative components in CMOS circuits consist of offstate leakage power, glitch power, and switching transient power. This paper presents a piecewise linear modeling of switching transient power of CMOS digital circuits, which includes the shortcircuit power, dynamic power, and switching power of parasitic capacitors. The piecewise linear power model takes a simplified approach to compute average power (or energy per cycle) without solving differential equations with large matrices. Even thought SPICE (Stanford Program for Integrated Circuit Emulation) can handle the accurate and nonlinear behaviors of transistors with more than one hundred fitting parameters, it usually takes a great amount of computation time for a large circuit simulation. Another competing circuit simulator is the switch level simulator, IRSIM, which is a tool for simulating digital circuits. It is a switchlevel simulator, because the transistors are treated as ideal switches, and the extracted capacitances and resistances are used to find the RC time constants for the ideal switches 2 to predict the relative timing events [34]. Thus, it is an ideal transistor model, and is not accurate in computing transient switching power. The proposed piecewise linear model, as an improved switch resistor model, closes the performance gap between SPICE and switchlevel simulators in power estimation. 1.1 Significance of the Study Dynamic power dissipation is well known and defined for CMOS digital circuits. Analytical works, more recently, for power modeling are focused on shortcircuit power modeling with slope effects, velocity saturation and gatetodrain capacitive coupling effects, propagation delay and short channel effects. Analytical works in offstate leakage power modeling are also popular as the transistor size shrinks into the deep submicron realm. However, channel capacitive currents induced power dissipation is not addressed in other transistor models [4] [6] [7] [13]. Therefore, the proposed piecewise linear model not only includes the firstorder capacitive currents but also takes into account the effect of the slope of the input waveform in average power estimation. Most fast simulators [34] [39] assume a step input, so that the piecewise linear model is at least an improved yet simplified nonlinear transistor model to replace the traditional resistor model in fast simulators. The piecewise linear model is verified in the submicron AMI CMOS 0.5μm and deep submicron TSMC 0.18μm process. 3 1.2 Limitation of the Piecewise Linear Model The model is constructed with IV and CV models approximating the complex BSIM (Berkeley ShortChannel Insulated gate field effect transistor Model) model [4] for CMOS transistors as switches. The current–voltage (I–V) model describes the zero–order (dc) behavior of a quasistatic current between the source and drain terminals, and the capacitance–voltage (C–V) model describes the firstorder dynamic behavior of channel capacitive currents associated with transistor parasitic capacitances. The piecewise linear I–V model approximates the physical transistor current with different piecewise linear regions in cutoff, ohmic, and saturation. The proposed model shows that its accuracy is within 3 to 5 % of SPICE for fast inputs in AMI 0.5μm and TSMC 0.18μm processes, and the accuracy may reach 15 to 20 % error for input transition times greater than 2000 picosecond in AMI 0.5μm process and 1000 picosecond in TSMC 0.18μm process. However, very slow input occurs not very often in submicron technologies and can usually be speeded up with circuit design techniques. 1.3 Introduction to the CMOS logic families 1) Standard CMOS logic gates A standard CMOS logic gate has the same number of pFETs and nFETs with the transistors connected in a complementary manner. A standard CMOS inverter, NAND, and NOR may be designed with different sizes to meet speed and power requirements. Most power dissipation of CMOS circuits comes from the switching transient power, which includes the shortcircuit power, and dynamic power. A piecewise linear model to calculate the average power dissipation of a CMOS inverter (Fig.1.1), a twoinput NAND 4 gate (Fig.1.2), and a threeinput OAI (OrAndInvert) digital circuit (Fig.1.3) driving a constant capacitor or driving various sizes of inverter loads, are chosen to compare modeling accuracy with the average power of the power supply as predicted by SPICE. Figure 1.1 CMOS inverter Figure 1.2 CMOS two input NAND gate 5 Figure 1.3 CMOS OAI gate 1.4 Organization In chapter two, conventional power models are introduced along with literature reviews of offstate leakage power, short circuit power, glitch power, and dynamic power models. In chapter three, the piecewise linear switching current–voltage (IV) model and channel storage charge or channel capacitance–voltage (CV) model are introduced. IV and CV models in the piecewise linear model are used to demonstrate the model in computing average power from the power supply currents. In chapter four, computing average power with the piecewise linear model is coded in C++ language for an inverter. In chapter five, more complex circuits are chosen. Average power evaluations for twoinput NAND and OrAndInverter (OAI) with various transistor sizes and loads are presented. Findings and conclusion are presented in chapter six. 6 CHAPTER 2 CONVENTIONAL TRANSISTOR MODELS FOR POWER ESTIMATION 2.0 Definitions: Energy or Power The use of power as a performance measure is often misleading. In battery operated devices, the amount of energy needed for operations may be a more useful measure because a battery stores a finite amount of energy, not power [35]. Energy per operation or average power is often used to evaluate energy efficiency of CMOS circuits. Definition of instantaneous power and average power (or energy per cycle), is summarized as follows. The instantaneous power P(t) is proportional to the power supply current Ivdd(t) and the supply voltage [8], which is written as P(t) = Ivdd (t) ⋅Vdd (2.1) The average power dissipation Pavg is defined as an integration of instantaneous power P(t) over some time interval T. Also, the average power dissipation is equivalent to the energy consumed over some interval T [8] and is written as T dd 0 P 1 I ( t ) V d t E avg T vd d T = ∫ ⋅ = (2.2) Energy ‘E’ is calculated from the integration of instantaneous power supply current during the period when the instantaneous power supply current enters the circuit [8]. 7 2.1 Sources of CMOS Power Dissipation Transistor dissipative power is mainly due to the currents from the channel inversion layer traveling in a resistive channel between source and drain terminals. Unfortunately, the power supply current into the transistor channel is a nonlinear function of terminal voltages. Transistor channel currents are, in fact, spaceaveraged quasistatic currents in the channel [6], which includes the voltagedependent quasistatic current component and a timevarying charging current component [25]. Conventional transistor models [25] show that quasistatic currents in the channel consist of the following components. IT = hT (VD,VG ,VB,VS) (2.3) iT (t) = hT (vD(t), vG (t),vB(t), vS (t)) (2.4) The channel current IT expressed in (2.3) is a function of the terminal voltage on the gate, source, drain, and substrate of the transistor [25] without timevarying voltages. Thus, the expression for IT is, in fact, a zeroorder quasistatic DC model. Channel capacitive currents which are equivalent to “charging currents” [25] in (2.4) are function of the time derivatives of the channel charge storage, which depends on the timevarying voltages associated with each terminal [25] [33], therefore, it is the firstorder quasistatic capacitive currents associated with voltagedependent parasitic capacitances. Figure 2.1 illustrates the FET device with parasitic capacitances. Five distinct types of transistor current contribute to the power dissipation of a CMOS circuit. 8 Figure 2.1 Four terminal MOSFET device and its parasitic capacitances I. Transistor offstate subthreshold leakage currents II. Switching transient currents, which include 1) Load capacitor charge and discharge through pFET and nFET network. 2) Shortcircuit current conduction between the power and ground nodes through both FET’s simultaneously. III. Channel capacitive currents due to switching transistors IV. Glitch currents due to unequal arrival of signals to the circuit. 2.1.1 OffState Leakage Power of the Transistor For CMOS logic families and memory circuits, the performance factors include the ratio of offstate leakage current (subthreshold conduction current) to turnon current (IOFF / ION), power, delay, and reliability [15]. Leakage current comes from gate, source, and drain terminals. Gate leakage occurs due to the scaling of gate oxide thickness and the resulting tunneling current from the gate to channel in the transistor as illustrated in Figure 2.2. A study [15] has shown that the gate oxide thickness TOX can be thinned down to 2nm before the leakage current becomes unacceptable for CMOS circuits. 9 Figure 2.2 Offstate currents from the transistor gate to its conducting channel The other concern for scaling oxide thickness thinner than 2 nm is that threshold voltage VT can not be scaled down proportionally with the channel length. The primary barrier is a leakage current dependent subthreshold slope, S, which is a measure of transistor turnoff rate from the gate voltage versus subthreshold leakage current. S should be small in order to reduce leakage current. The subthreshold slope is written as 1 D DS G OXIDE d ln10(kT) C S ( (log I )) (1 ) dV q C ≅ ⋅ − = + (2.5) where q denotes the electron charge, k = 1.38•1023 (J/K) Boltzmanns constant, T the absolute temperature in Kelvin, CD the incremental capacitance of the depletion layer per unit area, and COXIDE is the capacitance of the gate oxide per unit area. The depletion capacitance is a nonlinear function of the gate to bulk voltage. When VGB increases, the value of CD/COXIDE may become negligible. In other words, the subthreshold slope is largely driven by thermally excited electrons in the channel and has no physical controllability from the manufacturing process. Even though CMOS scaling causes offstate power to increase, a study has shown that the offstate power is 0.01% of active power dissipation in a 1um process while 10% in a 0.1um process [15]. Although offstate power is not included in the piecewise linear approximation in this research, the simple offstate transistor power from equation (2.6) [15] can be approximated with the 10 currents of the transistors connected to the power supply for each piecewise linear region of operation, where WTOTAL is the total turnedoff transistors width with VDD across them, and I0 is the parameter for offstate current per device width, and VT is the worse case threshold voltage. OFF TOTAL DD 0 qV P W V I exp( T ) kT − ≅ ⋅ ⋅ ⋅ (2.6) 2.1.2 Switching Transient Power in CMOS Transistors There are two components to the switching transient power: dynamic power dissipation and shortcircuit power dissipation [8] [28], and the models are reviewed as follows. 1. Dynamic Power Dissipation in CMOS Transistors Dynamic switching power occurs when the pFETs connected to the power supply turns on and a direct current path is established from the power supply to load capacitances. For standard CMOS circuits, the dynamic current consumption is dominated by the power supply current necessary to charge up node capacitances, and the dynamic power consumption Pdynamic is proportional to the power supply current and the square of the supply voltage [8]. Pdynamic is expressed as (2.7) [28]. SW SW SW SW T dynamic vdd sw 0 T 2 T Dp DSp Dn DSn sw 0 sw T 2 P 1 i (t)v(t)dt T 1 I V dt 1 I V dt T T = = + ∫ ∫ ∫ (2.7) 11 where out Dp load dV I C dt = − (2.8) VDSp = −(Vdd − Vout ) (2.9) out Dn load dV I C dt = − (2.10) VDS n = Vo u t (2.11) Therefore, average dynamic power is the sum of power computed from the power supply current charging the load capacitance by the pullup pFET network and discharging the same current by the pulldown nFET network for the second half of cycle. Such that, SW SW SW dd dd T 2 T out out dynamic load dd out load sw 0 sw T 2 V 0 load dd out out load out out sw 0 sw V load 2 dd sw 1 dV 1 dV P C (V V )dt C dt T dt T dt 1 C (V V )dV 1 C V dV T T C V T = − + − = − + − = ∫ ∫ ∫ ∫ (2.12) For a general circuit topology with transistors and capacitors only, total dynamic power dissipation is often computed for switching of all of the nodes according to the switching activity (αi ) at the ith capacitive node within a circuit, such that 1 0 N t t 2 dynamic i i i i sw i 1 P 1 C (V V ) T = = Σα ⋅ ⋅ − (2.13) Dynamic power dissipation assumes that t0 Vi , Vit1 are full swing signal between ground and Vdd during a complete chargedischarge cycle. Since most gates do not switch every 12 clock cycle, it is convenient to write the switching frequency as switching activity factor times the clock frequency fsw [8]. N N 2 2 dynamic dd i i sw dd i i sw i 1 i 1 P 1 V C f V C T = = = ⋅ ⋅Σ ⋅α = ⋅ ⋅Σ ⋅α (2.14) 2. Short Circuit Power Dissipation in CMOS Transistors Shortcircuit power is usually neglected in power calculations by switchlevel simulators [34] [39], which often assume a step input response for fast simulation. Due to the intrinsic resistance and parasitic capacitances in a transistor channel, any transistor circuit takes a finite time to rise or fall to its final value at any given node. Therefore, real circuits are usually driven by input with a finite transition time, and consequently, shortcircuit power can be as significant as the dynamic power [17] and cannot be neglected in power calculation. The short circuit power dissipation component is proportional to the input transition time and the load capacitance when a direct current path is established between the power supply and ground. Evaluation of the short circuit power component requires information about input transition times (input rise and fall times), transistor sizes, and the load driven by the circuit. There are many analytical evaluations of the shortcircuit power dissipation component for a simple inverter gate [17], [18], [19], and [20]. The first closedform expression for the shortcircuit power component for a CMOS inverter without load capacitor was from Veendrick in 1984 [17] [23]. The shortcircuit power expression Veendrick derived assumed that the shortcircuit current was symmetric for each input transition with a matched transistor’s mobility and threshold voltage, with equal input rise and fall time τ in a periodic signal T as shown in Fig. 2.4. 13 Figure 2.3 Veendrick’s shortcircuit current model of an inverter without load Under Veendrick’s assumption, shortcircuit current component in an inverter was approximated by transistors in the saturation, such that 2 I (VIN VT ) 2 β = − 0 ≤ I ≤ ISC MAX (2.15) Since the inverter is symmetric about t2, ISC MAX occurs at half of the supply voltage. The mean short circuit current is determined by integrating the instantaneous current from 0 to time T and divided by T. 2 T is the average number of transition per second. T 2 MEAN 0 DD 2 DD T t2 IN T t1 t2 T t1 I 1 I(t)dt 2 2 1 (V (t) V ) dt T T 2 2 2 (V t V ) d(V t V ) T 2 = = β − β = − − τ τ ∫ ∫ ∫ DD T DD 1 (V 2V )3 12 V T β τ = − ⋅ (2.16) where β = βP = β N 14 τr = τf = τ VTn = −  VTp  = VT DD IN T 1 DD 2 V (t) V t t V V t 2 = τ = ⋅τ τ = Therefore, following is the shortcircuit power of a CMOS inverter with no load capacitance: SC DD T P (V 2 V )3 12 T β τ = − ⋅ ⋅ (2.17) The short circuit power expression (2.17) was solved as a function of the input rising and falling transition time (τ) without a load capacitance, and the result may lead to a pessimistic prediction of the shortcircuit power dissipation, because Veendrick’s short circuit power model assumed transistors operated in saturation region only, which cannot accurately predict shortcircuit current as transistors in ohmic region. However, formula (2.17) clearly illustrates that the shortcircuit power is proportional to design parameters β and input transition times (τ) of an inverter’s input signal. For an inverter with a load capacitance, the transistor β values are determined by the required output rise and fall times [8]. Therefore, dependency of shortcircuit power on the input rise and fall times is still valid when an inverter drives a load capacitance. More recently (1996), a closed form expression presented by Bisdounis et al. for shortcircuit power dissipation was based on an output waveform expression with a squarelaw current transistor model [17]. Instead of using a squarelaw current model, Sakurai and Newton [22] suggested an αpower 15 model for the evaluation of shortcircuit power dissipation component. Afterward, Vemuru and Scheinberg [23] developed a shortcircuit power equation by adopting Sakurai and Newton’s αpower MOS model. αpower model and the square law model were proved to be fairly accurate power models, but implementing the higherorder current model takes a fairly large computation time. Hirata, A., et al., [24] reported a piecewise linear function for the shortcircuit power dissipation component in an inverter, but the model can not be extended to predict shortcircuit power for other circuit topologies. 2.1.3 Glitch Power Dissipation in CMOS Transistors It is well known that dynamic power dissipation is directly related to the number of signal transitions in full swing, but spurious transitions (or glitches) caused by unequal arrivals of propagation delays of input signals to the gate often occur in many static ICs [42]. Glitch power is often modeled by using the dynamic power dissipation model as equation (2.13) where t1 t0 (Vi − Vi ) is the incomplete transition during a complete chargedischarge cycle [40] [41] [42]. Power estimation tools can simulate glitches at the gate level for medium size circuits, but the accuracy of glitch power predictions for large circuits is inadequate [42]. 2.2 Summary Modeling average power dissipation in CMOS circuits, at least, should include the following components for CMOS technologies. 16 I. Shortcircuit power. II. Dynamic power. III. Switching power of parasitic capacitances. Not all transistor models are capable of computing each power dissipation component. For instance, the switchresistor model in IRSIM [13] [39] simulator can evaluate dynamic power dissipation only. Surprisingly, the HSPICE simulator, one of the most accurate SPICE circuit simulators, does not include the power dissipation caused by nonlinear parasitic capacitors [3]. Many researchers [19] [20] [22] [23] [24] [31] extend the αpower model to compute shortcircuit power dissipation component, but none of the models has addressed the significance of channel capacitive currents in a power evaluation. Besides, the αpower model usually has a noninteger value for α, which is not efficient enough to be implemented in a fast simulator. The main difference of the proposed piecewise linear model from previous models in the literature is to compute the average power supply current provided to the circuit instead of evaluating individual power dissipative components for each transistor. In order to compute average power from the power supply current, including channel capacitive currents for a fast simulator, an efficient yet simple transistor model is essential. A simplified (piecewise linear) zeroorder quasistatic switching current model and channel storage charge model are developed to serve the goal and are presented in the following chapter. 17 CHAPTER 3 A PIECEWISE LINEAR TRANSISTOR MODEL 3.0 Background The circuit simulator, SPICE, was designed primarily to evaluate circuit performance during the explosive growth of integrated circuits in the late 1960’s and early 1970’s [38]. A fast simulator, RSIM, was built in the late 1980’s and early 1990’ became competitive with SPICE for its efficiency but not accuracy in simulating large integrated circuits [39]. The RSIM is a switchlevel simulator with speedups of over three orders of magnitude over SPICE [13] [39]. Unfortunately, the switchedresistor model used by RSIM renders it incapable of simulating certain CMOS digital circuits [39] and does not compute power dissipation components other than dynamic power [34]. More recently, a piecewise linear gate modeling of CMOS circuits [36] has improved the switchedresistor model by incorporating a piecewise linear saturation current model and the effects of shortcircuit current and channel capacitive currents into gate delay modeling. Also, the model with a fast algorithm for circuit dynamic analysis can predict gate delay within 10% average error of SPICE regardless of circuit topologies [36]. The goal of this research is to extend the same piecewise linear model to compute average power dissipation in CMOS circuits by evaluating average power supply current. The piecewise linear switching current model and part of the circuit dynamic analysis [36] are reviewed in the following section as an essential step to power estimation. 18 3.1 Evaluation of Average Power Dissipation with the Piecewise Linear Model Rather than attempting to evaluate instantaneous power from each transistor device for each power dissipation component described at the end of chapter two, the proposed piecewise linear model evaluates average power by evaluating average power supply current from transistor(s) connected to the power supply. With the zeroorder switching currentvoltage (IV) model and the channel charge storage or capacitancevoltage (CV) model introduced in the following section, the average power from the power supply current is evaluated instead of evaluating each transistor with instantaneous current and voltage as functions of time. During switching transients that turn off transistors connected to the power supply, only shortcircuit current is included in Ivdd(t) calculation because the discharging current for the node capacitance flows through the turnon nFET network. In contrast, the sum of the dynamic current and the shortcircuit current is included in Ivdd(t) calculation when the transistors connected to the power supply turn on, because the charging current from the power supply for the node capacitance flows through the turnedon pFET network and the shortcircuit current from the turningoff nFET network flows simultaneously. The switching power of any implicit parasitic capacitance is estimated from ivdd(t) with the channel storage charge (CV) model. The power supply current is, in fact, the sum of the currents of every transistor and any explicit capacitance that is directly connected to the power supply. The instantaneous power, P(t) , in (2.1) is rewritten as (3.1) for the average power evaluation from the piecewise linear model (3.2). P(t) = ⎡⎣Ivdd (t) + ivdd (t)⎤⎦ ⋅Vdd (3.1) 19 T 0 P 1 I ( t ) i ( t ) d t E avg T vd d vd d T = ∫ ⎡⎣ + ⎤⎦ = (3.2) The notation Ivdd is used to indicate the power supply current which contributes power dissipation due to the shortcircuit current and dynamic current in CMOS circuits [10]. ivdd will be used to indicate the power supply current which comes from the firstorder switching power due to any implicit parasitic capacitance from transistors connected to the power supply. Ivdd (t) is evaluated by the model from the sum of each individual transistor source current Sm I , which represents the shortcircuit current (or turnoff current) during input (0→1) transitions and also represents the power supply current required to charge the node capacitance (or turnon current). Whereas ivdd(t) is estimated from the sum of the individual channel capacitive currents, Sm i , of each switching transistor connected to the power supply. The subscript stands for the source terminal of mth transistor(s) connected to the power supply. The turnoff current and turnon current will be used throughout the paper when the average power supply current is approximated with the piecewise linear model in each switching cycle. The method of computing average power dissipation can be extended for any multistage circuit that is partitioned into individual subcircuit as shown in Figure 3.1. 20 Figure 3.1 Evaluation of average power from the power supply current 3.1.1 Piecewise Linear Switching Current Model The piecewise linear model for transistor switching is a voltage controlled switch with a series resistance. The simple linear model simplifies the circuit dynamics once the switches have reached their final states. Although the switched resistor model [13] has been used very successfully in circuit simulation [39], it is not adequate to describe the finite time required to switch the transistors on to off. Also, the saturation behavior of the transistors has a significant impact on the switching waveform and average power evaluation. Unfortunately, there is no linear model that can include cutoff, ohmic, and saturation behaviors simultaneously. Complex transistor behavior is simplified to three piecewise linear regions of operation as shown in Figure 3.2. The piecewise linear model is as follows. 21 Figure 3.2 Transistor switch models in ohmic, saturation, and cutoff region respectively The zeroorder quasistatic switching current denoted as IDm and ISm (Fig. 3.2) for the drain and source terminal of the mth transistor connected to the power supply and has the following properties. IDm = −ISm (3.3) IGm = IBm = 0 (3.4) Equations (3.4) assumes that there is no leakage current flowing through the substrate and gate. Therefore, zeroorder quasistatic switching current has the following definitions in the cutoff, ohmic and saturation region for the nFET and pFET transistor in (3.5) and (3.6). m m Dm GSN Tn GSN Tn Dm DSN GSN Tn DSN DSsatn DS Dm GSN Tn GSN Tn DSN DSsatn I (off ) 0, V V (a G V ) , V V ,V V V V I (ohmic) n ,V satn a n I (sat) [G (V V )] ,V V ,V V ⎛ ⎞ ⎛ < ⎞ ⎜ ⎟ ⎜ ⎟ − ⎜ ⎟ = ⎜ ⋅ ⋅ > < ⎟ = ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ⋅ − > > ⎠ ⎝ ⎠ (3.5) 22 m m Dm GSP Tp GSP Tp Dm DSP GSP Tp DSP DS DS Dm GSP Tp GSP Tp DSP DS I (off ) 0, V V (a G V ) , V V ,V V V V I (ohmic) p satp ,V satp ap I (sat) [G (V V )] ,V V ,V V satp ⎛ ⎞ ⎛ > ⎞ ⎜ ⎟ ⎜ ⎟ − ⎜ ⎟ = ⎜ ⋅ ⋅ < > ⎟ = ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⋅ − < < ⎟ ⎝ ⎠⎝ ⎠ (3.6) Gnohmic a n GnSat a p Gpohmic GpSat ⎛ ⎞ ⎜ ⎟ ⎛ ⎞ ⎜ ⎟ ⎜ ⎟ = ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ (3.7) (aP ⋅G)m is the conductance of the mth pFET transistor in the ohmic region and the Gm is the transconductance of the mth transistor in the saturation region. The sign of transistor current at the drain given by (3.5) and (3.6) is determined by the terminal voltages of the transistor. Current going into a terminal indicates a positive drain current and negative current if the current exits from the terminal. an , ap,VTn , and VTp are process constants and process dependent variables. All parameters are positive except the threshold voltage VTp . an , ap are greater than one. Conductance of the pFET and nFET transistor for Gohmic and Gsat are determined from average sheet resistance extrapolated from I/V curves from the transistors used in the test circuits. The piecewise linear model is a reasonably good approximation to current in saturation, and less accurate for current in the ohmic region as shown in Fig 3.3 and 3.4 when comparing the piecewise linear switching currents with SPICE simulation. However, as illustrated in [39], modeling errors in regions of low drain current usually produce smaller timing errors than errors in regions of high drain current. Therefore, the current mismatch errors in regions of low drain current is not critical for the timing accuracy of the piecewise linear transistor model. Furthermore, additional accuracy for the low drain current can be obtained by adding more piecewise linear regions to better approximate the transistor current in the 23 ohmic region, but adding more regions to the model makes solving for circuit dynamics more timeconsuming because the node voltage must be checked at each moment in time to decide which piecewise linear model to use for each transistor in a circuit. The piecewise model is at least a more accurate switching current model than the traditional switched resistor model [13]. Figure 3.3 Accuracy of the piecewise linear switching current model for 2.4μm/0.6μm nFET Figure 3.4 Accuracy of the piecewise linear switching current model for 4.8μm/0.6μm pFET 24 As illustrated in Figure 3.1, the averaged power dissipation is computed from the sum of the switching current of every pFET connected to the power supply. Figure 3.5 illustrates the sign convention for the zeroorder quasistatic switching current component into the transistors. The firstorder channel capacitive currents into the transistor(s) connected to the power supply are evaluated separately by the channel storage charge model presented in the following section. Figure 3.5 Sign convention for zeroorder switching in transistors 3.1.2 Channel Storage Charge Model Besides the zeroorder quasistatic switching current in the transistor channel, channel currents also contain a firstorder channel capacitive current, which come from the channel charge stored in the nonlinear parasitic capacitances. Channel capacitive currents are denoted as iD, iS, iG, and iB in order to differentiate from the zeroorder quasistatic switching current for ID, IS, IG, and IB. Most transistor models [4] [5] [7] [26] are 25 not energy conserving due to the neglect of the firstorder channel capacitive currents when calculating power consumption [37], and therefore, parasitic capacitances of the transistor are treated as normal capacitors, which do not dissipate power. Particularly, a SPICE simulator assumes that parasitic capacitors are normal capacitors in nature and do not include them in a power calculation [3]. In order to correct the problem by including the nonlinear channel capacitive currents in a power calculation, the channel storage charge is partitioned as seen in Figure 3.6 between the source and drain to obtain a simple lumped parameter model for the dynamic behavior of the transistor. Charge conservation requires that the total channel charge to be conserved, such that Figure 3.6 Channel storage charge model QG = −(QS + QD + QB) (3.8) It should be emphasized that these are not linear capacitances since the charges are functions of all of the transistor terminal voltages. Channel capacitive currents can be written in terms of time derivatives of the channel storage charge on each transistor terminal. It is convenient to use these equations written in terms of the individual terminal voltages G V , S V , D V , and B V . G G S D B G GG GS GD GB i dQ C dV C dV C dV C dV dt dt dt dt dt = = − − − (3.9) S G S D B S SG SS SD SB i dQ C dV C dV C dV C dV dt dt dt dt dt = =− + − − (3.10) 26 dQD dVG dVS dVD dVB iD CDG CDS CDD CDB dt dt dt dt dt = =− − + − (3.11) iB = −(iG + iS + iD ) (3.12) Cij (i ≠ j) are all nonlinear capacitors and functions of the terminal voltages given by i ij ij C Q i, j G,D,S,B V ∂ = = ∂ (3.13) where CGG = CGS + CGD + CGB (3.14) CSS = CSG + CSD + CSB (3.15) CDD = CDG + CDS + CDB (3.16) The sign convention used for the firstorder channel capacitive current (3.10) into the source terminal of transistor(s) connected to the power supply is shown in Figure 3.7. Figure 3.7 Sign convention for channel capacitive currents in transistors 27 In digital applications, the substrate terminal is biased at a constant voltage so that the last column in equations (3.9)(3.11) can be ignored. Integration of the channel capacitive current equations gives the channel charge expressions (3.17)(3.19), which make the evaluation of channel storage charge convenient for piecewise linear approximations of the firstorder channel capacitive currents into each transistor terminal. ΔQG = CGGΔVG − CGSΔVS − CGDΔVD − CGBΔVB (3.17) ΔQS = −CSGΔVG + CSSΔVS − CSDΔVD − CSBΔVB (3.18) ΔQD = −CDGΔVG − CDSΔVS + CDDΔVD − CDBΔVB (3.19) The channel storage charge model (3.17)(3.19) requires linearized capacitances in each linear region of operation in order to evaluate average power dissipated by parasitic capacitors. The following is a piecewise linear approximation of the BSIM capacitance model. Ohmic Region: QGohm = Cox (VGS − VT ) − (aS + aD)CoxVDS + bSBCox (VSB + VT − VFB) (3.20.1) Sohm ox GS T S ox DS Q 1 C (V V ) a C V 2 − = − − (3.20.2) Dohm ox GS T D ox DS Q 1 C (V V ) a C V 2 − = − − (3.20.3) Saturation Region: QGsat = bGSCox (VGB − VFB) + bSBCox (VSB + VT − VFB) (3.21.1) −QSsat = (1− xpart )bGSCox (VGS − VT ) (3.21.2) −QDsat = xpartbGSCox (VGS − VT ) (3.21.3) Cutoff Region: 28 QGoff = bSBCox (VGB − VFB) (3.22.1) −QSoff = 0 (3.22.2) −QDoff = 0 (3.22.3) Using continuity of charge at the ohmicsaturation boundary, we find S part GS a a(1 (1 x )b ) 2 = − − (3.23) Similarly, D part GS a a(1 x b ) 2 = − (3.24) Using continuity of charge at the cutoffsaturation boundary, we find QG = bSBCox (VGB − VFB) = bGSCox (VGS − VT ) + bSBCox (VSB + VT − VFB) (3.25) is satisfied when VGS = VT , putting the values for aS and aD back into (3.20) gives QGohm = Cox (VGS − VT ) − a(1− bGS)CoxVDS + bSBCox (VSB + VT − VFB) (3.26.1) Sohm ox GS T part GS ox DS Q 1 C (V V ) a(1 (1 x )b )C V 2 2 − = − − − − (3.26.2) Dohm ox GS T part GS ox DS Q 1 C (V V ) a(1 x b )C V 2 2 − = − − − (3.26.3) The charge storage currents are: Goff G Goff SB ox dQ dV i b C dt dt = = (3.27.1) G S D Gohm ox SB SB GS dV dV dV i C (1 b a(1 b ) a(1 b ) dt dt dt = ⎡ − − − − − − ⎤ ⎢⎣ ⎥⎦ (3.27.2) G S D Sohm ox part GS part GS 1 dV 1 1 dV 1 dV i C ( a( (1 x )b )) a( (1 x )b ) 2 dt 2 2 dt 2 dt = ⎡− + − − − + − − ⎤ ⎢⎣ ⎥⎦ (3.27.3) G S D Dohm ox part GS part GS 1 dV 1 1 dV 1 dV i C ( a( x b )) a( x b ) 2 dt 2 2 dt 2 dt = ⎡− + − − + − ⎤ ⎢⎣ ⎥⎦ (3.27.4) 29 G S Gsat GS ox GS SB ox i b C dV (b b )C dV dt dt = − − (3.27.5) G S Ssat ox part GS part GS dV dV i C (1 x )b (1 x )b dt dt = ⎡− − + − ⎤ ⎢⎣ ⎥⎦ (3.27.6) G S Dsat ox part GS part GS dV dV i C x b x b dt dt = ⎡− + ⎤ ⎢⎣ ⎥⎦ (3.27.7) Comparing the derivatives of (3.27) with (3.9)(3.12) gives the following linearized results for the transistor capacitances. Table 1 Linearized Parasitic Transistor Capacitances with Overlap Capacitance Cutoff Ohmic Saturation CGG bSB COX + CGSO + CGDO +CGBO COX + CGBO bGS COX+ CGSO + CGDO +CGBO CGS CGSO (1 − bSB−a(1−bGS))COX + CGSO (bGSbSB)COX+CGSO CGD CGDO (1 − bGS)aCox + CGDO CGDO CSG CGSO (1/2)Cox + CGSO (1 − xpart)bGS COX + CGSO CSS CGSO (1/2 − a(1/2− (1−Xpart)bGS))COX+ CGSO (1 − xpart)bGS COX+ CGSO CSD 0 −a(1/2 −(1− xpartb)bGS)COX 0 CDG CGDO (1/2)Cox+ CGDO xpartbGS COX+ CGDO CDS 0 (− 1/2 + a(1/2 − xpartb)) Cox − XpartbGS COX CDD CGDO a(1/2 − XpartbGS) COX+ CGDO CGDO The gate to drain and gate to source overlap capacitances shown in Figure 3.8 are becoming more significant in submicron and deep submicron technologies, therefore gate overlap capacitances are included in the linearized capacitance model in Table 1. The gate to substrate overlap capacitance, CGBO, is negligible in modern processes but is included for the sake of completeness. The BSIM model for the overlap capacitance is 30 CGSO = WCgso (3.28) which must be added to CGG, CGS, CSS, and CSG to the previous expression (3.27), so CGDO = WCgdo (3.29) which must be added to CGG, CGD, CDD, and CDG to the previous expression (3.27), so CGBO = 2LCgbo (3.30) which must be added to CGG to the previous expression (3.27). Figure 3.8 Gate overlap capacitances for FETs With the linearized capacitance model, average power supply current into the parasitic capacitances can be evaluated by integrating the firstorder channel capacitive currents into the transistor(s) connected to the power supply, which is usually the transistor source current(s). From the linearized capacitance model, it is essential to understand that the linearized capacitances are valid only within each piecewise linear region while the firstorder channel capacitive current into the source node of the transistors is computed. Therefore, the initial and final terminal voltages in each piecewise linear region, associated with the transistor(s) connected to the power supply, must be computed before the average power dissipation can be evaluated. Approximate solutions for circuit dynamics has been used very successfully in predicting instantaneous 31 voltage waveforms [36], and the approximate solution for circuit voltage is extended beyond the gate delay predictions to compute the average power dissipated from the power supply with the piecewise linear switching current–voltage (IV) model and capacitance–voltage (CV) model. 3.2 Ramp Input Approximation Rather than attempt an arbitrary input, the piecewise linear model assumes the input signal is a simple ramp with finite transition time as show in Figure 3.9. in in0 in0 in in in0 in in0 in0 in0 Tin in Tin in0 Tin V (t ) t t V (t) V (t ) V (t t ) t t t t V (t ) t t t ⎧ < = ⎪ + − < < + ⎨⎪ ⎩ > + & (3.31) where the slope of a ramp input is in in0 Tin in in0 in Tin V V (t t ) V (t ) t + − & = (3.32) Figure 3.9 Input ramp approximations Under Veendrick’s assumption, the shortcircuit power is proportional to the input rise and fall times and the load capacitance. Hence, it is essential to approximate the input 32 signal with a ramp approximation to evaluate shortcircuit current induced power dissipation. Also, the simple ramp approximation includes the shortcircuit current into the gate delay evaluation, which is essential to predict rise and fall time at any capacitive node [19] [36]. For a more general input approximation than the input expression of (3.31), the input to each resistance connected region is approximated as a series of piecewise linear segments as shown in Figure 3.10. Figure 3.10 Piecewise linear approximation of input ramps in resistance connected regions in in0 in0 in ink 1 in ink in in ink ink ink ink ink 1 ink 1 ink in inkmax inkmax V (t ) t t V (t ) V (t ) V (t) V (t ) (t t ) t t t t t t V (t ) t t + + + ⎧ < ⎪⎪⎪ ⎪ − ≈ ⎨ + − < < + − ⎪⎪⎪ > ⎪⎩ (3.33) in ink V (t )is determined by approximating the input waveform at a finite number of times, tink . The accuracy of the approximation increases with the number of time points. However, adding time points increases the amount of calculation necessary to 33 determine the voltages in the resistance connected region. First, we will find the approximate solution for circuit voltage with a ramp input (3.31). 3.3 Approximate Solution for Circuit Voltage 3.3.1 Resistive Connected Regions A resistive connected region is defined as a set of circuit nodes connected by paths through the source or drain terminals of transistors in the ohmic region of operation. A resistive connected region can be described with a conductance matrix, G, when the zeroorder switching current is calculated. G is a matrix for a resistive connected region and should not be confused with transconductance Gm for the mth transistor. When the mth transistor is in saturation, it is modeled as gate voltage controlled current source between the drain and source and has the effect of decoupling source and drain into separate resistive connected regions [36]. The steady state solution of circuit voltage in delay modeling encompasses nonsingular G and singular G cases [36]. However, solving for the steady state solution of circuit voltage when the G matrix is singular can be avoided in computing average power dissipation, because the power supply current into the transistor(s) in saturation is determined by gate controlled current source, which is independent of drainsource bias. Thus, the approximate solution for circuit voltage at each drain node is considered only with a nonsingular G matrix only for average power estimate. Instead of solving for all circuit node voltages at once, the complexity of the circuit is reduced by approximating the solution in each resistive connected region connected to the power supply. 34 3.3.2 Approximate Solution for Circuit Voltage with NonSingular G Matrix It is assumed that the circuit of interest consists of transistors and capacitors only. The mth transistor is connected to circuit nodes Sm, Gm, and Dm, and the cth capacitor is connected to nodes AC and BC as shown in Figure 3.11. Figure 3.11 Notation for transistor number “m” and circuit node names Large CMOS circuits can be partitioned into many resistively connected groups of nodes. Using the ramp approximation from equation (3.31) for the input nodes, the circuit dynamic equation can be generalized regardless of circuit topologies [36]. in in in in 0 in 0 Tn Tn Tp Tp dd dd dV C V V G (V (t ) V (t t )) G V G V G V 0 dt C + & +G + + & − + + + = (3.34) where G and C in bold letters represent twodimensional matrices and Cin ,Gin ,GTn , GTp , and Gdd are column vectors. It helps to simplify the circuit dynamic equation if the column vectors Iin (t0 ) and &Iin are defined as Iin (t0 ) = CinV& in +GinVin (t0 ) +GTnVTn +GTpVTp +GddVdd (3.35) Iin = GinVin & & (3.36) The circuit dynamic equation (3.34) can be rewritten as 35 in 0 in 0 dV V I (t ) I (t t ) 0 dt C +G + + & − = (3.37) where the G matrix is now the ondiagonal subblock for a single resistance connected region and the C matrix is rectangular in general, and includes capacitive coupling from nodes inside the resistance connected to all other circuit nodes including those inside and outside the resistance connected region [36]. The steady state solution, V% , after the exponential components die out has the form of equation (3.38). 2 0 0 0 V(t) V(t ) V(t t ) V (t t ) 2 − % = % + %& − + &%& (3.38) The steady state solution for a general circuit must satisfy the dynamic equation which can be written as in in 0 V dV I I (t ) dt G C ⎡ ⎤ = − ⎢ + + ⎥ ⎣ ⎦ % % & (3.39) Collecting terms of the same power of t, which leads to GV&%& = 0 (3.40) GV = −(CV+ Iin ) %& &%& & (3.41) GV(t0 ) = −(CV+ Iin (t0 )) % %& (3.42) The conductance matrix G for the resistance connected region will be nonsingular as long as the region includes the power or ground node. When G is nonsingular, G1 can be used to find V&%& = 0 (3.43) The equation (3.41) can be rewritten as 1 V G Iin %& = − − ⋅ & (3.44) 36 1 V(t0 ) G (CV Iin (t0 )) % = − − %& + (3.45) V(t0 ) % can be rewritten after substituting V&% , such that 1 1 V(t0 ) G (CG Iin Iin (t0 )) % = − − & + (3.46) Gis a small dimension matrix describing a single resistance connected region, so that G1 is not difficult to compute. It is possible to find a steady state solution in each resistance connected region knowing only the piecewise linear approximation(s) to VIN. Thus, solving the circuit dynamic equation with a ramp input, the approximate voltage at each node Dm in a resistively connected region can be written as m m m m m 0 D D D 0 D 0 D V ( t ) = V ( t ) + [V ( t ) V ( t ) ] e x p ( t  t ) τ % − % ⋅ − t > t 0 (3.47) The column vectors for the approximate voltages at each resistively connected node Dm are rewritten as V D m ( t ) = V D m ( t 0 ) + V D m ( t  t 0 ) % % &% (3.48) m 1 1 D 0 in in 0 Dm V% (t ) = [G− (CG− &I + I (t ))] (3.49) m 1 D in D m V%& = − [G − ⋅ &I ] (3.50) Therefore, the equation (3.48) is rewritten as m 1 1 1 D in in 0 in 0 D m V% ( t ) = [G − (C G − &I + I ( t ) ) − G − ( &I ( t  t ) ) ] (3.51) Unfortunately, G and C are not constant in general, but change as the switching transistors go into their various regions of operation. It is assumed that the solution beginning at t0 does not “know” that it will become invalid later, but can be extended 37 indefinitely forward in time with a constant G and C. This allows the upper limit in the integrals to be extended to infinity when the average power is evaluated. 3.4 Average turnoff Energy Evaluation with the Zeroorder Switching Current Model In a CMOS circuit, average turnoff energy occurs due to shortcircuit current flows during the time when the pFET and nFET network are on simultaneously. It is necessary to compute the power supply current into the source of every pFET for the time period when shortcircuit current occurs. Average turnoff energy is evaluated from the sum of shortcircuit currents in each piecewise linear region for any turningoff pFET connected to the power supply. Each turningoff transistor may cross through each region of operation, cutoff, ohmic, and saturation. Given the slope of the input waveform (or gate voltage VGm (t) ) and the slope of the output waveform (or drain voltage VDm (t) ) as functions of time from solving circuit dynamic equations, shortcircuit current drawn from the power supply current into each transition can be approximated with the zeroorder piecewise linear switching current, such that, T T 2 1 2 2 0 1 2 vdd(off)dt S (ohmic)dt + S (sat)dt + S (off)dt n t t m m m 0 m 1 t t t I I I I ⎡ ⎤ ⎢ ⎥ − = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ = Σ ∫ ∫ ∫ ∫ (3.52) where t0 is the time when the nFETs reach VGSN = VTn, and the power supply current into the source of pFETs are proportional to each drain to source bias pf pFETs connected to the power supply. Average turnoff (shortcircuit) energy is evaluated when the input has reached VGSN = VTn, and pFETs are operated in the ohmic and saturation regions and is computed as 38 dd 0 T E 2 Ivdd (off) t = V ⋅ ∫ −Ivdd(off)dt for ri sin g transitions (3.53) where the subscript ‘m’ in (3.52) is the transistor number of turningoff transistor(s) connected to the power supply. Each term in (3.52) comes from each piecewise linear approximation to the zeroorder quasistatic switching current into turnoff transistor(s) in ohmic, saturation, and cutoff regions which are evaluated individually in the following sections. 3.4.1 ZeroOrder Turnoff Current in Ohmic Region: The power supply current Ivdd(t) going into the source of every turningoff transistor(s) in ohmic is the zeroorder quasistatic current in ohmic region, and is computed as follows. ( ) 1 1 0 0 1 m mm 0 1 m m 0 1 0 D m m m m 0 m 0 0 t t t m t m t P m D S t t P m D dd t t t t P m D D (t ) D (t ) dd t IS (ohmic)dt ID (ohmic)dt a G V dt a G V (t) V dt a G V (t)+[V V ] e V dt − − ⎡ ⎤ ⎡ ⎤ ⎢ ⎥ = − ⎢ ⎥ ⎣ ⎦ ⎣ ⎦ ⎡ ⎤ = − ⎢ ⎥ ⎣ ⎦ ⎡ ⎤ = − ⎢ − ⎥ ⎣ ⎦ ⎡⎛ ⎞ ⎤ = − ⎢⎜ ⋅ ⎟ − ⎥ ⎢⎜ ⎟ ⎥ ⎢⎜ ⎟ ⎥ ⎣⎝ ⎠ ⎦ τ ∫ ∫ ∫ ∫ ∫ % % t1 > t0 (3.54) where VDm (t) % in (3.54) has a constant term and a time dependent term, so that the solution of equation (3.54) is written as 39 t1 t0 D 1 0 1 0 P Dm m Dm( t ) m 0 Dm m Dm( t ) 0 Dm( t ) 0 dd G e 1 V V V V 1 V ( ) 2 a t t t t [( )( ) ( )( )] − − − τ = − − + − − − % τ % %& t1 > t0 (3.55) where Dm 0 V% (t ) and Dm V&% are defined in (3.49) and (3.50) and are the column vector for each resistively connected node in the linear ohmic region from the time period between t0 and t1 . The delay time constant ( Dm τ ) has a general form for a resistive connected node [36], which is written as follows. 1 0 0 Dm Dm Dm 0 Dm 0 [G C V(t ) V(t ) ] V (t ) V (t ) − − τ = − % % (3.56) 3.4.2 ZeroOrder Turnoff Current in saturation region Before the transistor turns off completely, it may operate in saturation, and the power supply current Ivdd(t) going into the source node of turningoff transistor(s) in saturation is the zeroorder current in saturation, which is proportional to the gate voltage (or the slope of input waveform) and the zeroorder current in saturation is computed as follows. 40 2 2 S D 1 1 2 G m Sm T p m 1 2 T pm 1 T in t t t m t m t m t t dd m dd t (s a t) d t (s a t) d t = G dt G V t d t T I I V V V V V ⎡ ⎤ ⎡ ⎤ ⎢ ⎥ = − ⎢ ⎥ ⎢⎣ ⎥⎦ ⎢⎣ ⎥⎦ ⎡ ⎤ − ⎢ − − ⎥ ⎢⎣ ⎥⎦ ⎡ ⎡ ⎛ ⎞ ⎤ ⎤ = − ⎢ ⎢ ⎜ − ⎟ ⎥ − ⎥ ⎢ ⎣ ⎝ ⎠ ⎦ ⎥ ⎣ ⎦ ∫ ∫ ∫ ∫ 2 1 dd m 2 1 dd Tp Tin m G (t t ) (t + t )V V + V 2 T ⎛ − ⎞ = − ⎜ + ⎟ ⎝ ⎠ , t2 > t1 (3.57) 3.4.3 ZeroOrder Turnoff Current in Cutoff Region The power supply current into the source of transistor(s) in cutoff region is zero and is included for the sake of completeness. 2 T 2 t Sm(off) ∫ I dt = 0 (3.58) In the piecewise linear model, average power supply current for the zeroorder component into the source of turnoff transistor(s) is zero after the input reaches a steady state value or the end of input transition time ‘TTin’. 3.5 Average Turnon Energy Evaluation with the Zeroorder Piecewise Linear Current Model The power supply current Ivdd(t) into the source of turningon pFET is the sum of the dynamic current for charging the load capacitance and the shortcircuit current of turningoff nFETs. It is worth to mention that the average turnoff energy of nFETs is already included when the average turnon energy of pFETs is evaluated directly from 41 the power supply current. It is one of the advantages of evaluating average power by computing power supply current instead of evaluating current and voltage for each turnoff transistor(s) individually. For arbitrary slopes of input and output waveforms at the drain and gate, and including all operation regions, the power supply current Ivdd(t) into the source of turnon pFETs in a resistive connected region can be formulated as, si 3 si 3 Sm Sm Sm T n t t T Vdd T T t t 2 m=1 2 I (on) dt = I (off)dt + I (Sat)dt I (ohmic)dt ⎡ ⎤ ⎢ ⎥ − ⎢ + ⎥ ⎢ ⎥ ⎣ ⎦ ∫ Σ ∫ ∫ ∫ (3.59) where tsi is the time when an input signal ramps down to VGSP = VTp of transistor(s) connected to the power supply. As the input continues to ramp down, the pFETs go into saturation region from the time tsi to t3, and so on until pFETs turns off after the input reaches the steady state “Low”. Average turnon energy during the input falling transition period is then computed as T dd T vdd 2 E I vdd (on) = V ⋅ ∫ − I (on) dt (3.60) It is assumed that the solution beginning at T 2 and can be extended indefinitely forward in time with a constant G and C. This allows the upper limit in the integral to be extended to infinity. The power supply current Ivdd(t) going into each turnon transistor in each piecewise linear operation can be computed as follows. 3.5.1 ZeroOrder Turnon Current in Cutoff Region 42 T S (off) 2 si m dt 0 t ∫ I = (3.61) 3.5.2 Zeroorder Turnon Current in Saturation Region The power supply current Ivdd(t) going into the source of pFETs in saturation is a zeroorder quasistatic current in saturation, and is computed as follows. 3 3 3 S D S T p m si s i s i 3 d d dd dd T p m s i T in t t t m Gm m t t t t m t (s a t) d t (s a t) d t G (V V V )d t m m V G V t V V d t T I = − I = − − − ⎡ ⎛ ⎞ ⎤ = − ⎢ ⎜ − ⎟ − − ⎥ ⎢⎣ ⎝ ⎠ ⎥⎦ ∫ ∫ ∫ ∫ Pm 3 si dd m 3 si T Tin (t t )V G (t t ) V 2 T [ + ] = + , t3 > tsi (3.62) 3.5.3 ZeroOrder Turnon Currents in Ohmic Region In the ohmic region, the zeroorder drain current or the source current of a transistor is independent of the gate voltage. Therefore, the zeroorder turnon currents from the power supply Ivdd(t) into the sources of pFET are evaluated using the same equation as (3.55) regardless of rising or falling inputs, but with the sign changes in the V&% expression. In other words, the zeroorder turnon current is proportional to the approximate drain voltage of each pFET transistors connected to the power supply. Approximated voltage at each drain node depends on the column vectors &Iin and Iin (t0 ) in each piecewise linear region from which a positive or a negative input slope (V& in ) is given. 43 3.5.4 Resistive Connected Region with Steady State Input When the transistor is driven by a steady state input, the slope of input waveform or V& in is zero. The power supply current Ivdd(t) going into the source of pFETs in ohmic and saturation regions with a steady state input has to be reevaluated. 3.5.4.1 ZeroOrder Turnon Current in Saturation When the driving input to the transistor(s) connected to the power supply is in the steady state of the input falling transitions, the zeroorder turnon current for transistor(s) in saturation is reevaluated as follows. m 3 G t3 t tsi t si (V ∫ ∫ ∫ S D Tpm 3 si m m t m dd t (sat)dt =  (sat)dt = G  V  V )dt I I t3 > tsi where VGm has a Vin & component equal to zero, which leads to the solution as ⋅ = Gm(t3 tsi)(Vdd +VTpm) (3.63) 3.5.4.2 ZeroOrder Turnon Current in Ohmic Region With the input in steady state, the column vector &Iin becomes I in = G in Vin = 0 & & (3.64) And the steady state solution for circuit voltage in a resistive connected region has to be reevaluated as follows [36]. 1 1 V D m ( t  t 0 ) = G (C V + I in ) = G I in = 0 %& &%& & & (3.65) 44 V D m ( t ) = V D m ( t 0 ) + V D m ( t  t 0 ) = V D m ( t 0 ) % % %& % (3.66) The approximate solution for the circuit voltage at the drain node after the input is in the steady is rewritten as follows. D m D m D m D m D m 0 0 0 0 t  t V ( t ) = V ( t ) + [V ( t )  V ( t ) ] e x p (  ) τ % % ⋅ (3.67) Where V%Dm (t0 ) is already defined by (3.49). Thus, zeroorder turnon current in the ohmic region is then rewritten for input in steady state. Yet, the G and C matrices are not constant in general, but remain constant in the ohmic region, so that the solution for the approximate circuit voltage at the drain terminal can be extended forward in time with a constant G and C matrix in the ohmic region, which allows the integrals to be extended to a specific time boundary or to infinity in time as seen in equations (3.68) and (3.69). 3 3 T T t t T dt dt ( = − = − ∫ ∫ ∫ S D m D m 3 m m P m dd t (ohmic) (ohmic) a G V (t)V ) I I T > t3 ( ) ( ) ( ) T t3 Dm [ ) T Vdd T e 1 ) ) Dm ] − ⎛ − ⎞ = − − + − + ⎜ τ − ⎟ − τ ⎜⎜ ⎟⎟ ⎝ ⎠ % % aPm Gm VDm(t0 t3 t3 VDm(t3 VDm(t3 (3.68) Here in (3.68), it can be proved that the quasistatic state voltage % Dm V at the output node follows the steady state value Vdd as t1 goes to infinity, so that the first two terms would cancel out. Thus, if an input reaches a steady state voltage, the boundary to the final region of operation of pFETs in the ohmic can be extended to infinity. Such that, 45 t 3 t3 dt dt ( ∞ ∞ ∞ = − = − ∫ ∫ ∫ S D m D m 0 m m P m dd t (ohmic) (ohmic) a G V (t) V ) I I = [− Vdd − ) τDm % ) + τDm )] aPm Gm t3 VDm(t3 + VDm(t3 (t3 (Vdd − ) )τDm = aPm Gm VDm(t3 (3.69) 3.6 Switching Energy in the Transistor Parasitic Capacitances The parasitic capacitors from transistors connected directly to the power supply also contribute power dissipation, because dissipative current flows in the channels of the switching transistor(s) as channel charge is redistributed within the channel. Therefore, the switching current induced energy is evaluated by integrating over a cycle of channel capacitive currents into the source of every pFET connected to the power supply and is written as follows. 0 0 T n T T 2 dd dd m T m t t 2 m 1 Ei V ivdd (t) V is is dt vdd [ ] = = ⋅ ∫ − = ⋅Σ ∫ +∫ (3.70) where E ivdd is the average switching energy drawn from the power supply current due to the nonlinear capacitive currents of the switching transistor(s) connected to the power supply. Lower case current ‘i’ is used to differentiate from “I” in zeroorder quasistatic current when average turnoff and turnon energy are evaluated. Expression from (3.70) is then evaluated in equation (3.71) and (3.72) individually which has the same integration boundaries of the zeroorder switching energy evaluated in equations (3.52) and (3.59). 46 0 T 1 2 2 1 2 n T n 2 t m m m m m 1 m 1 0 t t is dt is (ohmic)dt + is (sat)dt + is (off)dt = = t t t ⎡ ⎤ = ⎢ ⎥ ⎢ ⎥ ⎢⎣ ⎥⎦ Σ∫ Σ ∫ ∫ ∫ (3.71) n T n 3 T m 2 m m m m 1 2 m 1 T 3 tsi t T is dt is (off)dt + is (sat)dt + is (ohmic)dt = = tsi t ⎡ ⎤ = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ Σ∫ Σ ∫ ∫ ∫ (3.72) The average power supply current into the channel storage elements is the firstorder current and is a piecewise linear approximation of channel capacitive currents of the transistor in the cutoff, ohmic, and saturation so that the integral can be computed with the same technique, knowing only the initial and final voltage at the drain of each pFET connected to the power supply. CSGm , CSSm , CSDm , and CSBm are the lumped capacitances in Table 1 associated with each transistor terminal in the mth transistor(s) connected to the power supply. VSm Δ and VBm Δ are zero, because the source and body (substrate) voltages do not change for pFET that are directly connected to the power supply in digital CMOS circuit applications. Therefore, equation (3.71) and (3.72) are simplified to each component of integration individually as expressed in (3.73), (3.74), and (3.75). m m m m m m m m 0 0 1 1 G S D B m SG SS SD SB t t ohmic t t dV dV dV dV is (ohmic)dt = C C C C dt dt dt dt dt ⎛ ⎞ ⎜⎜− + − − ⎟⎟ ⎝ ⎠ ∫ ∫ (3.73) ( ) ( ) m m m m m m1 m 0 m m 1 m 0 1 1 SG (ohmic) G SD (ohmic) D 0 0ohmic SG (ohmic) G (t ) G (t ) ohmic SD (ohmic) D (t ) D (t ) ohmic t t C V  C V  t t C V V C V V ⎡ ⎤ = ⎢− ⋅ − ⋅ ⎥ ⎣ ⎦ = − ⎡ ⋅ − ⎤ − ⎡ ⋅ − ⎤ ⎣ ⎦ ⎣ ⎦ It should be noted that the lumped capacitors are not constant as the transistors switch from ohmic to saturation. Thus, the lumped terminal capacitors from the mth transistor in (3.73) for ohmic region are different from the lumped terminal capacitors in (3.74) for 47 transistor in saturation as shown by the linearized lumped capacitors in Table 1. When pFET in saturation, the channel capacitive current is computed as m m m m m m m m 2 2 1 1 G S D B m SG SS SD SB sat t t dV dV dV dV is (sat)dt = C C C C dt t t dt dt dt dt ⎛ ⎞ ⎜⎜ − + − − ⎟⎟ ⎝ ⎠ ∫ ∫ (3.74) ( ) ( ) m m m m m m 2 m 1 m m 2 m 1 2 2 SG (sat) G SD (sat) D 1 1sat SG (sat) G (t ) G (t ) SD (sat) D (t ) D (t ) sat t t C V  C V  t t C V V C V V ⎡ ⎤ = ⎢− ⋅ − ⋅ ⎥ ⎣ ⎦ = ⎡− ⋅ − − ⋅ − ⎤ ⎣ ⎦ Where CSGm and CSDm changes as transistors switch from ohmic to saturation. Similarly, in the cutoff region, m m m m m m m m 2 2 T T 2 2 G S D B m SG SS SD SB t t off dV dV dV dV is (off)dt = C C C C dt dt dt dt dt ⎛ ⎞ ⎜⎜− + − − ⎟⎟ ⎝ ⎠ ∫ ∫ (3.75) T T 2 2 m m m m m m m 2 m m m 2 T T 2 2 SG (off ) G SD (off ) D 2 2off SG (off ) G ( ) G (t ) SD (off ) D ( ) D (t ) off C V  C V  t t C V V C V V ⎡ ⎤ = ⎢− ⋅ − ⋅ ⎥ ⎢⎣ ⎥⎦ = ⎡− ⋅ ⎛ − ⎞ − ⋅ ⎛ − ⎞⎤ ⎢ ⎜ ⎟ ⎜ ⎟⎥ ⎣ ⎝ ⎠ ⎝ ⎠⎦ (3.72) is evaluated using the same approach for the other half cycle. The computation to the channel capacitive current contributed to the energy dissipation is simplified to the calculation of the initial and final voltage at drain and gate for each piecewise linear region with the linearized capacitance model. 3.7 Summary The piecewise linear transistor model consists of a zeroorder switching current model and a channel storage charge model. The zeroorder switching current model 48 evaluates the average power supply current at the time period when a CMOS circuit dissipates shortcircuit current and dynamic current. Equation (3.56) and (3.70) are derived from the generalized circuit dynamic equation with the zeroorder switching current model to predict the power supply current into the transistors connected to the power supply during the transistors in the ohmic region. When the transistors connected to the power supply are in saturation, the power supply current is proportional only to integral of the gate controlled current sources connected to the power supply which simplifies the computation because the current sources are independent of the drain voltages of the transistors in saturation. Total power supply current or total average power can be evaluated much quicker with the simplified solutions of the integrals of transistor switching transient currents to account for the short circuit current, dynamic current, and channel capacitive current into a total power calculation. In the following chapter, the power supply current into an inverter circuit driving different load capacitances will be evaluated, and the integral of each switching transient current and the solutions for each piecewise linear region will be used to obtain a total average power from the inverter driving different load capacitances. 49 CHAPTER 4 AVERAGE POWER ANALYSIS OF INVERTER WITH A PIECEWISE LINEAR MODEL 4.0 Introduction A piecewise linear transistor model was introduced in the previous chapter. In this chapter, the piecewise linear model will be used to evaluate the average power dissipation of a simple inverter gate. The average power will be computed from the power supply current into the source of pFET of the inverter, which is the sum of zeroorder quasistatic switching current and firstorder channel capacitive currents. The model computes average power of inverter by integrating zeroorder switching current and firstorder channel capacitive currents over a switching cycle. The integration of each switching transient current is simplified to a solution compatible with the efficient piecewise linear delay model [36]. Average power evaluation by the model is compared with SPICE simulation of the same circuit over a wide range of input slopes, transistor sizes, and different capacitive loads. 4.1 Average Power Analysis of Inverter Driving Load Capacitance An inverter has one drain node between the power supply and ground, so that the average turnoff (short circuit) energy, average turnon energy, and switching energy 50 of the transistors parasitic capacitances are evaluated based on the approximate circuit voltages at the drain and gate of pFET in the inverter, and the input slope were approximated by an efficient piecewise linear delay model [36]. Figure 4.1 Inverter driving load capacitance with input ramp approximation Using the ramp input approximation to the circuit dynamic equation of the inverter, Figure 4.2 is the graphical representation of piecewise linear approximation to the circuit voltages at the drain with transistors transitional boundaries and operation regions [36]. There are nine boundary lines and eight piecewise linear regions, which are derived from the piecewise linear switching current equations and the circuit dynamic equation for the inverter. It is necessary to define the terminals of the pFET, which is connected to the power supply, a driving input node, and drain node of inverter to facilitate average power calculation, so that we may write VGSN = VIN, VDSN = VOUT , VGSP = VIN – VDD, and VDSP = VOUT – VDD. Boundaries of each piecewise linear region as functions of time in ohmic, saturation, and cutoff (tsi, t1, t2, t3, TTin), terminal voltages (VDS, VGS), and each piecewise linear regions (R0 →R8) for the pFET and nFET in inverter are also shown in Figure 4.2. 51 Figure 4.2 Inverter transient analysis with boundaries and operation regions with rising input ramp approximation In Figure 4.2, a ramp input is assumed in the inverter for the first half cycle, and the output waveform is plotted against t/TTin from the closed form solution of the circuit dynamic equation (Eq. 3.37). Regions of operation in the inverter are denoted as “R1 Sat Ohm” which indicates region 1 with nFET in saturation and pFET in the ohmic region, and “VGS = VDD” on xaxis is the end of the input transition time “TTin”. Fig. 4.4 uses the same definitions of the piecewise linear region in the cutoff, ohmic and saturation and the model parameters. It should be noted that a fast input ramp is equivalent to a short input transition time “TTin”, so that curve 3 in Fig. 4.2 and Fig.4.4 is corresponding to a fast input ramp and curve 1 is the output waveform approximation of a slow input ramp [36]. 4.1.1 Turnoff Energy Analysis In an inverter gate, turnoff (shortcircuit) energy is evaluated from the pFET transistor, connected to the power supply, when it turns off. Turnoff energy is proportional to the input transition time on the gate and the zeroorder switching off current of pFET provided from the power supply during input (0→1) transition during the load capacitance discharge cycle. Turnoff energy is then evaluated by integrating the zeroorder switching off current provided by the power supply into the source of pFET 52 from the time period when it is on to off. If an input is a slow rising input ramp, the voltage waveform at drain node as shown in waveform 1 (Figure 4.2) is a possible solution. Then, given the input slope and the output waveform, the zeroorder current into the source of the turning off pFET is evaluated from the sum of pFET current from its on (ohmic) state to off state across the ohmic region from initial time t0 to t1 and across saturation region from t1 to t2 respectively, which is written according to the integration of the zeroorder switching current in each respective operating region in equation (3.52). T T 2 2 S S S 1 2 0 0 1 2 EIvdd(off ) V Ivdd(off)dt V I (ohmic)dt + I (sat)dt + I (off)dt t t dd dd m m m t t t t ⎡ ⎤ ⎢ ⎥ = − = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ∫ ∫ ∫ ∫ D t1 t0 Dm dd D 1 0 m( t0 ) m 2 1 dd 1 0 m 2 1 dd Tp Tin Pm m Dm( t ) Dm( t ) 0 0 Dm m V G e 1 V V Vdd V 1 (t + t )V V ( ) G (t t ) V +V 2 2 T a t t t t { [( )( ) ( )( )] } − − − τ = − − + − − ⎛ − ⎞ − + − ⎜ + ⎟ ⎝ ⎠ % τ % &% Where t1 > t0 and t2 > t1 (4.1) When the input is a fast ramp, the pFET may turn off before it goes into saturation region. The slope of the voltage waveform at the drain node shown in the waveform 3 (Figure 4.2) is a possible solution, such that the shortcircuit energy drawn from the power supply is reevaluated for ohmic region only as in equation (4.2). T T 2 2 S S 2 0 0 2 EIvdd(off ) V Ivdd(off)dt V I (ohmic)dt + I (off)dt t dd dd m m t t t ⎡ ⎤ ⎢ ⎥ = − = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ∫ ∫ ∫ t2 > t0 (4.2) dd D 2 0 2 0 Dm Dm( t ) m 0 Pm m Dm(t ) Dm(t ) Dm 0 0 t2 t0 dd V G e 1 V V V V 1 V ( ) 2 {a [( )( ) (t t )( t t )]} − − − τ = − − % τ + − % − &% − It should be noted that turnoff energy is evaluated only when the input is rising or the transistor(s) connected to the power supply turns off. 53 4.1.2 Turnon Energy Analysis Turnon energy is evaluated during input (1→0) transition when the pFET of the inverter, connected to the power supply, turns on and conducting the zeroorder switching current during the load capacitance charging cycle. The power supply current is the sum of the zeroorder switching currents for charging the load capacitance and the shortcircuit current of turningoff nFET. Resembling turnoff energy evaluation, output waveform approximation in Figure 4.4 is derived to compute turnon energy. Figure 4.3 Inverter driving load capacitance with input falling ramp approximation Figure 4.4 Inverter transient analysis with boundaries and operation regions with input falling ramp approximation Turnon energy is computed from the sum of zeroorder switching current of pFETs connected to the power supply and the short circuit current of turningoff nFET connected with pFETs. It should be noted that shortcircuit current of nFET is drawn 54 from the power supply current from the channel of turningon pFET. Therefore, evaluation of turnon energy is simplified to the calculation of total current into pFETs only. Equation (4.3) shows the turnon energy evaluated from the current of pFETs connected to the power supply during pFETs turningon period. T S S S T T 2 2 si 3 si 3 T EIvdd(on) V Ivdd (on)dt V I (off)dt + I (sat)dt + I (ohmic)dt t t dd dd m m m t t ⎡ ⎤ − ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ = ∫ = ∫ ∫ ∫ ( ) ( ) ( ) Pm m 3 si dd m 3 T P 3 3 Tin Dm(t0 ) T t3 Dm Dm(t3 ) Dm(t3 ) Dm dd si m dd V G (t  t ) (t t )V V a G V T t V T t 2 T e 1V V [ ] { [ ] } − − + + − − + − + ⎛ ⎞ ⎜ τ ⎟ ⎜ − ⎟ − τ ⎜ ⎟ ⎝ ⎠ = + % % Where t3 > tsi and T > t3 (4.3) 4.1.3 Switching Energy in the Transistor Parasitic Capacitances The power supply current into the parasitic capacitances of pFET, connected to the power supply, is the firstorder channel capacitive currents in the transistors. Switching power of the parasitic capacitances is evaluated by integrating the firstorder channel capacitive currents over a switching cycle to measure if the channel capacitive currents draw energy from the power supply. Equation (3.70) can be rewritten for a simple inverter gate, such that switching energy of the parasitic capacitances of the pFET can be computes as 0 0 T T T 2 dd dd m T m t t 2 Ei V ivdd (t) V is is dt vdd = ⋅ ∫ − = ⋅[∫ +∫ ] 0 T 2 dd m m m m m m t 2T t1 t2 tsi t3 T V is (ohmic)dt + is (sat)dt + is (off)dt is (off)dt + is (sat)dt + is (ohmic)dt t1 t2 tsi t3 ⎡ ⎤ = ⎢ + ⎥ ⎢ ⎥ ⎢⎣ ⎥⎦ ∫ ∫ ∫ ∫ ∫ ∫ 55 ( ) ( ) ( ) ( ) ( ) m m1 m 0 m m 1 m 0 m m 2 m 1 m m 2 m 1 m m 3 m si m m 3 dd SG (ohmic) G (t ) G (t ) ohmic SD (ohmic) D (t ) D (t ) ohmic SG (sat) G (t ) G (t ) sat SD (sat) D (t ) D (t ) sat SG (sat) G (t ) G (t ) sat SD (sat) D (t ) D V C V V C V V C V V C V V C V V C V V = {−⎡⎣ ⋅ − ⎤⎦ − ⎡⎣ ⋅ − ⎤⎦ − ⎡ ⋅ − ⎤ − ⎡ ⋅ − ⎤ − ⎣ ⎦ ⎣ ⎦ ⎡ ⋅ − ⎤ − ⋅ − ⎣ ⎦ ( ) ( ) ( ) m si m m m 3 m m m 3 (t ) sat SG (ohmic) G (T) G (t ) ohmic SD (ohmic) D (T) D (t ) ohmic C V V C V V } ⎡ ⎤ − ⎣ ⎦ ⎡ ⋅ − ⎤ − ⎡ ⋅ − ⎤ ⎣ ⎦ ⎣ ⎦ (4.4) Where the lumped capacitors CSGm and CSDm in ohmic region are different from CSGm and CSDm in saturation as shown in Table 1. The simplified form in (4.4) allows a direct evaluation to the channel capacitive currents knowing only the initial and final voltage at drain and gate terminal with the linearized channel capacitances model. 4.2 Energy per cycle Calculation Total energy dissipation in the inverter is computed from the sum of turnoff energy, turnon energy, and switching energy of parasitic capacitors of transistors connected to the power supply. Average power in (4.5), approximated by the piecewise linear model for a CMOS circuit, is equivalent to energy per cycle. Therefore, energy per cycle is used interchangeably with the average power. avg (EIvdd (off ) EIvdd (on) Eivdd ) P = 1 T ⋅ + + (4.5) 4.2.1 Energy Per Cycle Evaluation by the Model Table 2 is an example of computing energy per cycle from the power supply for the inverter in Figure 4.5. Energy per cycle simulation of the inverter was calculated by the program in appendix III. The program computes the energy of the power supply 56 current from the sum of piecewise linear transistor current across each operating region for a complete cycle. Turnoff energy is denoted as EIvdd(off), and Turnon energy is denoted as EIvdd(on), and switching energy of the parasitic capacitances is denoted as Eivdd. Sum of turnoff energy, turnon energy, and switching energy of parasitic capacitors is the average power. Figure 4.5 Energy per cycle calculation of inverter by the model with TSMC 0.18μm process TTin (Picosec.) Input Transition E Ivdd(off) (0→1) E Ivdd(on) (1→0) E ivdd (0→1) E ivdd (1→0) Σ E (Energy per cycle predicted by Model) 1000 5.00E13 1.34E12 4.57E14 2.66E14 1.821E12 900 4.37E13 1.32E12 4.57E14 2.66E14 1.741E12 800 3.76E13 1.31E12 4.57E14 2.66E14 1.662E12 700 3.15E13 1.29E12 4.57E14 2.66E14 1.583E12 600 2.54E13 1.27E12 4.57E14 2.66E14 1.506E12 500 1.96E13 1.25E12 4.57E14 2.66E14 1.431E12 450 1.67E13 1.25E12 4.57E14 2.66E14 1.395E12 400 1.39E13 1.24E12 4.57E14 2.66E14 1.360E12 350 1.12E13 1.23E12 4.57E14 2.66E14 1.327E12 300 8.63E14 1.23E12 4.57E14 2.66E14 1.294E12 250 6.21E14 1.22E12 4.57E14 2.66E14 1.264E12 200 4.02E14 1.22E12 4.57E14 2.66E14 1.237E12 150 2.13E14 1.21E12 4.57E14 2.66E14 1.213E12 130 1.48E14 1.21E12 4.57E14 2.66E14 1.205E12 110 9.24E15 1.21E12 4.57E14 2.66E14 1.198E12 100 6.78E15 1.21E12 4.57E14 2.66E14 1.195E12 90 4.59E15 1.21E12 4.57E14 2.66E14 1.192E12 Table 2 Energy per cycle simulation of inverter in Fig.4.5 using PWL model for various input transition time TTin from 1000ps to 20ps 57 4.2.2 Energy per cycle simulation in SPICE In SPICE, energy per cycle of a circuit can be simulated from the power supply or the transistor devices in the circuit. In Table 3, the SPICE shows an inconsistency of energy per cycle evaluated from the power supply and devices in the same circuit. Since the BSIM3v3 is a chargeconserving transistor model, the average power supply current from the power supply in SPICE is used as a reference to confirm the model’s accuracy. TTin(Picosec.) Simulated energy per cycle from inverter transistors Simulated energy per cycle from inverter power supply Energy per cycle predicted by Model 1000 1.914e12 1.895e12 1.821E12 900 1.822e12 1.803e12 1.741E12 800 1.734e12 1.712e12 1.662E12 700 1.647e12 1.623e12 1.583E12 600 1.563e12 1.537e12 1.506E12 500 1.482e12 1.455e12 1.431E12 450 1.444e12 1.416e12 1.395E12 400 1.408e12 1.377e12 1.360E12 350 1.373e12 1.341e12 1.327E12 300 1.340e12 1.306e12 1.294E12 250 1.309e12 1.274e12 1.264E12 200 1.281e12 1.245e12 1.237E12 150 1.258e12 1.220e12 1.213E12 130 1.250e12 1.211e12 1.205E12 110 1.243e12 1.204e12 1.198E12 100 1.240e12 1.200e12 1.195E12 90 1.238e12 1.197e12 1.192E12 Table 3 Comparisons of energy per cycle predictions in SPICE and PWL model for the inverter in Fig.4.5 4.3 Model Accuracy of An Inverter Driving Load Capacitance An inverter driving different load capacitances is used to test for the accuracy of piecewise linear model for the average power evaluation. The model accuracy is measured with reference to the SPICE energy per cycle simulation from the power supply 58 in a standard 0.5μm process and a deep submicron 0.18μm process. The first circuit is the inverter driving a100 fF load capacitance, and the second circuit is the inverter driving inverter load. There are two reasons of choosing a large output capacitor and a small capacitive load. First, the large load capacitance has much larger impact on the transistor zeroorder switching current than the channel storage charge in the channel, so that the zeroorder switching current model can be measured for its accuracy in predicting the turnoff (short circuit) power and average turnon power. Also, the accuracy of the model parameters for the zeroorder switching current can be justified while the effect of the channel capacitances is not included. However, adjusting the model parameters only for the shortcircuit current as predicted in the SPICE would also affect the model accuracy to evaluate the turnon energy. Therefore, the model parameters are not optimized for the individual zeroorder and firstorder switching currents, but the model parameters are averaged to evaluate an average switching transient currents drawn from the power supply. 4.3.1 Model Accuracy in AMI CMOS 0.5μm Process (Lmin = 0.6μm) K is a ratio of pFET transistor width to nFET transistor width. K has 1, 2, and 4 for different inverter transistor ratio. Figure 4.6, 4.7, and 4.8 is the energy per cycle simulation predicted by the model in comparisons with the SPICE. 59 Figure 4.6 Accuracy of the PWL model in inverter gate (K = 4) driving 100fF load Figure 4.7 Accuracy of the PWL model in inverter gate (K = 2) driving 100fF load 60 Figure 4.8 Accuracy of the PWL model in inverter gate (K = 1) driving 100fF load 4.3.2 Model Accuracy in TSMC CMOS 0.18μm Process (Lmin = 0.18μm) Testing the accuracy and validity of the model in different CMOS process is to confirm the portability of the piecewise linear model. Accuracies of the piecewise linear model shows the excellent agreements in high frequencies with the SPICE’s predictions in TSMC 0.18μm process while a different set of model parameters for TSMC 0.18μm process are used. Figure 4.9 Accuracy of the PWL model in inverter gate (K = 4) driving 100fF load 61 Figure 4.10 Accuracy of the PWL model in inverter gate (K = 2) driving 100fF load The piecewise linear model shows that average power prediction for large input transitions at low switching frequencies is less accurate than small transition time in the high frequencies. The results indicate that the shortcircuit current is dominant and underestimated for slow inputs. Inaccuracy of the piecewise linear model for slow inputs is twofolds. First, the zeroorder switching current underestimates the current waveform predicted by SPICE due to an approximated transistor current model less accurate in ohmic region than the current predicted by the SPICE. Second, the conductance and transconductance is chosen to match the IV characteristics of the SPICE BSIM3v3 model in a region of large current and a region of small current, thus, the accuracies of the average power predictions in some circuit topologies may be better than the others for the same input slopes. However, overall accuracy for slow inputs is fairly well controlled within 10% error of SPICE in average for all circuits under tests. 62 4.4 Model Accuracy of Inverter Driving Inverter Gate Load Figure 4.11 Inverter driving gate load Load capacitance is not the dominant factor any more since the inverter gate capacitance is comparable to the driver inverter size. The channel capacitive current from the parasitic capacitances is comparable to the zeroorder switching current drawn from the power supply current when the inverter driving a small load, and now the channel capacitive current has more impacts on the average power than previous case for the inverter driving large capacitance load. 4.4.1 Model Accuracy in AMI CMOS 0.5μm Process (Lmin = 0.6μm) Figure 4.12 Accuracy of the PWL model in inverter gate K = 2 driving inverter load (WP/Wn=2.4μm/2.4μm L=0.6μm) 63 Figure 4.13 Accuracy of the PWL model in inverter gate K=1 driving inverter load (WP/Wn=2.4μm/2.4μm L=0.6μm) 4.4.2 Model Accuracy in TSMC CMOS 0.18μm Process (Lmin = 0.18μm) Figure 4.14 Accuracy of the PWL model in inverter gate driving inverter load (K = 4) 64 Figure 4.15 Accuracy of the PWL model in inverter gate driving inverter load (K = 2) Figure 4.16 Accuracy of the PWL model in inverter gate driving inverter load (K = 1) 4.5 Summary This chapter has illustrated the simplified transistor switching current model in predicting the average power dissipation of the inverter driving different load capacitances. As indicated by [8], modeling of the CMOS transistors as series of resistances and capacitances can approximate the transistor performances very accurately in digital CMOS applications. Even though the transistor in the ohmic region is not as accurate as the transistor in saturation, the piecewise linear model has achieved average power predictions within 5% of errors of SPICE for input transition times below 500pico 65 second. It is encouraging that the simplified switching current (IV) and (CV) models can achieve the target accuracy when the input is switching in a high speed, which is common for most large integrated circuits. There are two discrepant average power simulations from SPICE in each plot. The average power predicted by the piecewise linear model is much closed to the SPICE’s average power evaluated from the power supply current than from the total transistor devices. The discrepancies in the average power simulations from the SPICE are reduced when the transistors shrink to a 0.18μm process from a 0.5μm process. 66 CHAPTER 5 AVERAGE POWER ANALYSIS OF COMPLEX GATES WITH A PIECEWISE LINEAR MODEL 5.0 Introduction In Chapter four, the piecewise linear model is applied to the inverter gate, and the piecewise linear model for the average power evaluation is within 10% average error of SPICE for a wide range of input slopes, different capacitor loads, different transistor sizes and load capacitances, and different process technologies in submicron AMIS 0.5μm and deep submicron TSMC0.18μm process. The piecewise linear model is applicable not only to predict a simple inverter gate, but also extendable to other circuit topologies. The piecewise linear model has shown its scalable and portable among submicron and deep submicron processes by using different set of model parameters. Appendix II includes model parameters used in piecewise linear model for AMIS 0.5μm and TSMC 0.18μm processes. 5.1 Average Power Analysis of Twoinput NAND Gate In this chapter, the applications of the piecewise linear model are extended beyond an inverter gate analysis. Complex gates, such as a twoinput NAND gate and an OAI gate are common digital CMOS circuits and are used as the test circuits in this 67 chapter. NAND gate uses the same model as to evaluate the power supply current into the circuit, but the two dimensional G and C matrices is written according to the drain nodes in each piecewise linear region. Similar to the inverter analysis, the power supply current drawn from the supply into the circuit is evaluated from pFETs that are switching. The average power predicted by the model is compared with SPICE by varying input slopes, different transistor sizes, output loads, and process technologies. 5.1.1 Twoinput NAND Gate Driving Load Capacitance Fig. 5.1 is the twoinput NAND gate with input signals A and B. The gate drives a constant 100fF load. Average power of NAND gates is evaluated when only input A is switching for a complete cycle. Multiple inputs can be handled by making in V a column matrix, but the output node driving the load is critical for evaluating average power from the power supply. The pullup parallel connected transistors are the same size and so does the pulldown series connected transistors. The width ratio of the PMOS transistor to NMOS transistor changes from K = 4, 2, and 1. Figure 5.1 Twoinput NAND driving load capacitance 68 Energy per cycle is calculated with different input transition time and a different load for the twoinput NAND with the input signal ‘A’ switched from a cycle. Switching input signal ‘B’ resemble an inverter driving a capacitive load. Therefore, switching B is not discussed. 5.1.2 Model Accuracy of Twoinput NAND in AMI 0.5μm Process (Lmin = 0.6μm) The average power of NAND gate is evaluated when the input A is switching for a complete cycle and the input of the lower NMOS transistor stay high. Fig. 5.2 shows the average power of NAND gates against various input slopes. Input rise time varies from 50ps to 1500ps and width ratio of PMOS transistors to NMOS transistors varies from K = 4, 2, and 1. Average error was within 3% of SPICE for small input slopes at the high switching frequencies and within 10% for large input slopes at the slower switching frequencies. Figure 5.2 Accuracy of the PWL model for twoinput NAND K = 4 (Wp/Wn = 9.6μm/2.4μm) driving 100fF load 69 Figure 5.3 Accuracy of the PWL model for twoinput NAND K = 2 (Wp/Wn = 4.8μm/2.4μm) driving 100fF load Figure 5.4 Accuracy of the PWL model for twoinput NAND gate K = 2 (Wp/Wn = 4.8μm/2.4μm) driving inverter load 70 Figure 5.5 Accuracy of the PWL model for twoinput NAND gate K = 1 driving inverter load (Wp/Wn = 2.4μm/2.4μm) 5.1.3 Model Accuracy of Twoinput NAND in TSMC 0.18μm Process Figure 5.6 Accuracy of the PWL model for twoinput NAND gate K = 4 (Wp/Wn = 2.88μm/0.72μm) driving 100fF load 71 Figure 5.7 Accuracy of the PWL model for twoinput NAND gate K = 2 (Wp/Wn = 1.44μm/0.72μm) driving 100fF load Figure 5.8 Accuracy of the PWL model for twoinput NAND gate K = 1 (Wp/Wn = 0.72μm/0.72μm) driving 100fF load 72 Figure 5.9 Accuracy of the PWL model for twoinput NAND gate K = 4 driving inverter load (Wp/Wn=2.88μm/1.44μm L=0.18μm) Figure 5.10 Accuracy of the PWL model for twoinput NAND gate K = 2 driving inverter load (Wp/Wn=1.44μm/0.72μm L=0.18μm) 73 Figure 5.11 Accuracy of the PWL model for twoinput NAND gate K = 1 driving inverter load (Wp/Wn=0.72μm/0.72μm L=0.18μm) 5.2 Average Power Analysis of OAI Gate Fig. 5.12 is an OAI gate with input A, B, and C. Input A = 0→1, B = 1, and C = 0 are assumed when the average power of OAI gates is evaluated. The model allows multiple inputs by making VIN as a column matrix, but only the supply node and the drain of pFET connected to the power supply are necessary for evaluating average power from the power supply. The width of PMOS transistors to NMOS transistors varies from K = 4, 2, 1 driving a constant 100fF load with different input slopes. A submicron 0.5μm process and deep submicron 0.18μm process parameters are used to confirm the model’s accuracy. 5.2.1 Average Power Analysis of OAI Gate Driving Load Capacitance 74 Figure 5.12 OAI gate driving 100fF load 5.2.1.1 Model Accuracy of OAI gate in AMI 0.5μm Process Average power of OAI gate is evaluated based on one switching cycle. Inputs A switches for a complete cycle while the input B is tied to VDD and the input C is tied to ground. Accuracy for OAI gates driving a constant 100fF with different transistor K ratio is still within 3% error of SPICE for small input slopes and in 10% error of SPICE for large input slopes in average. 75 Figure 5.13 Accuracy of the PWL model in OAI gate K = 4 (Wp/Wn = 9.6μm/2.4μm) driving 100fF load in 0.5μm process Figure 5.14 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 4.8μm/2.4μm) driving 100fF load in 0.5μm process 76 Figure 5.15 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 2.4μm/2.4μm) driving 100fF load in 0.5μm process 5.2.1.2 Model Accuracy of OAI Gate in TSMC 0.18μm Process Threeinput OAI gate is tested in TSMC 0.18μm process as well to measure the model’s accuracy in different process technologies. Accuracy of OAI gate driving a constant 100fF with different transistor K ratio is within 5% of SPICE for small input slopes and within 10% of SPICE for large input slopes. 77 Figure 5.16 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 2.88μm/0.72μm) driving 100fF load in 0.18μm process Figure 5.17 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 1.44μm/0.72μm) driving 100fF load in 0.18μm process 78 Figure 5.18 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 0.72μm/0.72μm) driving 100fF load in 0.18μm process 5.2.2 Average Power Analysis of OAI Gate Driving Inverter Load In this case, average power of OAI gate is evaluated with input, A, which switches for a complete cycle whiles input, B, tied to VDD and input, C, and tied to the ground. Accuracy of the OAI gates driving inverter with different inverter ratio of K = 4, 2, and 1 is compared with SPICE with the same designs. Averaged error is within 3% of SPICE for small input slopes and within 10% of SPICE for large input slopes. 79 Figure 5.19 OAI gate driving different inverter loads 5.2.2.1 Model Accuracy of OAI Gate in AMI 0.5μm Process Figure 5.20 Accuracy of the PWL model in OAI gate K = 4 (Wp/Wn = 9.6μm/2.4μm) driving inverter load K=1 in 0.5μm process 80 Figure 5.21 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 4.8μm/2.4μm) driving inverter load K=1 in 0.5μm process Figure 5.22 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 2.4μm/2.4μm) driving inverter load K=1 in 0.5μm process 5.2.2.2 Model Accuracy of OAI Gate in TSMC 0.18μm Process 81 Figure 5.23 Accuracy of the PWL model in OAI gate K = 4 (Wp/Wn = 2.88μm/0.72μm) driving inverter load K= 4 in 0.18μm process Figure 5.24 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 1.44μm/0.72μm) driving inverter load K= 2 in 0.18μm process 82 CHAPTER 6 6.0 CONCLUSION The scaling of semiconductor process technologies has been the fuel that boosts millions of transistors to be incorporated in a single digital integrated circuit, and power dissipation is becoming a critical issue when more transistors are integrated and operated in high frequencies. Unfortunately, as the complexity of integrated circuits increases, simulating circuits with an accurate yet simple transistor model becomes very challenging. In general, lower levels of simulation utilize more detailed transistor model and provide greater accuracy, such as SPICE. However, increased accuracy is usually achieved at the expense of long computation times. This dissertation has proposed a piecewise linear transistor model to evaluate the total power dissipation from the power supply current into the circuits. The piecewise linear model includes the effect of signal input slope into the shortcircuit power and dynamic power computation. The innovation of the model in power evaluation is to include the firstorder channel capacitive currents from the transistor parasitic capacitances into a power calculation. Extensive comparisons have been done between the piecewise linear model and the SPICE BSIM3v3 model in the circuit simulation. The test circuit included an inverter gate, a twoinput NAND gate, and an OAI gate driving different load capacitances. Excellent accuracies of the piecewise linear model have been achieved for the average 83 power predictions under those test circuits for both AMI 0.5μm process and the deep submicron TSMC 0.18μm process. The proposed model has the advantage of simulation speed over SPICE running BSIM3 model, because the piecewise linear model is used to compute the power supply current into a large circuit partitioned into many resistively connected regions with only a few number of transistors and capacitors. Therefore, matrices operation is necessary only when solving the power supply current into the resistively connected nodes from the transistors connected to the power supply. However, simulation speed of the proposed model will be slower than the switchedresistor model in IRSIM since the switchedresistor model has not modeled the transistors in saturation, input slope effects, and accurate circuit dynamics comparable to SPICE’s prediction, but the proposed model will be much accurate than the switched resistor model in a power calculation. 6.1 FINDINGS Simulation inconsistencies were found in SPICE when simulating the average power dissipation by the power supply and simulating average power consumption by the transistor devices in the inverter driving different load capacitances. Discrepancies exist when more complex gates were simulated for average power, such as a twoinput NAND gate and OAI gate driving different loads. The average power provided to the circuit from the power supply is less than the sum of the average power dissipated by every transistor device in the same circuit. The discrepancies of average power from SPICE simulations come from the zeroorder transistor model in SPICE, which computes instantaneous power with the product of the zeroorder instantaneous current and drainsource voltage. 84 Solving the power simulation problem in SPICE requires an energy conserving transistor model, which is beyond the scope of this dissertation. Since the BSIM3v3 model is a well known charge conserving transistor model, accuracies of the proposed model were tested with references to the power supply current entering the circuits or the total average power of the power supply from the SPICE simulation. That is the same approach with the piecewise linear model to evaluate the total average power of a circuit from the power supply current. The piecewise linear approximations of average power to an inverter gate, a twoinput NAND gate and an OAI gate driving different load capacitances with various transistor sizes were validated by comparing the model predicted average power with the average power simulation from the power supply in SPICE, and the accuracies were within 5% average error of SPICE for fast inputs and within 10% for most slow inputs. More complex gates, threeinput OAI gate with different transistor sizes and driving different load conditions in a standard CMOS 0.5μm and 0.18μm technologies, were also verified with the same range of model accuracy. 6.2 FUTURE WORKS The main focus of this dissertation is the accuracy of the simple piecewise linear current transistor model in predicting the average power supply current and power for a standard CMOS circuit. Comprehensive tests are done for simple CMOS circuits to verify the proposed model functionality to compute the switching transient power consumption. However, the gate induced subthreshold leakage current has become a major power dissipation contributor of the total power dissipation, and in many scaled technologies leakage contributes 30% to 50% of the overall power under nominal 85 operating conditions, and leakage is becoming significant compared to switching transient power [38]. Therefore, modeling leakage current is significant for scaled CMOS technologies. The piecewise linear model is applicable for average power evaluation to any general CMOS circuits. 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Benini, “Analysis of glitch power dissipation in CMOS ICs,” IEEE 2000. 90 APPENDICES 91 Appendix A I. AVERAGE POWER SIMULATIONS IN SPECTRE SPICE I.1 SPICE Simulation Inconsistency of Average Power In the SPICE, average power measured from the power supply or from devices is computed from the integration of instantaneous power waveform over one switching cycle. We ran into simulation discrepancies in SPICE between simulating average power dissipation from the power supply and from the transistor devices in the same circuit (Figure A.1 and A.2). SPICE shows that average power dissipation by the devices is higher than the average power actually drawn from the power supply. The discrepancies may come from the zeroorder quasistatic SPICE transistor model, which computes power consumption from a quasistatic zeroorder instantaneous current multiplied by drainsource voltage. Overestimation of average power in SPICE transistor models leads to the issue of nonenergy conserving transistor model in SPICE, which neglects of the firstorder channel capacitive currents. The transistor model (BSIM) and Spectre simulator has the same problem by not taking into account of the firstorder channel capacitive currents into the transistor parasitic capacitances as indicated in HSPICE simulator manual [3]. 92 Average power dissipation simulation from the power supply can be written as equations (I.1), and the average power simulation from devices can be written as equation (I.2). DD 1 T E Pavg ( vd d ) i vd d ( t ) * V ( t )d t T 0 T = ∫ = (I.1) n n Dnn Dnn Dpn Dpn m 1 m 1 1 T 1 T Pavg(device) i (t) *V (t)dt i (t) *V (t)dt T = 0 T = 0 = Σ ∫ + Σ ∫ (I.2) SPICE simulation discrepancies are shown in Figure A.1 and A.2. Figure A.3 and A.4 demonstrate the simulation tool of SPECTRE SPICE in simulating the average power of inverter from the power supply and the transistor devices respectively. Figure A.1 Average Power Simulation of Inverter in SPICE 93 Figure A.2 SPICE power waveform/cycle of Fig.A.1 with 1ns input slope. Dot in red: total device power; solid green line: supply power. Dashdot in blue: the supply current. I.2 SPECTRE SPICE circuit net list for an inverter driving 100fF load simulator lang=spectre model ami06N bsim3v3 type = n +version = 3.1 tnom = 27 tox = 1.41E8 model ami06P bsim3v3 type = p +version = 3.1 tnom = 27 tox = 1.41E8 // Library name: inverter_lib // Cell name: inverter // View name: extracted _inst0 (OUT IN ps pb) ami06P w=9.6e06 l=6e07 as=1.44e11 ad=1.44e11 \ ps=1.26e05 pd=1.26e05 m=1 region=sat _inst1 (OUT IN gnd gnd) ami06N w=2.4e06 l=6e07 as=3.6e12 ad=3.6e12 \ ps=5.4e06 pd=5.4e06 m=1 region=sat _inst2 (OUT gnd) capacitor c=100e15 m=1 // power supplies VPWR(vdd 0) vsource dc=5.0 VGND(gnd 0) vsource dc=0.0 94 // inputs VIN(IN 0) vsource dc=5.0 type=pulse val0=5 val1=0\ period=13n rise=1500p fall=1500p width=5n // current test meter VTEST1(vdd ps) vsource dc=0.0 type=pulse val0=0 val1=0 VTEST2(vdd pb) vsource dc=0.0 type=pulse val0=0 val1=0 opts1 options pwr=total save=all setting1 options save=all opts options currents=all opts2 options pwr=total save=all save _inst0:pwr save _inst1:pwr save VPWR:pwr save VGND:pwr // controls inverter tran step=1p start=0n stop=13n errpreset=conservative save OUT IN I.3 Average Power Simulation in SPECTRE Figure A.3 Average Power Simulation from the Power Supply in SPECTRE 95 Figure A.4 Average Power Simulation from Total Device Power in SPECTRE SPICE 96 Appendix B MODEL PARAMETER EXTRACTIONS FOR AMI 0.5μm AND TSMC 0.18μm PROCESSES I. Model Parameters Extraction The piecewise linear current model has a total of six parameters: an , ap , VTn , Tp V , Gsat , andGohmic . The parameters of a piecewise linear transistor model can be extracted directly from SPICE ID − VGS and ID − VDS curves for transistors used in the circuit. There are many techniques associated with VTn and VTp extractions from transistor I/V curves from [4]. The VTn and VTp in the piecewise linear model are extrapolated from SPICE ID − VGS family curves at the maximum slope of VGS curves to IDS = 0 point. The tangent line across IDS = 0 is the threshold voltage on the VGS curve as shown in Fig.B.1 and Fig. B.2. An averaged VTn and VTp in equation (B.1) are computed from the threshold voltages extrapolated from ID − VGS curves. T1 T2 T3 T4 Tm T V V V V ....V V m + + + = (B.1) Transistor ID − VGS curves are generated in SPICE with BSIM3v3 transistor model in a region of greatest current, for AMIS 0.5μm process, 2.5 < VGS < 5.0 and 2.5 < VDS < 5.0 . 97 The rationale is that most of change of voltage at the output of CMOS circuit is proportional to the output transistor biased in the high current range [39], because the rate of voltage change at the output depends on the magnitude of the current. The modeling errors in regions of low drain current (when the transistor in the ohmic region) usually produce smaller timing errors than errors in regions of high current (when the transistor is in saturation) [39]. Hence, the proposed piecewise linear transistor model uses an average value for each parameter to minimize the timing error in regions of high current as indicated in [39]. Figure B.1 Threshold voltage extraction from high VDSN curves in 0.5μm process Figure B.2 Threshold voltage extraction from low VDSN curves in 0.5μm process 98 The maximum slope of the ID −VGS curve is the large signal transconductance of the transistor G. An averaged transconductance was determined by taking the average slopes from ID −VGS curves at highVDS and low VDS curves. Since five ID −VGS curves were plotted at a high VDS and five ID −VGS curves were plotted for a low VDS , a total of four extrapolated G(N)SAT and G(P)SAT were averaged to obtain an average GNSAT , GPSAT. The conductance at the ohmic region for nFET and pFET devices, G(N)OHM , and G(P)OHM, were derived using the same approach with ID −VDS curves. In this case, the average conductance can be computed as equation (B.3) from ID −VDS curves and as shown in Figure 3.3 and Figure 3.4. Similarly, average transconductance (slopes of curves) can be extracted from ID −VGS curves shown in Figure B.1 and Figure B.2. Gnsat1 Gnsat2 Gnsat4 Gn(p)sat 4 + + + = K (B.2) Gohmic1 Gohmic2 Gohmic4 Gn(p)ohm 4 + + + = K (B.3) Quasistatic dc current scaling factors an and ap for nFET and pFET are computed by Gn(p)ohm an(p) Gn(p)sat = (B.4) Appendix II includes all parameters extracted from SPICE simulations in AMI 0.5μm and TSMC 0.18μm process for the piecewise linear model. 99 The model parameters for the piecewise linear (PWL) model were extracted from I/V family curves of various transistor sizes from the AMI CMOS 0.6um submicron technology and a TSMC 0.18μm deep submicron technology. i. Extracted PWL transistor parameters for AMI 0.5μm process Wp (um) Rsp (Ω/ ) VTp (V) ap 1.2 2.1×104 1.8 1.251763 2.4 2.1×104 1.6 1.396283 4.8 2.1×104 1.49 1.348792 9.6 2.1×104 1.386 1.352994 Table B.1 Falling input PMOS parameters for AMI 0.5μm process Wp (um) Rsp (Ω/ ) VTp (V) ap 1.2 3.3×104 1.292 2.9 2.4 3.3×104 1.241 2.8 4.8 3.3×104 1.243 2.0 9.6 3.3×104 1.161 1.2 Table B.2 Rising input PMOS parameters for AMI 0.5μm process 100 Wn (um) Rsn (Ω/ ) VTn (V) an 1.2 1.7×104 1.34 1.38442 2.4 1.7×104 1.1 1.64235 4.8 1.7×104 0.99 1.03714 9.6 1.7×104 0.96 1.4
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Title  Power Modeling of Cmos Digital Circuits with a Piecewise Linear Model 
Date  20070501 
Author  Liu, Cheng Chih 
Department  Electrical Engineering 
Document Type  
Full Text Type  Open Access 
Abstract  This paper presents the average power modeling of CMOS digital circuits with a piecewise linear (PWL) model. The innovation of the piecewise linear model in the average power evaluation against previous power models is to include, for the first time, the effects of the firstorder channel capacitive currents into a power calculation. Also, the model in the evaluation of the average power supply current predicts the currents contributed to the shortcircuit power, dynamic power, and switching power of parasitic capacitances. A firstorder channel storage charge model is derived to compute the power consumption caused by the nonlinear parasitic capacitances in a transistor channel. The PWL modeling of average power was validated by comparing SPICE average power simulation from the power supply current. The proposed model was validated with a submicron CMOS 0.5μm process and a deep submicron 0.18μm process to test its portability as a technologyindependent model. Findings and conclusions./ The simulation discrepancies were found when the SPICE simulating the average power dissipation from the power supply current and the average power consumed by the devices in the same circuit. The average power consumed by the devices in a circuit is more than provided by the power supply current. The discrepancies come from the zeroorder quasistatic SPICE transistor model, which computes the instantaneous power from the zeroorder quasistatic transistor current and multiplied by its drainsource voltage. It has been well defined that the BSIM is a chargeconserving transistor model, so the average power dissipated by the power supply current into the circuit is the true power in SPICE which was used to test the accuracy of the PWL model. The PWL approximation to the average power of an inverter gate and a twoinput NAND gate with various transistor sizes and loads were within 3 to 5% averaged error of SPICE for fast inputs and within 10% for slow inputs. Complex OAI gates were also verified with the same range of accuracy. 
Note  Dissertation 
Rights  © Oklahoma Agricultural and Mechanical Board of Regents 
Transcript  POWER MODELING OF CMOS DIGITAL CIRCUITS WITH A PIECEWISE LINEAR MODEL By CHENG CHIH LIU Bachelor of Science Pittsburg State University Pittsburg, Kansas 1999 Master of Science Oklahoma State University Stillwater, Oklahoma 2001 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY May, 2007 ii POWER MODELING OF CMOS DIGITAL CIRCUITS WITH A PIECEWISE LINEAR MODEL Dissertation Approved: Dr. Louis G. Johnson Dissertation Adviser Dr. R. G. Ramakumar Dr. Yumin Zhang Dr. H.K. Dai Dr. A. Gordon Emslie Dean of the Graduate College iii ACKNOWLEDGMENTS I would like to express my gratitude to Dr. Louis G. Johnson for his fiveyear guidance and supports for this dissertation. Without his abundant experiences in the area of CMOS integrated circuits, I could not possibly discover this research topic and the theory behind it. Moreover, I am appreciative of his many helpful advices from design to fabrication of a working prototype of analog integrated circuit for neural recoding application. I also would like thank Dr. R.G. Ramakumar, Dr. Yumin Zhang, and Dr. H.K. Dai for their busy time and valuable feedback with their expertise while serving as members in my committee. Their suggestions and ideas helped me complete this dissertation. A special appreciation goes to Jian Chang, now in the Texas Instruments, in my research group for verifying the piecewise linear delay model. I am also thankful to all the members in our digital VLSI research group, and to Sameer, for discussing many questions in an energy conserving MOSFET model. Last but not least; I appreciate my Dad, Mom, brother, and sister for their supports and encouragements. Without their support, I would not be motivated to pursue a doctoral degree. Especially, I am indebted to my wife, ChinHuey, for her unconditional love and supports throughout my school years, and also my children, John and Amy, being good companies during my studies. iv TABLE OF CONTENTS CHAPTER Page 1. INTRODUCTION .....................................................................................................1 1.0 Purpose of the study...........................................................................................1 1.1 Significance of the study....................................................................................2 1.2 Limitation of the proposed model......................................................................3 1.3 Introduction to the CMOS logic families...........................................................3 1.4 Organization.......................................................................................................5 2. CONVENTIONAL TRANSISTOR MODELS FOR POWER EVALUATION......6 2.0 Definition: Energy or Power..............................................................................6 2.1 Sources of CMOS Power dissipation.................................................................7 2.1.1 Offstate leakage power of the transistor ..................................................8 2.1.2 Switching transient power in CMOS transistors.....................................10 2.1.3 Glitch power dissipation in CMOS transistors .......................................15 2.2 Summary..........................................................................................................15 3. A PIECEWISE LINEAR TRANSISTOR MODEL ................................................17 3.0 Background......................................................................................................17 3.1 Evaluation of average power dissipation with the piecewise linear model .....18 3.1.1 Piecewise linear current model ...............................................................20 3.1.2 Channel storage charge model ................................................................24 3.2 Ramp input approximation ..............................................................................31 3.3 Approximate solution for circuit voltage.........................................................33 3.3.1 Resistive connected region .....................................................................33 3.3.2 Approximate solution for circuit voltage with nonsingular G matrix.....34 3.4 Average turnoff energy evaluation with the piecewise linear current model..37 3.4.1 Zeroorder turnoff current in ohmic region ...........................................38 3.4.2 Zeroorder turnoff current in saturation region .....................................39 3.4.3 Zeroorder turnoff current in cutoff region............................................40 3.5 Average turnon energy evaluation with the piecewise linear current model ..40 3.5.1 Zeroorder turnon current in cutoff region ............................................41 3.5.2 Zeroorder turnon current in saturation region ......................................41 3.5.3 Zeroorder turnon current in ohmic region............................................42 3.5.4 Resistive connected region with steady state input.................................42 v 3.5.4.1 Zeroorder turnon current in saturation region .........................42 3.5.4.2 Zeroorder turnon current in ohmic region...............................43 3.6 Switching energy in the Transistor parasitic capacitances ..............................45 3.7 Summary ..........................................................................................................47 4. AVERAGE POWER ANALYSIS OF INVERTER WITH THE PWLMODEL...49 4.0 Introduction......................................................................................................49 4.1 Energy per cycle analysis of inverter driving load capacitance.......................49 4.1.1 Turnoff energy analysis .........................................................................51 4.1.2 Turnon energy analysis..........................................................................53 4.1.3 Switching energy in the transistor parasitic capacitances.......................54 4.2 Energy per cycle calculation............................................................................55 4.2.1 Energy per cycle evaluation from the model .........................................55 4.2.2 Energy per cycle simulation from SPICE..............................................57 4.3 Model accuracy of inverter driving load capacitance ......................................57 4.3.1 Model accuracy in AMI CMOS 0.5μm process .....................................58 4.3.2 Model accuracy in TSMC CMOS 0.18μm process ................................60 4.4 Model accuracy of inverter driving inverter gate load.....................................62 4.4.1 Model accuracy in AMI CMOS 0.5μm process .....................................62 4.4.2 Model accuracy in TSMC CMOS 0.18μm process ................................63 4.5 Summary..........................................................................................................64 5. COMPLEX GATES ANALYSIS WITH A PIECEWISE LINEAR MODEL.....66 5.0 Introduction......................................................................................................66 5.1 Average power analysis of twoinput NAND gate ..........................................66 5.1.1 Twoinput NAND gate driving capacitance load ...................................67 5.1.2 Model accuracy in NAND gate in AMI 0.5μm process .........................68 5.1.3 Model accuracy in NAND gate in TSMC 0.18μm process ....................70 5.2 Average power analysis of OAI gate ...............................................................73 5.2.1 Average power analysis of OAI gate driving capacitance load..............74 5.2.1.1 Accuracy of model in OAI gate in AMI 0.5μm process...................74 5.2.1.2 Model accuracy in OAI gate in TSMC 0.18μm process...................76 5.2.2 Average power analysis of OAI gate driving an inverter load ...............78 5.2.2.1 Model accuracy in OAI gate in AMI 0.5μm process........................79 5.2.2.2 Model accuracy in OAI gate in TSMC 0.18μm process...................81 6. CONCLUSION....................................................................................................82 BIBLIOGRAPHY........................................................................................................86 vi APPENDICES APPENDIX Page A Average power simulation in the SPICE SPECTRE ..............................................91 B Model parameter extractions for AMI 0.5μm and TSMC 0.18μm Process………. .......................................................................................................96 C Coding and implementation ..................................................................................106 vii LIST OF TABLES TABLE Page 1 Linearized parasitic transistor capacitance with overlap capacitance.................29 2 Average power simulation of inverter in Fig.4.5 using PWL model for various input transition time from 1000ps to 20ps ..........................................................56 3 Comparisons of average power predictions in SPICE and PWL model with various input slopes from 1000ps to 90ps...........................................................57 B.1 Falling input PMOS parameters for AMI 0.5μm process ...............................99 B.2 Rising input PMOS parameters for AMI 0.5μm process ................................99 B.3 Falling input NMOS parameters for AMI 0.5μm process ............................100 B.4 Rising input NMOS parameters for AMI 0.5μm process. ............................100 B.5 Falling input PMOS parameters for TSMC 0.18μm process ........................101 B.6 Rising input PMOS parameters for TSMC 0.18μm process.........................101 B.7 Falling input NMOS parameters for TSMC 0.18μm process .......................102 B.8 Rising input NMOS parameters for TSMC 0.18μm process ........................102 viii LIST OF FIGURES FIGURES Page 1.1 CMOS inverter.........................................................................................................4 1.2 CMOS two input NAND gate..................................................................................4 1.3 CMOS OAI gate ......................................................................................................5 2.1 Four terminal MOSFET device and its parasitic capacitances ................................8 2.2 Offstate currents from the transistor gate to its conducting channel. .....................9 2.3 Veendrick’s shortcircuit current model of an inverter without load. ...................13 3.1 Average power measurement from the power supply current ...............................20 3.2 Transistor switchlevel models in ohmic, saturation, and cutoff region................21 3.3 Accuracy of the PWL switching current model for 2.4μm/0.6μm nFET. .............23 3.4 Accuracy of the PWL switching current model for 4.8um/0.6um pFET...............23 3.5 Sign convention for zeroorder piecewise linear switching current ......................24 3.6 Channel storage charge model ...............................................................................25 3.7 Sign convention for channel capacitive currents in transistors..............................26 3.8 Gate overlap capacitances for FETs ......................................................................30 3.9 Input ramp approximation......................................................................................31 3.10 Piecewise linear approximation of input ramps in resistance connected region .32 3.11 Notation of transistor number ‘m’ and circuit node names .................................34 4.1 Inverter driving load capacitance with rising input ramp approximation..............50 4.2 Inverter transient analysis with boundaries and operation regions with rising input ramp approximation....................................................................51 4.3 Inverter driving load capacitance with falling input ramp approximation ............53 4.4 Inverter transient analysis with boundaries and operation regions with falling input ramp approximation ..................................................................53 4.5 Average power calculation by the model for TSMC 0.18μm process...................56 4.6 Accuracy of the PWL model in inverter (K = 4, 0.5μm) driving 100fF load........59 4.7 Accuracy of the PWL model in inverter (K = 2, 0.5μm) driving 100fF load........59 4.8 Accuracy of the PWL model in inverter (K = 1, 0.5μm) driving 100fF load........60 4.9 Accuracy of the PWL model in inverter (K = 4, 0.18μm) driving 100fF load......60 4.10 Accuracy of the PWL model in inverter (K = 2, 0.18μm) driving 100fF load ....61 4.11 Inverter driving gate load capacitance .................................................................62 4.12 Accuracy of the PWL model in inverter (K = 2, 0.5μm) driving inverter load ...62 4.13 Accuracy of the PWL model in inverter (K = 1, 0.5μm) driving inverter load ...63 ix 4.14 Accuracy of the PWL model in inverter (K = 4, 0.18μm) driving inverter load .63 4.15 Accuracy of the PWL model in inverter (K = 2, 0.18μm) driving inverter load .64 4.16 Accuracy of the PWL model in inverter (K = 1, 0.18μm) driving inverter load .64 5.1 Twoinput NAND driving load capacitance .........................................................67 5.2 Accuracy of the PWL model in twoinput NAND gate (K = 4, 0.5μm) driving 100fF load ..............................................................................................................68 5.3 Accuracy of the PWL model in twoinput NAND gate (K = 2, 0.5μm) driving 100fF load ..............................................................................................................69 5.4 Accuracy of the PWL model in twoinput NAND gate (K = 2, 0.5μm) driving inverter gate load....................................................................................................69 5.5 Accuracy of the PWL model in twoinput NAND gate (K = 1, 0.5μm) driving inverter gate load....................................................................................................70 5.6 Accuracy of the PWL model in twoinput NAND gate (K = 4, 0.18μm) driving 100fF load ..............................................................................................................70 5.7 Accuracy of the PWL model in twoinput NAND gate (K = 2, 0.18μm) driving 100fF load ..............................................................................................................71 5.8 Accuracy of the PWL model in twoinput NAND gate (K = 1, 0.18μm) driving 100fF load ..............................................................................................................71 5.9 Accuracy of the PWL model in twoinput NAND gates (K = 4, 0.18μm) driving inverter gate load....................................................................................................72 5.10 Accuracy of PWL model for a twoinput NAND gate (K = 2, 0.18μm) driving inverter gate load..................................................................................................72 5.11 Accuracy of the PWL model in twoinput NAND gate (K = 1, 0.18μm) driving inverter gate load..................................................................................................73 5.12 OAI Gates driving a 100fF Load .........................................................................74 5.13 Accuracy of the PWL model in OAI gate (K = 4, 0.5μm) driving 100fF load....75 5.14 Accuracy of the PWL model in OAI gate (K = 2, 0.5μm) driving 100fF load....75 5.15 Accuracy of the PWL model in OAI gate (K = 1, 0.5μm) driving 100fF load....76 5.16 Accuracy of the PWL model in OAI gate (K = 1, 0.18μm) driving 100fF load..77 5.17 Accuracy of the PWL model in OAI gate (K = 2, 0.18μm) driving100fF load...77 5.18 Accuracy of the PWL model in OAI gate (K = 1, 0.18μm) driving100fF load...78 5.19 OAI gate driving different inverter gate loads.....................................................79 5.20 Accuracy of the PWL model in OAI gate (K = 4, 0.5μm) driving inverter.........79 5.21 Accuracy of the PWL model in OAI gate (K = 2, 0.5μm) driving inverter.........80 5.22 Accuracy of the PWL model in OAI gate (K = 1, 0.5μm) driving inverter.........80 5.23 Accuracy of the PWL model in OAI gate (K = 4, 0.18μm) driving inverter.......81 5.24 Accuracy of the PWL model in OAI gate (K = 2, 0.18μm) driving inverter ......81 A.1 Average power simulation of inverter in SPICE ..................................................92 A.2 SPICE power waveform/cycle with 1ns input slope: dot in red: total device power; solid green line: supply power dashdot in blue: supply current. ...........93 A.3 Average power simulation in power supply in SPECTRE ...................................94 A.4 Average device power simulation in SPECTRE...................................................95 B.1 Threshold voltage extraction from high VDSN curves in 0.5μm process ...............97 x B.2 Threshold voltage extraction from low VDSN curves in 0.5μm process ................97 B.3 Transistor diffusion capacitance model...............................................................103 B.4 Source junction capacitance versus body bias ....................................................104 xi LIST OF PHYSICAL CONSTANTS AND PROCESS PARAMETERS ε0 = 8.85 10 14 Fm × − ox ε = 3.97 for silicon dioxide k = 0 1.3803 10 23 Joule K × − kT = 4.1409 × 10−21 Joule for room temp. at 270 q = 1.6 × 10−19 Coulomb Cox = ox 0 tox ε ⋅ε = 11 ox 3.51 10 Fm (for the gate oxide on silicon) t (m) × − n β = μn ⋅Cox p β = μp ⋅Cox xii LIST OF SYMBOLS Symbol Meaning Unit an Ratio of conductance and transconductance for the nMOS transistor ap Ratio of conductance and transconductance for the pMOS transistor β Effective transistor strength A.V2 C Capacitance matrix F Cd Depletion layer capacitance F GG C Linearized parasitic capacitance on the gate of the transistor F GS C Linearized parasitic capacitance on the gatesource of the transistor F Cgdo Voltage independent gatedrain overlap capacitance per unit gate width F.m1 Cgso Voltage independent gatesource overlap capacitance per unit gate width F.m1 OX C Oxide capacitance per unit area F.m2 EIvdd Energy dissipation due to the shortcircuit current and dynamic current J Eivdd Energy dissipation due to the firstorder channel capacitive currents J Gm Conductance of the mth transistor S G Conductance matrix S E T Energy dissipation per switching cycle J/S 0 ε Permittivity of vacuum F.m1 ox ε Relative permittivity of oxide Ivdd Zeroorder power supply current in the piecewise linear transistor model A ivdd Firstorder power supply current in the piecewise linear transistor model A ISm Zeroorder piecewise linear switching source current of the mth transistor A iSm Firstorder piecewise linear switching source current of the mth transistor A IDm Zeroorder piecewise linear switching drain current of the mth transistor A iDm Firstorder piecewise linear switching drain current of the mth transistor A ISC Shortcircuit current A xiii k Boltzman’s constant J.K1 τ Delay time second or s r τ Delay time for rising signal second or s f τ Delay time for falling signal second or s n μ Channel electron mobility m2 V1 s1 P μ Channel hole mobility m2 V1 s1 Pavg Average power dissipation W Pdynamic Dynamic power dissipation W PSC Short circuit power dissipation W POFF Offstate leakage power dissipation W T I Zeroorder quasistatic current in the transistor channel A iT Firstorder quasistatic current in the transistor channel A DS V sat Drainsource saturation voltage of the transistor V T V Transistor threshold voltage V V% Approximated output voltage in the steady state V V&% Firstorder terms for the approximated output voltage V V&%& Secondorder terms for the approximated output voltage V V Output voltage of the resistive connected node V S Subthreshold slope mV/decade TTin Input transition time s tox Gate oxide thickness m xPart Parameter for the channel charge partition φB Builtin potential of the bottom wall junction capacitance V φBSW Builtin potential of the isolation side sidewall junction capacitance V φBSWG Builtin potential of the gate side sidewall junction capacitance V 1 CHAPTER 1 INTRODUCTION 1.0 Purpose of the Study Power dissipation is one of the major concerns for high speed very large scale integrated circuits (VLSI) design. Power dissipative components in CMOS circuits consist of offstate leakage power, glitch power, and switching transient power. This paper presents a piecewise linear modeling of switching transient power of CMOS digital circuits, which includes the shortcircuit power, dynamic power, and switching power of parasitic capacitors. The piecewise linear power model takes a simplified approach to compute average power (or energy per cycle) without solving differential equations with large matrices. Even thought SPICE (Stanford Program for Integrated Circuit Emulation) can handle the accurate and nonlinear behaviors of transistors with more than one hundred fitting parameters, it usually takes a great amount of computation time for a large circuit simulation. Another competing circuit simulator is the switch level simulator, IRSIM, which is a tool for simulating digital circuits. It is a switchlevel simulator, because the transistors are treated as ideal switches, and the extracted capacitances and resistances are used to find the RC time constants for the ideal switches 2 to predict the relative timing events [34]. Thus, it is an ideal transistor model, and is not accurate in computing transient switching power. The proposed piecewise linear model, as an improved switch resistor model, closes the performance gap between SPICE and switchlevel simulators in power estimation. 1.1 Significance of the Study Dynamic power dissipation is well known and defined for CMOS digital circuits. Analytical works, more recently, for power modeling are focused on shortcircuit power modeling with slope effects, velocity saturation and gatetodrain capacitive coupling effects, propagation delay and short channel effects. Analytical works in offstate leakage power modeling are also popular as the transistor size shrinks into the deep submicron realm. However, channel capacitive currents induced power dissipation is not addressed in other transistor models [4] [6] [7] [13]. Therefore, the proposed piecewise linear model not only includes the firstorder capacitive currents but also takes into account the effect of the slope of the input waveform in average power estimation. Most fast simulators [34] [39] assume a step input, so that the piecewise linear model is at least an improved yet simplified nonlinear transistor model to replace the traditional resistor model in fast simulators. The piecewise linear model is verified in the submicron AMI CMOS 0.5μm and deep submicron TSMC 0.18μm process. 3 1.2 Limitation of the Piecewise Linear Model The model is constructed with IV and CV models approximating the complex BSIM (Berkeley ShortChannel Insulated gate field effect transistor Model) model [4] for CMOS transistors as switches. The current–voltage (I–V) model describes the zero–order (dc) behavior of a quasistatic current between the source and drain terminals, and the capacitance–voltage (C–V) model describes the firstorder dynamic behavior of channel capacitive currents associated with transistor parasitic capacitances. The piecewise linear I–V model approximates the physical transistor current with different piecewise linear regions in cutoff, ohmic, and saturation. The proposed model shows that its accuracy is within 3 to 5 % of SPICE for fast inputs in AMI 0.5μm and TSMC 0.18μm processes, and the accuracy may reach 15 to 20 % error for input transition times greater than 2000 picosecond in AMI 0.5μm process and 1000 picosecond in TSMC 0.18μm process. However, very slow input occurs not very often in submicron technologies and can usually be speeded up with circuit design techniques. 1.3 Introduction to the CMOS logic families 1) Standard CMOS logic gates A standard CMOS logic gate has the same number of pFETs and nFETs with the transistors connected in a complementary manner. A standard CMOS inverter, NAND, and NOR may be designed with different sizes to meet speed and power requirements. Most power dissipation of CMOS circuits comes from the switching transient power, which includes the shortcircuit power, and dynamic power. A piecewise linear model to calculate the average power dissipation of a CMOS inverter (Fig.1.1), a twoinput NAND 4 gate (Fig.1.2), and a threeinput OAI (OrAndInvert) digital circuit (Fig.1.3) driving a constant capacitor or driving various sizes of inverter loads, are chosen to compare modeling accuracy with the average power of the power supply as predicted by SPICE. Figure 1.1 CMOS inverter Figure 1.2 CMOS two input NAND gate 5 Figure 1.3 CMOS OAI gate 1.4 Organization In chapter two, conventional power models are introduced along with literature reviews of offstate leakage power, short circuit power, glitch power, and dynamic power models. In chapter three, the piecewise linear switching current–voltage (IV) model and channel storage charge or channel capacitance–voltage (CV) model are introduced. IV and CV models in the piecewise linear model are used to demonstrate the model in computing average power from the power supply currents. In chapter four, computing average power with the piecewise linear model is coded in C++ language for an inverter. In chapter five, more complex circuits are chosen. Average power evaluations for twoinput NAND and OrAndInverter (OAI) with various transistor sizes and loads are presented. Findings and conclusion are presented in chapter six. 6 CHAPTER 2 CONVENTIONAL TRANSISTOR MODELS FOR POWER ESTIMATION 2.0 Definitions: Energy or Power The use of power as a performance measure is often misleading. In battery operated devices, the amount of energy needed for operations may be a more useful measure because a battery stores a finite amount of energy, not power [35]. Energy per operation or average power is often used to evaluate energy efficiency of CMOS circuits. Definition of instantaneous power and average power (or energy per cycle), is summarized as follows. The instantaneous power P(t) is proportional to the power supply current Ivdd(t) and the supply voltage [8], which is written as P(t) = Ivdd (t) ⋅Vdd (2.1) The average power dissipation Pavg is defined as an integration of instantaneous power P(t) over some time interval T. Also, the average power dissipation is equivalent to the energy consumed over some interval T [8] and is written as T dd 0 P 1 I ( t ) V d t E avg T vd d T = ∫ ⋅ = (2.2) Energy ‘E’ is calculated from the integration of instantaneous power supply current during the period when the instantaneous power supply current enters the circuit [8]. 7 2.1 Sources of CMOS Power Dissipation Transistor dissipative power is mainly due to the currents from the channel inversion layer traveling in a resistive channel between source and drain terminals. Unfortunately, the power supply current into the transistor channel is a nonlinear function of terminal voltages. Transistor channel currents are, in fact, spaceaveraged quasistatic currents in the channel [6], which includes the voltagedependent quasistatic current component and a timevarying charging current component [25]. Conventional transistor models [25] show that quasistatic currents in the channel consist of the following components. IT = hT (VD,VG ,VB,VS) (2.3) iT (t) = hT (vD(t), vG (t),vB(t), vS (t)) (2.4) The channel current IT expressed in (2.3) is a function of the terminal voltage on the gate, source, drain, and substrate of the transistor [25] without timevarying voltages. Thus, the expression for IT is, in fact, a zeroorder quasistatic DC model. Channel capacitive currents which are equivalent to “charging currents” [25] in (2.4) are function of the time derivatives of the channel charge storage, which depends on the timevarying voltages associated with each terminal [25] [33], therefore, it is the firstorder quasistatic capacitive currents associated with voltagedependent parasitic capacitances. Figure 2.1 illustrates the FET device with parasitic capacitances. Five distinct types of transistor current contribute to the power dissipation of a CMOS circuit. 8 Figure 2.1 Four terminal MOSFET device and its parasitic capacitances I. Transistor offstate subthreshold leakage currents II. Switching transient currents, which include 1) Load capacitor charge and discharge through pFET and nFET network. 2) Shortcircuit current conduction between the power and ground nodes through both FET’s simultaneously. III. Channel capacitive currents due to switching transistors IV. Glitch currents due to unequal arrival of signals to the circuit. 2.1.1 OffState Leakage Power of the Transistor For CMOS logic families and memory circuits, the performance factors include the ratio of offstate leakage current (subthreshold conduction current) to turnon current (IOFF / ION), power, delay, and reliability [15]. Leakage current comes from gate, source, and drain terminals. Gate leakage occurs due to the scaling of gate oxide thickness and the resulting tunneling current from the gate to channel in the transistor as illustrated in Figure 2.2. A study [15] has shown that the gate oxide thickness TOX can be thinned down to 2nm before the leakage current becomes unacceptable for CMOS circuits. 9 Figure 2.2 Offstate currents from the transistor gate to its conducting channel The other concern for scaling oxide thickness thinner than 2 nm is that threshold voltage VT can not be scaled down proportionally with the channel length. The primary barrier is a leakage current dependent subthreshold slope, S, which is a measure of transistor turnoff rate from the gate voltage versus subthreshold leakage current. S should be small in order to reduce leakage current. The subthreshold slope is written as 1 D DS G OXIDE d ln10(kT) C S ( (log I )) (1 ) dV q C ≅ ⋅ − = + (2.5) where q denotes the electron charge, k = 1.38•1023 (J/K) Boltzmanns constant, T the absolute temperature in Kelvin, CD the incremental capacitance of the depletion layer per unit area, and COXIDE is the capacitance of the gate oxide per unit area. The depletion capacitance is a nonlinear function of the gate to bulk voltage. When VGB increases, the value of CD/COXIDE may become negligible. In other words, the subthreshold slope is largely driven by thermally excited electrons in the channel and has no physical controllability from the manufacturing process. Even though CMOS scaling causes offstate power to increase, a study has shown that the offstate power is 0.01% of active power dissipation in a 1um process while 10% in a 0.1um process [15]. Although offstate power is not included in the piecewise linear approximation in this research, the simple offstate transistor power from equation (2.6) [15] can be approximated with the 10 currents of the transistors connected to the power supply for each piecewise linear region of operation, where WTOTAL is the total turnedoff transistors width with VDD across them, and I0 is the parameter for offstate current per device width, and VT is the worse case threshold voltage. OFF TOTAL DD 0 qV P W V I exp( T ) kT − ≅ ⋅ ⋅ ⋅ (2.6) 2.1.2 Switching Transient Power in CMOS Transistors There are two components to the switching transient power: dynamic power dissipation and shortcircuit power dissipation [8] [28], and the models are reviewed as follows. 1. Dynamic Power Dissipation in CMOS Transistors Dynamic switching power occurs when the pFETs connected to the power supply turns on and a direct current path is established from the power supply to load capacitances. For standard CMOS circuits, the dynamic current consumption is dominated by the power supply current necessary to charge up node capacitances, and the dynamic power consumption Pdynamic is proportional to the power supply current and the square of the supply voltage [8]. Pdynamic is expressed as (2.7) [28]. SW SW SW SW T dynamic vdd sw 0 T 2 T Dp DSp Dn DSn sw 0 sw T 2 P 1 i (t)v(t)dt T 1 I V dt 1 I V dt T T = = + ∫ ∫ ∫ (2.7) 11 where out Dp load dV I C dt = − (2.8) VDSp = −(Vdd − Vout ) (2.9) out Dn load dV I C dt = − (2.10) VDS n = Vo u t (2.11) Therefore, average dynamic power is the sum of power computed from the power supply current charging the load capacitance by the pullup pFET network and discharging the same current by the pulldown nFET network for the second half of cycle. Such that, SW SW SW dd dd T 2 T out out dynamic load dd out load sw 0 sw T 2 V 0 load dd out out load out out sw 0 sw V load 2 dd sw 1 dV 1 dV P C (V V )dt C dt T dt T dt 1 C (V V )dV 1 C V dV T T C V T = − + − = − + − = ∫ ∫ ∫ ∫ (2.12) For a general circuit topology with transistors and capacitors only, total dynamic power dissipation is often computed for switching of all of the nodes according to the switching activity (αi ) at the ith capacitive node within a circuit, such that 1 0 N t t 2 dynamic i i i i sw i 1 P 1 C (V V ) T = = Σα ⋅ ⋅ − (2.13) Dynamic power dissipation assumes that t0 Vi , Vit1 are full swing signal between ground and Vdd during a complete chargedischarge cycle. Since most gates do not switch every 12 clock cycle, it is convenient to write the switching frequency as switching activity factor times the clock frequency fsw [8]. N N 2 2 dynamic dd i i sw dd i i sw i 1 i 1 P 1 V C f V C T = = = ⋅ ⋅Σ ⋅α = ⋅ ⋅Σ ⋅α (2.14) 2. Short Circuit Power Dissipation in CMOS Transistors Shortcircuit power is usually neglected in power calculations by switchlevel simulators [34] [39], which often assume a step input response for fast simulation. Due to the intrinsic resistance and parasitic capacitances in a transistor channel, any transistor circuit takes a finite time to rise or fall to its final value at any given node. Therefore, real circuits are usually driven by input with a finite transition time, and consequently, shortcircuit power can be as significant as the dynamic power [17] and cannot be neglected in power calculation. The short circuit power dissipation component is proportional to the input transition time and the load capacitance when a direct current path is established between the power supply and ground. Evaluation of the short circuit power component requires information about input transition times (input rise and fall times), transistor sizes, and the load driven by the circuit. There are many analytical evaluations of the shortcircuit power dissipation component for a simple inverter gate [17], [18], [19], and [20]. The first closedform expression for the shortcircuit power component for a CMOS inverter without load capacitor was from Veendrick in 1984 [17] [23]. The shortcircuit power expression Veendrick derived assumed that the shortcircuit current was symmetric for each input transition with a matched transistor’s mobility and threshold voltage, with equal input rise and fall time τ in a periodic signal T as shown in Fig. 2.4. 13 Figure 2.3 Veendrick’s shortcircuit current model of an inverter without load Under Veendrick’s assumption, shortcircuit current component in an inverter was approximated by transistors in the saturation, such that 2 I (VIN VT ) 2 β = − 0 ≤ I ≤ ISC MAX (2.15) Since the inverter is symmetric about t2, ISC MAX occurs at half of the supply voltage. The mean short circuit current is determined by integrating the instantaneous current from 0 to time T and divided by T. 2 T is the average number of transition per second. T 2 MEAN 0 DD 2 DD T t2 IN T t1 t2 T t1 I 1 I(t)dt 2 2 1 (V (t) V ) dt T T 2 2 2 (V t V ) d(V t V ) T 2 = = β − β = − − τ τ ∫ ∫ ∫ DD T DD 1 (V 2V )3 12 V T β τ = − ⋅ (2.16) where β = βP = β N 14 τr = τf = τ VTn = −  VTp  = VT DD IN T 1 DD 2 V (t) V t t V V t 2 = τ = ⋅τ τ = Therefore, following is the shortcircuit power of a CMOS inverter with no load capacitance: SC DD T P (V 2 V )3 12 T β τ = − ⋅ ⋅ (2.17) The short circuit power expression (2.17) was solved as a function of the input rising and falling transition time (τ) without a load capacitance, and the result may lead to a pessimistic prediction of the shortcircuit power dissipation, because Veendrick’s short circuit power model assumed transistors operated in saturation region only, which cannot accurately predict shortcircuit current as transistors in ohmic region. However, formula (2.17) clearly illustrates that the shortcircuit power is proportional to design parameters β and input transition times (τ) of an inverter’s input signal. For an inverter with a load capacitance, the transistor β values are determined by the required output rise and fall times [8]. Therefore, dependency of shortcircuit power on the input rise and fall times is still valid when an inverter drives a load capacitance. More recently (1996), a closed form expression presented by Bisdounis et al. for shortcircuit power dissipation was based on an output waveform expression with a squarelaw current transistor model [17]. Instead of using a squarelaw current model, Sakurai and Newton [22] suggested an αpower 15 model for the evaluation of shortcircuit power dissipation component. Afterward, Vemuru and Scheinberg [23] developed a shortcircuit power equation by adopting Sakurai and Newton’s αpower MOS model. αpower model and the square law model were proved to be fairly accurate power models, but implementing the higherorder current model takes a fairly large computation time. Hirata, A., et al., [24] reported a piecewise linear function for the shortcircuit power dissipation component in an inverter, but the model can not be extended to predict shortcircuit power for other circuit topologies. 2.1.3 Glitch Power Dissipation in CMOS Transistors It is well known that dynamic power dissipation is directly related to the number of signal transitions in full swing, but spurious transitions (or glitches) caused by unequal arrivals of propagation delays of input signals to the gate often occur in many static ICs [42]. Glitch power is often modeled by using the dynamic power dissipation model as equation (2.13) where t1 t0 (Vi − Vi ) is the incomplete transition during a complete chargedischarge cycle [40] [41] [42]. Power estimation tools can simulate glitches at the gate level for medium size circuits, but the accuracy of glitch power predictions for large circuits is inadequate [42]. 2.2 Summary Modeling average power dissipation in CMOS circuits, at least, should include the following components for CMOS technologies. 16 I. Shortcircuit power. II. Dynamic power. III. Switching power of parasitic capacitances. Not all transistor models are capable of computing each power dissipation component. For instance, the switchresistor model in IRSIM [13] [39] simulator can evaluate dynamic power dissipation only. Surprisingly, the HSPICE simulator, one of the most accurate SPICE circuit simulators, does not include the power dissipation caused by nonlinear parasitic capacitors [3]. Many researchers [19] [20] [22] [23] [24] [31] extend the αpower model to compute shortcircuit power dissipation component, but none of the models has addressed the significance of channel capacitive currents in a power evaluation. Besides, the αpower model usually has a noninteger value for α, which is not efficient enough to be implemented in a fast simulator. The main difference of the proposed piecewise linear model from previous models in the literature is to compute the average power supply current provided to the circuit instead of evaluating individual power dissipative components for each transistor. In order to compute average power from the power supply current, including channel capacitive currents for a fast simulator, an efficient yet simple transistor model is essential. A simplified (piecewise linear) zeroorder quasistatic switching current model and channel storage charge model are developed to serve the goal and are presented in the following chapter. 17 CHAPTER 3 A PIECEWISE LINEAR TRANSISTOR MODEL 3.0 Background The circuit simulator, SPICE, was designed primarily to evaluate circuit performance during the explosive growth of integrated circuits in the late 1960’s and early 1970’s [38]. A fast simulator, RSIM, was built in the late 1980’s and early 1990’ became competitive with SPICE for its efficiency but not accuracy in simulating large integrated circuits [39]. The RSIM is a switchlevel simulator with speedups of over three orders of magnitude over SPICE [13] [39]. Unfortunately, the switchedresistor model used by RSIM renders it incapable of simulating certain CMOS digital circuits [39] and does not compute power dissipation components other than dynamic power [34]. More recently, a piecewise linear gate modeling of CMOS circuits [36] has improved the switchedresistor model by incorporating a piecewise linear saturation current model and the effects of shortcircuit current and channel capacitive currents into gate delay modeling. Also, the model with a fast algorithm for circuit dynamic analysis can predict gate delay within 10% average error of SPICE regardless of circuit topologies [36]. The goal of this research is to extend the same piecewise linear model to compute average power dissipation in CMOS circuits by evaluating average power supply current. The piecewise linear switching current model and part of the circuit dynamic analysis [36] are reviewed in the following section as an essential step to power estimation. 18 3.1 Evaluation of Average Power Dissipation with the Piecewise Linear Model Rather than attempting to evaluate instantaneous power from each transistor device for each power dissipation component described at the end of chapter two, the proposed piecewise linear model evaluates average power by evaluating average power supply current from transistor(s) connected to the power supply. With the zeroorder switching currentvoltage (IV) model and the channel charge storage or capacitancevoltage (CV) model introduced in the following section, the average power from the power supply current is evaluated instead of evaluating each transistor with instantaneous current and voltage as functions of time. During switching transients that turn off transistors connected to the power supply, only shortcircuit current is included in Ivdd(t) calculation because the discharging current for the node capacitance flows through the turnon nFET network. In contrast, the sum of the dynamic current and the shortcircuit current is included in Ivdd(t) calculation when the transistors connected to the power supply turn on, because the charging current from the power supply for the node capacitance flows through the turnedon pFET network and the shortcircuit current from the turningoff nFET network flows simultaneously. The switching power of any implicit parasitic capacitance is estimated from ivdd(t) with the channel storage charge (CV) model. The power supply current is, in fact, the sum of the currents of every transistor and any explicit capacitance that is directly connected to the power supply. The instantaneous power, P(t) , in (2.1) is rewritten as (3.1) for the average power evaluation from the piecewise linear model (3.2). P(t) = ⎡⎣Ivdd (t) + ivdd (t)⎤⎦ ⋅Vdd (3.1) 19 T 0 P 1 I ( t ) i ( t ) d t E avg T vd d vd d T = ∫ ⎡⎣ + ⎤⎦ = (3.2) The notation Ivdd is used to indicate the power supply current which contributes power dissipation due to the shortcircuit current and dynamic current in CMOS circuits [10]. ivdd will be used to indicate the power supply current which comes from the firstorder switching power due to any implicit parasitic capacitance from transistors connected to the power supply. Ivdd (t) is evaluated by the model from the sum of each individual transistor source current Sm I , which represents the shortcircuit current (or turnoff current) during input (0→1) transitions and also represents the power supply current required to charge the node capacitance (or turnon current). Whereas ivdd(t) is estimated from the sum of the individual channel capacitive currents, Sm i , of each switching transistor connected to the power supply. The subscript stands for the source terminal of mth transistor(s) connected to the power supply. The turnoff current and turnon current will be used throughout the paper when the average power supply current is approximated with the piecewise linear model in each switching cycle. The method of computing average power dissipation can be extended for any multistage circuit that is partitioned into individual subcircuit as shown in Figure 3.1. 20 Figure 3.1 Evaluation of average power from the power supply current 3.1.1 Piecewise Linear Switching Current Model The piecewise linear model for transistor switching is a voltage controlled switch with a series resistance. The simple linear model simplifies the circuit dynamics once the switches have reached their final states. Although the switched resistor model [13] has been used very successfully in circuit simulation [39], it is not adequate to describe the finite time required to switch the transistors on to off. Also, the saturation behavior of the transistors has a significant impact on the switching waveform and average power evaluation. Unfortunately, there is no linear model that can include cutoff, ohmic, and saturation behaviors simultaneously. Complex transistor behavior is simplified to three piecewise linear regions of operation as shown in Figure 3.2. The piecewise linear model is as follows. 21 Figure 3.2 Transistor switch models in ohmic, saturation, and cutoff region respectively The zeroorder quasistatic switching current denoted as IDm and ISm (Fig. 3.2) for the drain and source terminal of the mth transistor connected to the power supply and has the following properties. IDm = −ISm (3.3) IGm = IBm = 0 (3.4) Equations (3.4) assumes that there is no leakage current flowing through the substrate and gate. Therefore, zeroorder quasistatic switching current has the following definitions in the cutoff, ohmic and saturation region for the nFET and pFET transistor in (3.5) and (3.6). m m Dm GSN Tn GSN Tn Dm DSN GSN Tn DSN DSsatn DS Dm GSN Tn GSN Tn DSN DSsatn I (off ) 0, V V (a G V ) , V V ,V V V V I (ohmic) n ,V satn a n I (sat) [G (V V )] ,V V ,V V ⎛ ⎞ ⎛ < ⎞ ⎜ ⎟ ⎜ ⎟ − ⎜ ⎟ = ⎜ ⋅ ⋅ > < ⎟ = ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ⋅ − > > ⎠ ⎝ ⎠ (3.5) 22 m m Dm GSP Tp GSP Tp Dm DSP GSP Tp DSP DS DS Dm GSP Tp GSP Tp DSP DS I (off ) 0, V V (a G V ) , V V ,V V V V I (ohmic) p satp ,V satp ap I (sat) [G (V V )] ,V V ,V V satp ⎛ ⎞ ⎛ > ⎞ ⎜ ⎟ ⎜ ⎟ − ⎜ ⎟ = ⎜ ⋅ ⋅ < > ⎟ = ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⋅ − < < ⎟ ⎝ ⎠⎝ ⎠ (3.6) Gnohmic a n GnSat a p Gpohmic GpSat ⎛ ⎞ ⎜ ⎟ ⎛ ⎞ ⎜ ⎟ ⎜ ⎟ = ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ (3.7) (aP ⋅G)m is the conductance of the mth pFET transistor in the ohmic region and the Gm is the transconductance of the mth transistor in the saturation region. The sign of transistor current at the drain given by (3.5) and (3.6) is determined by the terminal voltages of the transistor. Current going into a terminal indicates a positive drain current and negative current if the current exits from the terminal. an , ap,VTn , and VTp are process constants and process dependent variables. All parameters are positive except the threshold voltage VTp . an , ap are greater than one. Conductance of the pFET and nFET transistor for Gohmic and Gsat are determined from average sheet resistance extrapolated from I/V curves from the transistors used in the test circuits. The piecewise linear model is a reasonably good approximation to current in saturation, and less accurate for current in the ohmic region as shown in Fig 3.3 and 3.4 when comparing the piecewise linear switching currents with SPICE simulation. However, as illustrated in [39], modeling errors in regions of low drain current usually produce smaller timing errors than errors in regions of high drain current. Therefore, the current mismatch errors in regions of low drain current is not critical for the timing accuracy of the piecewise linear transistor model. Furthermore, additional accuracy for the low drain current can be obtained by adding more piecewise linear regions to better approximate the transistor current in the 23 ohmic region, but adding more regions to the model makes solving for circuit dynamics more timeconsuming because the node voltage must be checked at each moment in time to decide which piecewise linear model to use for each transistor in a circuit. The piecewise model is at least a more accurate switching current model than the traditional switched resistor model [13]. Figure 3.3 Accuracy of the piecewise linear switching current model for 2.4μm/0.6μm nFET Figure 3.4 Accuracy of the piecewise linear switching current model for 4.8μm/0.6μm pFET 24 As illustrated in Figure 3.1, the averaged power dissipation is computed from the sum of the switching current of every pFET connected to the power supply. Figure 3.5 illustrates the sign convention for the zeroorder quasistatic switching current component into the transistors. The firstorder channel capacitive currents into the transistor(s) connected to the power supply are evaluated separately by the channel storage charge model presented in the following section. Figure 3.5 Sign convention for zeroorder switching in transistors 3.1.2 Channel Storage Charge Model Besides the zeroorder quasistatic switching current in the transistor channel, channel currents also contain a firstorder channel capacitive current, which come from the channel charge stored in the nonlinear parasitic capacitances. Channel capacitive currents are denoted as iD, iS, iG, and iB in order to differentiate from the zeroorder quasistatic switching current for ID, IS, IG, and IB. Most transistor models [4] [5] [7] [26] are 25 not energy conserving due to the neglect of the firstorder channel capacitive currents when calculating power consumption [37], and therefore, parasitic capacitances of the transistor are treated as normal capacitors, which do not dissipate power. Particularly, a SPICE simulator assumes that parasitic capacitors are normal capacitors in nature and do not include them in a power calculation [3]. In order to correct the problem by including the nonlinear channel capacitive currents in a power calculation, the channel storage charge is partitioned as seen in Figure 3.6 between the source and drain to obtain a simple lumped parameter model for the dynamic behavior of the transistor. Charge conservation requires that the total channel charge to be conserved, such that Figure 3.6 Channel storage charge model QG = −(QS + QD + QB) (3.8) It should be emphasized that these are not linear capacitances since the charges are functions of all of the transistor terminal voltages. Channel capacitive currents can be written in terms of time derivatives of the channel storage charge on each transistor terminal. It is convenient to use these equations written in terms of the individual terminal voltages G V , S V , D V , and B V . G G S D B G GG GS GD GB i dQ C dV C dV C dV C dV dt dt dt dt dt = = − − − (3.9) S G S D B S SG SS SD SB i dQ C dV C dV C dV C dV dt dt dt dt dt = =− + − − (3.10) 26 dQD dVG dVS dVD dVB iD CDG CDS CDD CDB dt dt dt dt dt = =− − + − (3.11) iB = −(iG + iS + iD ) (3.12) Cij (i ≠ j) are all nonlinear capacitors and functions of the terminal voltages given by i ij ij C Q i, j G,D,S,B V ∂ = = ∂ (3.13) where CGG = CGS + CGD + CGB (3.14) CSS = CSG + CSD + CSB (3.15) CDD = CDG + CDS + CDB (3.16) The sign convention used for the firstorder channel capacitive current (3.10) into the source terminal of transistor(s) connected to the power supply is shown in Figure 3.7. Figure 3.7 Sign convention for channel capacitive currents in transistors 27 In digital applications, the substrate terminal is biased at a constant voltage so that the last column in equations (3.9)(3.11) can be ignored. Integration of the channel capacitive current equations gives the channel charge expressions (3.17)(3.19), which make the evaluation of channel storage charge convenient for piecewise linear approximations of the firstorder channel capacitive currents into each transistor terminal. ΔQG = CGGΔVG − CGSΔVS − CGDΔVD − CGBΔVB (3.17) ΔQS = −CSGΔVG + CSSΔVS − CSDΔVD − CSBΔVB (3.18) ΔQD = −CDGΔVG − CDSΔVS + CDDΔVD − CDBΔVB (3.19) The channel storage charge model (3.17)(3.19) requires linearized capacitances in each linear region of operation in order to evaluate average power dissipated by parasitic capacitors. The following is a piecewise linear approximation of the BSIM capacitance model. Ohmic Region: QGohm = Cox (VGS − VT ) − (aS + aD)CoxVDS + bSBCox (VSB + VT − VFB) (3.20.1) Sohm ox GS T S ox DS Q 1 C (V V ) a C V 2 − = − − (3.20.2) Dohm ox GS T D ox DS Q 1 C (V V ) a C V 2 − = − − (3.20.3) Saturation Region: QGsat = bGSCox (VGB − VFB) + bSBCox (VSB + VT − VFB) (3.21.1) −QSsat = (1− xpart )bGSCox (VGS − VT ) (3.21.2) −QDsat = xpartbGSCox (VGS − VT ) (3.21.3) Cutoff Region: 28 QGoff = bSBCox (VGB − VFB) (3.22.1) −QSoff = 0 (3.22.2) −QDoff = 0 (3.22.3) Using continuity of charge at the ohmicsaturation boundary, we find S part GS a a(1 (1 x )b ) 2 = − − (3.23) Similarly, D part GS a a(1 x b ) 2 = − (3.24) Using continuity of charge at the cutoffsaturation boundary, we find QG = bSBCox (VGB − VFB) = bGSCox (VGS − VT ) + bSBCox (VSB + VT − VFB) (3.25) is satisfied when VGS = VT , putting the values for aS and aD back into (3.20) gives QGohm = Cox (VGS − VT ) − a(1− bGS)CoxVDS + bSBCox (VSB + VT − VFB) (3.26.1) Sohm ox GS T part GS ox DS Q 1 C (V V ) a(1 (1 x )b )C V 2 2 − = − − − − (3.26.2) Dohm ox GS T part GS ox DS Q 1 C (V V ) a(1 x b )C V 2 2 − = − − − (3.26.3) The charge storage currents are: Goff G Goff SB ox dQ dV i b C dt dt = = (3.27.1) G S D Gohm ox SB SB GS dV dV dV i C (1 b a(1 b ) a(1 b ) dt dt dt = ⎡ − − − − − − ⎤ ⎢⎣ ⎥⎦ (3.27.2) G S D Sohm ox part GS part GS 1 dV 1 1 dV 1 dV i C ( a( (1 x )b )) a( (1 x )b ) 2 dt 2 2 dt 2 dt = ⎡− + − − − + − − ⎤ ⎢⎣ ⎥⎦ (3.27.3) G S D Dohm ox part GS part GS 1 dV 1 1 dV 1 dV i C ( a( x b )) a( x b ) 2 dt 2 2 dt 2 dt = ⎡− + − − + − ⎤ ⎢⎣ ⎥⎦ (3.27.4) 29 G S Gsat GS ox GS SB ox i b C dV (b b )C dV dt dt = − − (3.27.5) G S Ssat ox part GS part GS dV dV i C (1 x )b (1 x )b dt dt = ⎡− − + − ⎤ ⎢⎣ ⎥⎦ (3.27.6) G S Dsat ox part GS part GS dV dV i C x b x b dt dt = ⎡− + ⎤ ⎢⎣ ⎥⎦ (3.27.7) Comparing the derivatives of (3.27) with (3.9)(3.12) gives the following linearized results for the transistor capacitances. Table 1 Linearized Parasitic Transistor Capacitances with Overlap Capacitance Cutoff Ohmic Saturation CGG bSB COX + CGSO + CGDO +CGBO COX + CGBO bGS COX+ CGSO + CGDO +CGBO CGS CGSO (1 − bSB−a(1−bGS))COX + CGSO (bGSbSB)COX+CGSO CGD CGDO (1 − bGS)aCox + CGDO CGDO CSG CGSO (1/2)Cox + CGSO (1 − xpart)bGS COX + CGSO CSS CGSO (1/2 − a(1/2− (1−Xpart)bGS))COX+ CGSO (1 − xpart)bGS COX+ CGSO CSD 0 −a(1/2 −(1− xpartb)bGS)COX 0 CDG CGDO (1/2)Cox+ CGDO xpartbGS COX+ CGDO CDS 0 (− 1/2 + a(1/2 − xpartb)) Cox − XpartbGS COX CDD CGDO a(1/2 − XpartbGS) COX+ CGDO CGDO The gate to drain and gate to source overlap capacitances shown in Figure 3.8 are becoming more significant in submicron and deep submicron technologies, therefore gate overlap capacitances are included in the linearized capacitance model in Table 1. The gate to substrate overlap capacitance, CGBO, is negligible in modern processes but is included for the sake of completeness. The BSIM model for the overlap capacitance is 30 CGSO = WCgso (3.28) which must be added to CGG, CGS, CSS, and CSG to the previous expression (3.27), so CGDO = WCgdo (3.29) which must be added to CGG, CGD, CDD, and CDG to the previous expression (3.27), so CGBO = 2LCgbo (3.30) which must be added to CGG to the previous expression (3.27). Figure 3.8 Gate overlap capacitances for FETs With the linearized capacitance model, average power supply current into the parasitic capacitances can be evaluated by integrating the firstorder channel capacitive currents into the transistor(s) connected to the power supply, which is usually the transistor source current(s). From the linearized capacitance model, it is essential to understand that the linearized capacitances are valid only within each piecewise linear region while the firstorder channel capacitive current into the source node of the transistors is computed. Therefore, the initial and final terminal voltages in each piecewise linear region, associated with the transistor(s) connected to the power supply, must be computed before the average power dissipation can be evaluated. Approximate solutions for circuit dynamics has been used very successfully in predicting instantaneous 31 voltage waveforms [36], and the approximate solution for circuit voltage is extended beyond the gate delay predictions to compute the average power dissipated from the power supply with the piecewise linear switching current–voltage (IV) model and capacitance–voltage (CV) model. 3.2 Ramp Input Approximation Rather than attempt an arbitrary input, the piecewise linear model assumes the input signal is a simple ramp with finite transition time as show in Figure 3.9. in in0 in0 in in in0 in in0 in0 in0 Tin in Tin in0 Tin V (t ) t t V (t) V (t ) V (t t ) t t t t V (t ) t t t ⎧ < = ⎪ + − < < + ⎨⎪ ⎩ > + & (3.31) where the slope of a ramp input is in in0 Tin in in0 in Tin V V (t t ) V (t ) t + − & = (3.32) Figure 3.9 Input ramp approximations Under Veendrick’s assumption, the shortcircuit power is proportional to the input rise and fall times and the load capacitance. Hence, it is essential to approximate the input 32 signal with a ramp approximation to evaluate shortcircuit current induced power dissipation. Also, the simple ramp approximation includes the shortcircuit current into the gate delay evaluation, which is essential to predict rise and fall time at any capacitive node [19] [36]. For a more general input approximation than the input expression of (3.31), the input to each resistance connected region is approximated as a series of piecewise linear segments as shown in Figure 3.10. Figure 3.10 Piecewise linear approximation of input ramps in resistance connected regions in in0 in0 in ink 1 in ink in in ink ink ink ink ink 1 ink 1 ink in inkmax inkmax V (t ) t t V (t ) V (t ) V (t) V (t ) (t t ) t t t t t t V (t ) t t + + + ⎧ < ⎪⎪⎪ ⎪ − ≈ ⎨ + − < < + − ⎪⎪⎪ > ⎪⎩ (3.33) in ink V (t )is determined by approximating the input waveform at a finite number of times, tink . The accuracy of the approximation increases with the number of time points. However, adding time points increases the amount of calculation necessary to 33 determine the voltages in the resistance connected region. First, we will find the approximate solution for circuit voltage with a ramp input (3.31). 3.3 Approximate Solution for Circuit Voltage 3.3.1 Resistive Connected Regions A resistive connected region is defined as a set of circuit nodes connected by paths through the source or drain terminals of transistors in the ohmic region of operation. A resistive connected region can be described with a conductance matrix, G, when the zeroorder switching current is calculated. G is a matrix for a resistive connected region and should not be confused with transconductance Gm for the mth transistor. When the mth transistor is in saturation, it is modeled as gate voltage controlled current source between the drain and source and has the effect of decoupling source and drain into separate resistive connected regions [36]. The steady state solution of circuit voltage in delay modeling encompasses nonsingular G and singular G cases [36]. However, solving for the steady state solution of circuit voltage when the G matrix is singular can be avoided in computing average power dissipation, because the power supply current into the transistor(s) in saturation is determined by gate controlled current source, which is independent of drainsource bias. Thus, the approximate solution for circuit voltage at each drain node is considered only with a nonsingular G matrix only for average power estimate. Instead of solving for all circuit node voltages at once, the complexity of the circuit is reduced by approximating the solution in each resistive connected region connected to the power supply. 34 3.3.2 Approximate Solution for Circuit Voltage with NonSingular G Matrix It is assumed that the circuit of interest consists of transistors and capacitors only. The mth transistor is connected to circuit nodes Sm, Gm, and Dm, and the cth capacitor is connected to nodes AC and BC as shown in Figure 3.11. Figure 3.11 Notation for transistor number “m” and circuit node names Large CMOS circuits can be partitioned into many resistively connected groups of nodes. Using the ramp approximation from equation (3.31) for the input nodes, the circuit dynamic equation can be generalized regardless of circuit topologies [36]. in in in in 0 in 0 Tn Tn Tp Tp dd dd dV C V V G (V (t ) V (t t )) G V G V G V 0 dt C + & +G + + & − + + + = (3.34) where G and C in bold letters represent twodimensional matrices and Cin ,Gin ,GTn , GTp , and Gdd are column vectors. It helps to simplify the circuit dynamic equation if the column vectors Iin (t0 ) and &Iin are defined as Iin (t0 ) = CinV& in +GinVin (t0 ) +GTnVTn +GTpVTp +GddVdd (3.35) Iin = GinVin & & (3.36) The circuit dynamic equation (3.34) can be rewritten as 35 in 0 in 0 dV V I (t ) I (t t ) 0 dt C +G + + & − = (3.37) where the G matrix is now the ondiagonal subblock for a single resistance connected region and the C matrix is rectangular in general, and includes capacitive coupling from nodes inside the resistance connected to all other circuit nodes including those inside and outside the resistance connected region [36]. The steady state solution, V% , after the exponential components die out has the form of equation (3.38). 2 0 0 0 V(t) V(t ) V(t t ) V (t t ) 2 − % = % + %& − + &%& (3.38) The steady state solution for a general circuit must satisfy the dynamic equation which can be written as in in 0 V dV I I (t ) dt G C ⎡ ⎤ = − ⎢ + + ⎥ ⎣ ⎦ % % & (3.39) Collecting terms of the same power of t, which leads to GV&%& = 0 (3.40) GV = −(CV+ Iin ) %& &%& & (3.41) GV(t0 ) = −(CV+ Iin (t0 )) % %& (3.42) The conductance matrix G for the resistance connected region will be nonsingular as long as the region includes the power or ground node. When G is nonsingular, G1 can be used to find V&%& = 0 (3.43) The equation (3.41) can be rewritten as 1 V G Iin %& = − − ⋅ & (3.44) 36 1 V(t0 ) G (CV Iin (t0 )) % = − − %& + (3.45) V(t0 ) % can be rewritten after substituting V&% , such that 1 1 V(t0 ) G (CG Iin Iin (t0 )) % = − − & + (3.46) Gis a small dimension matrix describing a single resistance connected region, so that G1 is not difficult to compute. It is possible to find a steady state solution in each resistance connected region knowing only the piecewise linear approximation(s) to VIN. Thus, solving the circuit dynamic equation with a ramp input, the approximate voltage at each node Dm in a resistively connected region can be written as m m m m m 0 D D D 0 D 0 D V ( t ) = V ( t ) + [V ( t ) V ( t ) ] e x p ( t  t ) τ % − % ⋅ − t > t 0 (3.47) The column vectors for the approximate voltages at each resistively connected node Dm are rewritten as V D m ( t ) = V D m ( t 0 ) + V D m ( t  t 0 ) % % &% (3.48) m 1 1 D 0 in in 0 Dm V% (t ) = [G− (CG− &I + I (t ))] (3.49) m 1 D in D m V%& = − [G − ⋅ &I ] (3.50) Therefore, the equation (3.48) is rewritten as m 1 1 1 D in in 0 in 0 D m V% ( t ) = [G − (C G − &I + I ( t ) ) − G − ( &I ( t  t ) ) ] (3.51) Unfortunately, G and C are not constant in general, but change as the switching transistors go into their various regions of operation. It is assumed that the solution beginning at t0 does not “know” that it will become invalid later, but can be extended 37 indefinitely forward in time with a constant G and C. This allows the upper limit in the integrals to be extended to infinity when the average power is evaluated. 3.4 Average turnoff Energy Evaluation with the Zeroorder Switching Current Model In a CMOS circuit, average turnoff energy occurs due to shortcircuit current flows during the time when the pFET and nFET network are on simultaneously. It is necessary to compute the power supply current into the source of every pFET for the time period when shortcircuit current occurs. Average turnoff energy is evaluated from the sum of shortcircuit currents in each piecewise linear region for any turningoff pFET connected to the power supply. Each turningoff transistor may cross through each region of operation, cutoff, ohmic, and saturation. Given the slope of the input waveform (or gate voltage VGm (t) ) and the slope of the output waveform (or drain voltage VDm (t) ) as functions of time from solving circuit dynamic equations, shortcircuit current drawn from the power supply current into each transition can be approximated with the zeroorder piecewise linear switching current, such that, T T 2 1 2 2 0 1 2 vdd(off)dt S (ohmic)dt + S (sat)dt + S (off)dt n t t m m m 0 m 1 t t t I I I I ⎡ ⎤ ⎢ ⎥ − = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ = Σ ∫ ∫ ∫ ∫ (3.52) where t0 is the time when the nFETs reach VGSN = VTn, and the power supply current into the source of pFETs are proportional to each drain to source bias pf pFETs connected to the power supply. Average turnoff (shortcircuit) energy is evaluated when the input has reached VGSN = VTn, and pFETs are operated in the ohmic and saturation regions and is computed as 38 dd 0 T E 2 Ivdd (off) t = V ⋅ ∫ −Ivdd(off)dt for ri sin g transitions (3.53) where the subscript ‘m’ in (3.52) is the transistor number of turningoff transistor(s) connected to the power supply. Each term in (3.52) comes from each piecewise linear approximation to the zeroorder quasistatic switching current into turnoff transistor(s) in ohmic, saturation, and cutoff regions which are evaluated individually in the following sections. 3.4.1 ZeroOrder Turnoff Current in Ohmic Region: The power supply current Ivdd(t) going into the source of every turningoff transistor(s) in ohmic is the zeroorder quasistatic current in ohmic region, and is computed as follows. ( ) 1 1 0 0 1 m mm 0 1 m m 0 1 0 D m m m m 0 m 0 0 t t t m t m t P m D S t t P m D dd t t t t P m D D (t ) D (t ) dd t IS (ohmic)dt ID (ohmic)dt a G V dt a G V (t) V dt a G V (t)+[V V ] e V dt − − ⎡ ⎤ ⎡ ⎤ ⎢ ⎥ = − ⎢ ⎥ ⎣ ⎦ ⎣ ⎦ ⎡ ⎤ = − ⎢ ⎥ ⎣ ⎦ ⎡ ⎤ = − ⎢ − ⎥ ⎣ ⎦ ⎡⎛ ⎞ ⎤ = − ⎢⎜ ⋅ ⎟ − ⎥ ⎢⎜ ⎟ ⎥ ⎢⎜ ⎟ ⎥ ⎣⎝ ⎠ ⎦ τ ∫ ∫ ∫ ∫ ∫ % % t1 > t0 (3.54) where VDm (t) % in (3.54) has a constant term and a time dependent term, so that the solution of equation (3.54) is written as 39 t1 t0 D 1 0 1 0 P Dm m Dm( t ) m 0 Dm m Dm( t ) 0 Dm( t ) 0 dd G e 1 V V V V 1 V ( ) 2 a t t t t [( )( ) ( )( )] − − − τ = − − + − − − % τ % %& t1 > t0 (3.55) where Dm 0 V% (t ) and Dm V&% are defined in (3.49) and (3.50) and are the column vector for each resistively connected node in the linear ohmic region from the time period between t0 and t1 . The delay time constant ( Dm τ ) has a general form for a resistive connected node [36], which is written as follows. 1 0 0 Dm Dm Dm 0 Dm 0 [G C V(t ) V(t ) ] V (t ) V (t ) − − τ = − % % (3.56) 3.4.2 ZeroOrder Turnoff Current in saturation region Before the transistor turns off completely, it may operate in saturation, and the power supply current Ivdd(t) going into the source node of turningoff transistor(s) in saturation is the zeroorder current in saturation, which is proportional to the gate voltage (or the slope of input waveform) and the zeroorder current in saturation is computed as follows. 40 2 2 S D 1 1 2 G m Sm T p m 1 2 T pm 1 T in t t t m t m t m t t dd m dd t (s a t) d t (s a t) d t = G dt G V t d t T I I V V V V V ⎡ ⎤ ⎡ ⎤ ⎢ ⎥ = − ⎢ ⎥ ⎢⎣ ⎥⎦ ⎢⎣ ⎥⎦ ⎡ ⎤ − ⎢ − − ⎥ ⎢⎣ ⎥⎦ ⎡ ⎡ ⎛ ⎞ ⎤ ⎤ = − ⎢ ⎢ ⎜ − ⎟ ⎥ − ⎥ ⎢ ⎣ ⎝ ⎠ ⎦ ⎥ ⎣ ⎦ ∫ ∫ ∫ ∫ 2 1 dd m 2 1 dd Tp Tin m G (t t ) (t + t )V V + V 2 T ⎛ − ⎞ = − ⎜ + ⎟ ⎝ ⎠ , t2 > t1 (3.57) 3.4.3 ZeroOrder Turnoff Current in Cutoff Region The power supply current into the source of transistor(s) in cutoff region is zero and is included for the sake of completeness. 2 T 2 t Sm(off) ∫ I dt = 0 (3.58) In the piecewise linear model, average power supply current for the zeroorder component into the source of turnoff transistor(s) is zero after the input reaches a steady state value or the end of input transition time ‘TTin’. 3.5 Average Turnon Energy Evaluation with the Zeroorder Piecewise Linear Current Model The power supply current Ivdd(t) into the source of turningon pFET is the sum of the dynamic current for charging the load capacitance and the shortcircuit current of turningoff nFETs. It is worth to mention that the average turnoff energy of nFETs is already included when the average turnon energy of pFETs is evaluated directly from 41 the power supply current. It is one of the advantages of evaluating average power by computing power supply current instead of evaluating current and voltage for each turnoff transistor(s) individually. For arbitrary slopes of input and output waveforms at the drain and gate, and including all operation regions, the power supply current Ivdd(t) into the source of turnon pFETs in a resistive connected region can be formulated as, si 3 si 3 Sm Sm Sm T n t t T Vdd T T t t 2 m=1 2 I (on) dt = I (off)dt + I (Sat)dt I (ohmic)dt ⎡ ⎤ ⎢ ⎥ − ⎢ + ⎥ ⎢ ⎥ ⎣ ⎦ ∫ Σ ∫ ∫ ∫ (3.59) where tsi is the time when an input signal ramps down to VGSP = VTp of transistor(s) connected to the power supply. As the input continues to ramp down, the pFETs go into saturation region from the time tsi to t3, and so on until pFETs turns off after the input reaches the steady state “Low”. Average turnon energy during the input falling transition period is then computed as T dd T vdd 2 E I vdd (on) = V ⋅ ∫ − I (on) dt (3.60) It is assumed that the solution beginning at T 2 and can be extended indefinitely forward in time with a constant G and C. This allows the upper limit in the integral to be extended to infinity. The power supply current Ivdd(t) going into each turnon transistor in each piecewise linear operation can be computed as follows. 3.5.1 ZeroOrder Turnon Current in Cutoff Region 42 T S (off) 2 si m dt 0 t ∫ I = (3.61) 3.5.2 Zeroorder Turnon Current in Saturation Region The power supply current Ivdd(t) going into the source of pFETs in saturation is a zeroorder quasistatic current in saturation, and is computed as follows. 3 3 3 S D S T p m si s i s i 3 d d dd dd T p m s i T in t t t m Gm m t t t t m t (s a t) d t (s a t) d t G (V V V )d t m m V G V t V V d t T I = − I = − − − ⎡ ⎛ ⎞ ⎤ = − ⎢ ⎜ − ⎟ − − ⎥ ⎢⎣ ⎝ ⎠ ⎥⎦ ∫ ∫ ∫ ∫ Pm 3 si dd m 3 si T Tin (t t )V G (t t ) V 2 T [ + ] = + , t3 > tsi (3.62) 3.5.3 ZeroOrder Turnon Currents in Ohmic Region In the ohmic region, the zeroorder drain current or the source current of a transistor is independent of the gate voltage. Therefore, the zeroorder turnon currents from the power supply Ivdd(t) into the sources of pFET are evaluated using the same equation as (3.55) regardless of rising or falling inputs, but with the sign changes in the V&% expression. In other words, the zeroorder turnon current is proportional to the approximate drain voltage of each pFET transistors connected to the power supply. Approximated voltage at each drain node depends on the column vectors &Iin and Iin (t0 ) in each piecewise linear region from which a positive or a negative input slope (V& in ) is given. 43 3.5.4 Resistive Connected Region with Steady State Input When the transistor is driven by a steady state input, the slope of input waveform or V& in is zero. The power supply current Ivdd(t) going into the source of pFETs in ohmic and saturation regions with a steady state input has to be reevaluated. 3.5.4.1 ZeroOrder Turnon Current in Saturation When the driving input to the transistor(s) connected to the power supply is in the steady state of the input falling transitions, the zeroorder turnon current for transistor(s) in saturation is reevaluated as follows. m 3 G t3 t tsi t si (V ∫ ∫ ∫ S D Tpm 3 si m m t m dd t (sat)dt =  (sat)dt = G  V  V )dt I I t3 > tsi where VGm has a Vin & component equal to zero, which leads to the solution as ⋅ = Gm(t3 tsi)(Vdd +VTpm) (3.63) 3.5.4.2 ZeroOrder Turnon Current in Ohmic Region With the input in steady state, the column vector &Iin becomes I in = G in Vin = 0 & & (3.64) And the steady state solution for circuit voltage in a resistive connected region has to be reevaluated as follows [36]. 1 1 V D m ( t  t 0 ) = G (C V + I in ) = G I in = 0 %& &%& & & (3.65) 44 V D m ( t ) = V D m ( t 0 ) + V D m ( t  t 0 ) = V D m ( t 0 ) % % %& % (3.66) The approximate solution for the circuit voltage at the drain node after the input is in the steady is rewritten as follows. D m D m D m D m D m 0 0 0 0 t  t V ( t ) = V ( t ) + [V ( t )  V ( t ) ] e x p (  ) τ % % ⋅ (3.67) Where V%Dm (t0 ) is already defined by (3.49). Thus, zeroorder turnon current in the ohmic region is then rewritten for input in steady state. Yet, the G and C matrices are not constant in general, but remain constant in the ohmic region, so that the solution for the approximate circuit voltage at the drain terminal can be extended forward in time with a constant G and C matrix in the ohmic region, which allows the integrals to be extended to a specific time boundary or to infinity in time as seen in equations (3.68) and (3.69). 3 3 T T t t T dt dt ( = − = − ∫ ∫ ∫ S D m D m 3 m m P m dd t (ohmic) (ohmic) a G V (t)V ) I I T > t3 ( ) ( ) ( ) T t3 Dm [ ) T Vdd T e 1 ) ) Dm ] − ⎛ − ⎞ = − − + − + ⎜ τ − ⎟ − τ ⎜⎜ ⎟⎟ ⎝ ⎠ % % aPm Gm VDm(t0 t3 t3 VDm(t3 VDm(t3 (3.68) Here in (3.68), it can be proved that the quasistatic state voltage % Dm V at the output node follows the steady state value Vdd as t1 goes to infinity, so that the first two terms would cancel out. Thus, if an input reaches a steady state voltage, the boundary to the final region of operation of pFETs in the ohmic can be extended to infinity. Such that, 45 t 3 t3 dt dt ( ∞ ∞ ∞ = − = − ∫ ∫ ∫ S D m D m 0 m m P m dd t (ohmic) (ohmic) a G V (t) V ) I I = [− Vdd − ) τDm % ) + τDm )] aPm Gm t3 VDm(t3 + VDm(t3 (t3 (Vdd − ) )τDm = aPm Gm VDm(t3 (3.69) 3.6 Switching Energy in the Transistor Parasitic Capacitances The parasitic capacitors from transistors connected directly to the power supply also contribute power dissipation, because dissipative current flows in the channels of the switching transistor(s) as channel charge is redistributed within the channel. Therefore, the switching current induced energy is evaluated by integrating over a cycle of channel capacitive currents into the source of every pFET connected to the power supply and is written as follows. 0 0 T n T T 2 dd dd m T m t t 2 m 1 Ei V ivdd (t) V is is dt vdd [ ] = = ⋅ ∫ − = ⋅Σ ∫ +∫ (3.70) where E ivdd is the average switching energy drawn from the power supply current due to the nonlinear capacitive currents of the switching transistor(s) connected to the power supply. Lower case current ‘i’ is used to differentiate from “I” in zeroorder quasistatic current when average turnoff and turnon energy are evaluated. Expression from (3.70) is then evaluated in equation (3.71) and (3.72) individually which has the same integration boundaries of the zeroorder switching energy evaluated in equations (3.52) and (3.59). 46 0 T 1 2 2 1 2 n T n 2 t m m m m m 1 m 1 0 t t is dt is (ohmic)dt + is (sat)dt + is (off)dt = = t t t ⎡ ⎤ = ⎢ ⎥ ⎢ ⎥ ⎢⎣ ⎥⎦ Σ∫ Σ ∫ ∫ ∫ (3.71) n T n 3 T m 2 m m m m 1 2 m 1 T 3 tsi t T is dt is (off)dt + is (sat)dt + is (ohmic)dt = = tsi t ⎡ ⎤ = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ Σ∫ Σ ∫ ∫ ∫ (3.72) The average power supply current into the channel storage elements is the firstorder current and is a piecewise linear approximation of channel capacitive currents of the transistor in the cutoff, ohmic, and saturation so that the integral can be computed with the same technique, knowing only the initial and final voltage at the drain of each pFET connected to the power supply. CSGm , CSSm , CSDm , and CSBm are the lumped capacitances in Table 1 associated with each transistor terminal in the mth transistor(s) connected to the power supply. VSm Δ and VBm Δ are zero, because the source and body (substrate) voltages do not change for pFET that are directly connected to the power supply in digital CMOS circuit applications. Therefore, equation (3.71) and (3.72) are simplified to each component of integration individually as expressed in (3.73), (3.74), and (3.75). m m m m m m m m 0 0 1 1 G S D B m SG SS SD SB t t ohmic t t dV dV dV dV is (ohmic)dt = C C C C dt dt dt dt dt ⎛ ⎞ ⎜⎜− + − − ⎟⎟ ⎝ ⎠ ∫ ∫ (3.73) ( ) ( ) m m m m m m1 m 0 m m 1 m 0 1 1 SG (ohmic) G SD (ohmic) D 0 0ohmic SG (ohmic) G (t ) G (t ) ohmic SD (ohmic) D (t ) D (t ) ohmic t t C V  C V  t t C V V C V V ⎡ ⎤ = ⎢− ⋅ − ⋅ ⎥ ⎣ ⎦ = − ⎡ ⋅ − ⎤ − ⎡ ⋅ − ⎤ ⎣ ⎦ ⎣ ⎦ It should be noted that the lumped capacitors are not constant as the transistors switch from ohmic to saturation. Thus, the lumped terminal capacitors from the mth transistor in (3.73) for ohmic region are different from the lumped terminal capacitors in (3.74) for 47 transistor in saturation as shown by the linearized lumped capacitors in Table 1. When pFET in saturation, the channel capacitive current is computed as m m m m m m m m 2 2 1 1 G S D B m SG SS SD SB sat t t dV dV dV dV is (sat)dt = C C C C dt t t dt dt dt dt ⎛ ⎞ ⎜⎜ − + − − ⎟⎟ ⎝ ⎠ ∫ ∫ (3.74) ( ) ( ) m m m m m m 2 m 1 m m 2 m 1 2 2 SG (sat) G SD (sat) D 1 1sat SG (sat) G (t ) G (t ) SD (sat) D (t ) D (t ) sat t t C V  C V  t t C V V C V V ⎡ ⎤ = ⎢− ⋅ − ⋅ ⎥ ⎣ ⎦ = ⎡− ⋅ − − ⋅ − ⎤ ⎣ ⎦ Where CSGm and CSDm changes as transistors switch from ohmic to saturation. Similarly, in the cutoff region, m m m m m m m m 2 2 T T 2 2 G S D B m SG SS SD SB t t off dV dV dV dV is (off)dt = C C C C dt dt dt dt dt ⎛ ⎞ ⎜⎜− + − − ⎟⎟ ⎝ ⎠ ∫ ∫ (3.75) T T 2 2 m m m m m m m 2 m m m 2 T T 2 2 SG (off ) G SD (off ) D 2 2off SG (off ) G ( ) G (t ) SD (off ) D ( ) D (t ) off C V  C V  t t C V V C V V ⎡ ⎤ = ⎢− ⋅ − ⋅ ⎥ ⎢⎣ ⎥⎦ = ⎡− ⋅ ⎛ − ⎞ − ⋅ ⎛ − ⎞⎤ ⎢ ⎜ ⎟ ⎜ ⎟⎥ ⎣ ⎝ ⎠ ⎝ ⎠⎦ (3.72) is evaluated using the same approach for the other half cycle. The computation to the channel capacitive current contributed to the energy dissipation is simplified to the calculation of the initial and final voltage at drain and gate for each piecewise linear region with the linearized capacitance model. 3.7 Summary The piecewise linear transistor model consists of a zeroorder switching current model and a channel storage charge model. The zeroorder switching current model 48 evaluates the average power supply current at the time period when a CMOS circuit dissipates shortcircuit current and dynamic current. Equation (3.56) and (3.70) are derived from the generalized circuit dynamic equation with the zeroorder switching current model to predict the power supply current into the transistors connected to the power supply during the transistors in the ohmic region. When the transistors connected to the power supply are in saturation, the power supply current is proportional only to integral of the gate controlled current sources connected to the power supply which simplifies the computation because the current sources are independent of the drain voltages of the transistors in saturation. Total power supply current or total average power can be evaluated much quicker with the simplified solutions of the integrals of transistor switching transient currents to account for the short circuit current, dynamic current, and channel capacitive current into a total power calculation. In the following chapter, the power supply current into an inverter circuit driving different load capacitances will be evaluated, and the integral of each switching transient current and the solutions for each piecewise linear region will be used to obtain a total average power from the inverter driving different load capacitances. 49 CHAPTER 4 AVERAGE POWER ANALYSIS OF INVERTER WITH A PIECEWISE LINEAR MODEL 4.0 Introduction A piecewise linear transistor model was introduced in the previous chapter. In this chapter, the piecewise linear model will be used to evaluate the average power dissipation of a simple inverter gate. The average power will be computed from the power supply current into the source of pFET of the inverter, which is the sum of zeroorder quasistatic switching current and firstorder channel capacitive currents. The model computes average power of inverter by integrating zeroorder switching current and firstorder channel capacitive currents over a switching cycle. The integration of each switching transient current is simplified to a solution compatible with the efficient piecewise linear delay model [36]. Average power evaluation by the model is compared with SPICE simulation of the same circuit over a wide range of input slopes, transistor sizes, and different capacitive loads. 4.1 Average Power Analysis of Inverter Driving Load Capacitance An inverter has one drain node between the power supply and ground, so that the average turnoff (short circuit) energy, average turnon energy, and switching energy 50 of the transistors parasitic capacitances are evaluated based on the approximate circuit voltages at the drain and gate of pFET in the inverter, and the input slope were approximated by an efficient piecewise linear delay model [36]. Figure 4.1 Inverter driving load capacitance with input ramp approximation Using the ramp input approximation to the circuit dynamic equation of the inverter, Figure 4.2 is the graphical representation of piecewise linear approximation to the circuit voltages at the drain with transistors transitional boundaries and operation regions [36]. There are nine boundary lines and eight piecewise linear regions, which are derived from the piecewise linear switching current equations and the circuit dynamic equation for the inverter. It is necessary to define the terminals of the pFET, which is connected to the power supply, a driving input node, and drain node of inverter to facilitate average power calculation, so that we may write VGSN = VIN, VDSN = VOUT , VGSP = VIN – VDD, and VDSP = VOUT – VDD. Boundaries of each piecewise linear region as functions of time in ohmic, saturation, and cutoff (tsi, t1, t2, t3, TTin), terminal voltages (VDS, VGS), and each piecewise linear regions (R0 →R8) for the pFET and nFET in inverter are also shown in Figure 4.2. 51 Figure 4.2 Inverter transient analysis with boundaries and operation regions with rising input ramp approximation In Figure 4.2, a ramp input is assumed in the inverter for the first half cycle, and the output waveform is plotted against t/TTin from the closed form solution of the circuit dynamic equation (Eq. 3.37). Regions of operation in the inverter are denoted as “R1 Sat Ohm” which indicates region 1 with nFET in saturation and pFET in the ohmic region, and “VGS = VDD” on xaxis is the end of the input transition time “TTin”. Fig. 4.4 uses the same definitions of the piecewise linear region in the cutoff, ohmic and saturation and the model parameters. It should be noted that a fast input ramp is equivalent to a short input transition time “TTin”, so that curve 3 in Fig. 4.2 and Fig.4.4 is corresponding to a fast input ramp and curve 1 is the output waveform approximation of a slow input ramp [36]. 4.1.1 Turnoff Energy Analysis In an inverter gate, turnoff (shortcircuit) energy is evaluated from the pFET transistor, connected to the power supply, when it turns off. Turnoff energy is proportional to the input transition time on the gate and the zeroorder switching off current of pFET provided from the power supply during input (0→1) transition during the load capacitance discharge cycle. Turnoff energy is then evaluated by integrating the zeroorder switching off current provided by the power supply into the source of pFET 52 from the time period when it is on to off. If an input is a slow rising input ramp, the voltage waveform at drain node as shown in waveform 1 (Figure 4.2) is a possible solution. Then, given the input slope and the output waveform, the zeroorder current into the source of the turning off pFET is evaluated from the sum of pFET current from its on (ohmic) state to off state across the ohmic region from initial time t0 to t1 and across saturation region from t1 to t2 respectively, which is written according to the integration of the zeroorder switching current in each respective operating region in equation (3.52). T T 2 2 S S S 1 2 0 0 1 2 EIvdd(off ) V Ivdd(off)dt V I (ohmic)dt + I (sat)dt + I (off)dt t t dd dd m m m t t t t ⎡ ⎤ ⎢ ⎥ = − = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ∫ ∫ ∫ ∫ D t1 t0 Dm dd D 1 0 m( t0 ) m 2 1 dd 1 0 m 2 1 dd Tp Tin Pm m Dm( t ) Dm( t ) 0 0 Dm m V G e 1 V V Vdd V 1 (t + t )V V ( ) G (t t ) V +V 2 2 T a t t t t { [( )( ) ( )( )] } − − − τ = − − + − − ⎛ − ⎞ − + − ⎜ + ⎟ ⎝ ⎠ % τ % &% Where t1 > t0 and t2 > t1 (4.1) When the input is a fast ramp, the pFET may turn off before it goes into saturation region. The slope of the voltage waveform at the drain node shown in the waveform 3 (Figure 4.2) is a possible solution, such that the shortcircuit energy drawn from the power supply is reevaluated for ohmic region only as in equation (4.2). T T 2 2 S S 2 0 0 2 EIvdd(off ) V Ivdd(off)dt V I (ohmic)dt + I (off)dt t dd dd m m t t t ⎡ ⎤ ⎢ ⎥ = − = ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ∫ ∫ ∫ t2 > t0 (4.2) dd D 2 0 2 0 Dm Dm( t ) m 0 Pm m Dm(t ) Dm(t ) Dm 0 0 t2 t0 dd V G e 1 V V V V 1 V ( ) 2 {a [( )( ) (t t )( t t )]} − − − τ = − − % τ + − % − &% − It should be noted that turnoff energy is evaluated only when the input is rising or the transistor(s) connected to the power supply turns off. 53 4.1.2 Turnon Energy Analysis Turnon energy is evaluated during input (1→0) transition when the pFET of the inverter, connected to the power supply, turns on and conducting the zeroorder switching current during the load capacitance charging cycle. The power supply current is the sum of the zeroorder switching currents for charging the load capacitance and the shortcircuit current of turningoff nFET. Resembling turnoff energy evaluation, output waveform approximation in Figure 4.4 is derived to compute turnon energy. Figure 4.3 Inverter driving load capacitance with input falling ramp approximation Figure 4.4 Inverter transient analysis with boundaries and operation regions with input falling ramp approximation Turnon energy is computed from the sum of zeroorder switching current of pFETs connected to the power supply and the short circuit current of turningoff nFET connected with pFETs. It should be noted that shortcircuit current of nFET is drawn 54 from the power supply current from the channel of turningon pFET. Therefore, evaluation of turnon energy is simplified to the calculation of total current into pFETs only. Equation (4.3) shows the turnon energy evaluated from the current of pFETs connected to the power supply during pFETs turningon period. T S S S T T 2 2 si 3 si 3 T EIvdd(on) V Ivdd (on)dt V I (off)dt + I (sat)dt + I (ohmic)dt t t dd dd m m m t t ⎡ ⎤ − ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ = ∫ = ∫ ∫ ∫ ( ) ( ) ( ) Pm m 3 si dd m 3 T P 3 3 Tin Dm(t0 ) T t3 Dm Dm(t3 ) Dm(t3 ) Dm dd si m dd V G (t  t ) (t t )V V a G V T t V T t 2 T e 1V V [ ] { [ ] } − − + + − − + − + ⎛ ⎞ ⎜ τ ⎟ ⎜ − ⎟ − τ ⎜ ⎟ ⎝ ⎠ = + % % Where t3 > tsi and T > t3 (4.3) 4.1.3 Switching Energy in the Transistor Parasitic Capacitances The power supply current into the parasitic capacitances of pFET, connected to the power supply, is the firstorder channel capacitive currents in the transistors. Switching power of the parasitic capacitances is evaluated by integrating the firstorder channel capacitive currents over a switching cycle to measure if the channel capacitive currents draw energy from the power supply. Equation (3.70) can be rewritten for a simple inverter gate, such that switching energy of the parasitic capacitances of the pFET can be computes as 0 0 T T T 2 dd dd m T m t t 2 Ei V ivdd (t) V is is dt vdd = ⋅ ∫ − = ⋅[∫ +∫ ] 0 T 2 dd m m m m m m t 2T t1 t2 tsi t3 T V is (ohmic)dt + is (sat)dt + is (off)dt is (off)dt + is (sat)dt + is (ohmic)dt t1 t2 tsi t3 ⎡ ⎤ = ⎢ + ⎥ ⎢ ⎥ ⎢⎣ ⎥⎦ ∫ ∫ ∫ ∫ ∫ ∫ 55 ( ) ( ) ( ) ( ) ( ) m m1 m 0 m m 1 m 0 m m 2 m 1 m m 2 m 1 m m 3 m si m m 3 dd SG (ohmic) G (t ) G (t ) ohmic SD (ohmic) D (t ) D (t ) ohmic SG (sat) G (t ) G (t ) sat SD (sat) D (t ) D (t ) sat SG (sat) G (t ) G (t ) sat SD (sat) D (t ) D V C V V C V V C V V C V V C V V C V V = {−⎡⎣ ⋅ − ⎤⎦ − ⎡⎣ ⋅ − ⎤⎦ − ⎡ ⋅ − ⎤ − ⎡ ⋅ − ⎤ − ⎣ ⎦ ⎣ ⎦ ⎡ ⋅ − ⎤ − ⋅ − ⎣ ⎦ ( ) ( ) ( ) m si m m m 3 m m m 3 (t ) sat SG (ohmic) G (T) G (t ) ohmic SD (ohmic) D (T) D (t ) ohmic C V V C V V } ⎡ ⎤ − ⎣ ⎦ ⎡ ⋅ − ⎤ − ⎡ ⋅ − ⎤ ⎣ ⎦ ⎣ ⎦ (4.4) Where the lumped capacitors CSGm and CSDm in ohmic region are different from CSGm and CSDm in saturation as shown in Table 1. The simplified form in (4.4) allows a direct evaluation to the channel capacitive currents knowing only the initial and final voltage at drain and gate terminal with the linearized channel capacitances model. 4.2 Energy per cycle Calculation Total energy dissipation in the inverter is computed from the sum of turnoff energy, turnon energy, and switching energy of parasitic capacitors of transistors connected to the power supply. Average power in (4.5), approximated by the piecewise linear model for a CMOS circuit, is equivalent to energy per cycle. Therefore, energy per cycle is used interchangeably with the average power. avg (EIvdd (off ) EIvdd (on) Eivdd ) P = 1 T ⋅ + + (4.5) 4.2.1 Energy Per Cycle Evaluation by the Model Table 2 is an example of computing energy per cycle from the power supply for the inverter in Figure 4.5. Energy per cycle simulation of the inverter was calculated by the program in appendix III. The program computes the energy of the power supply 56 current from the sum of piecewise linear transistor current across each operating region for a complete cycle. Turnoff energy is denoted as EIvdd(off), and Turnon energy is denoted as EIvdd(on), and switching energy of the parasitic capacitances is denoted as Eivdd. Sum of turnoff energy, turnon energy, and switching energy of parasitic capacitors is the average power. Figure 4.5 Energy per cycle calculation of inverter by the model with TSMC 0.18μm process TTin (Picosec.) Input Transition E Ivdd(off) (0→1) E Ivdd(on) (1→0) E ivdd (0→1) E ivdd (1→0) Σ E (Energy per cycle predicted by Model) 1000 5.00E13 1.34E12 4.57E14 2.66E14 1.821E12 900 4.37E13 1.32E12 4.57E14 2.66E14 1.741E12 800 3.76E13 1.31E12 4.57E14 2.66E14 1.662E12 700 3.15E13 1.29E12 4.57E14 2.66E14 1.583E12 600 2.54E13 1.27E12 4.57E14 2.66E14 1.506E12 500 1.96E13 1.25E12 4.57E14 2.66E14 1.431E12 450 1.67E13 1.25E12 4.57E14 2.66E14 1.395E12 400 1.39E13 1.24E12 4.57E14 2.66E14 1.360E12 350 1.12E13 1.23E12 4.57E14 2.66E14 1.327E12 300 8.63E14 1.23E12 4.57E14 2.66E14 1.294E12 250 6.21E14 1.22E12 4.57E14 2.66E14 1.264E12 200 4.02E14 1.22E12 4.57E14 2.66E14 1.237E12 150 2.13E14 1.21E12 4.57E14 2.66E14 1.213E12 130 1.48E14 1.21E12 4.57E14 2.66E14 1.205E12 110 9.24E15 1.21E12 4.57E14 2.66E14 1.198E12 100 6.78E15 1.21E12 4.57E14 2.66E14 1.195E12 90 4.59E15 1.21E12 4.57E14 2.66E14 1.192E12 Table 2 Energy per cycle simulation of inverter in Fig.4.5 using PWL model for various input transition time TTin from 1000ps to 20ps 57 4.2.2 Energy per cycle simulation in SPICE In SPICE, energy per cycle of a circuit can be simulated from the power supply or the transistor devices in the circuit. In Table 3, the SPICE shows an inconsistency of energy per cycle evaluated from the power supply and devices in the same circuit. Since the BSIM3v3 is a chargeconserving transistor model, the average power supply current from the power supply in SPICE is used as a reference to confirm the model’s accuracy. TTin(Picosec.) Simulated energy per cycle from inverter transistors Simulated energy per cycle from inverter power supply Energy per cycle predicted by Model 1000 1.914e12 1.895e12 1.821E12 900 1.822e12 1.803e12 1.741E12 800 1.734e12 1.712e12 1.662E12 700 1.647e12 1.623e12 1.583E12 600 1.563e12 1.537e12 1.506E12 500 1.482e12 1.455e12 1.431E12 450 1.444e12 1.416e12 1.395E12 400 1.408e12 1.377e12 1.360E12 350 1.373e12 1.341e12 1.327E12 300 1.340e12 1.306e12 1.294E12 250 1.309e12 1.274e12 1.264E12 200 1.281e12 1.245e12 1.237E12 150 1.258e12 1.220e12 1.213E12 130 1.250e12 1.211e12 1.205E12 110 1.243e12 1.204e12 1.198E12 100 1.240e12 1.200e12 1.195E12 90 1.238e12 1.197e12 1.192E12 Table 3 Comparisons of energy per cycle predictions in SPICE and PWL model for the inverter in Fig.4.5 4.3 Model Accuracy of An Inverter Driving Load Capacitance An inverter driving different load capacitances is used to test for the accuracy of piecewise linear model for the average power evaluation. The model accuracy is measured with reference to the SPICE energy per cycle simulation from the power supply 58 in a standard 0.5μm process and a deep submicron 0.18μm process. The first circuit is the inverter driving a100 fF load capacitance, and the second circuit is the inverter driving inverter load. There are two reasons of choosing a large output capacitor and a small capacitive load. First, the large load capacitance has much larger impact on the transistor zeroorder switching current than the channel storage charge in the channel, so that the zeroorder switching current model can be measured for its accuracy in predicting the turnoff (short circuit) power and average turnon power. Also, the accuracy of the model parameters for the zeroorder switching current can be justified while the effect of the channel capacitances is not included. However, adjusting the model parameters only for the shortcircuit current as predicted in the SPICE would also affect the model accuracy to evaluate the turnon energy. Therefore, the model parameters are not optimized for the individual zeroorder and firstorder switching currents, but the model parameters are averaged to evaluate an average switching transient currents drawn from the power supply. 4.3.1 Model Accuracy in AMI CMOS 0.5μm Process (Lmin = 0.6μm) K is a ratio of pFET transistor width to nFET transistor width. K has 1, 2, and 4 for different inverter transistor ratio. Figure 4.6, 4.7, and 4.8 is the energy per cycle simulation predicted by the model in comparisons with the SPICE. 59 Figure 4.6 Accuracy of the PWL model in inverter gate (K = 4) driving 100fF load Figure 4.7 Accuracy of the PWL model in inverter gate (K = 2) driving 100fF load 60 Figure 4.8 Accuracy of the PWL model in inverter gate (K = 1) driving 100fF load 4.3.2 Model Accuracy in TSMC CMOS 0.18μm Process (Lmin = 0.18μm) Testing the accuracy and validity of the model in different CMOS process is to confirm the portability of the piecewise linear model. Accuracies of the piecewise linear model shows the excellent agreements in high frequencies with the SPICE’s predictions in TSMC 0.18μm process while a different set of model parameters for TSMC 0.18μm process are used. Figure 4.9 Accuracy of the PWL model in inverter gate (K = 4) driving 100fF load 61 Figure 4.10 Accuracy of the PWL model in inverter gate (K = 2) driving 100fF load The piecewise linear model shows that average power prediction for large input transitions at low switching frequencies is less accurate than small transition time in the high frequencies. The results indicate that the shortcircuit current is dominant and underestimated for slow inputs. Inaccuracy of the piecewise linear model for slow inputs is twofolds. First, the zeroorder switching current underestimates the current waveform predicted by SPICE due to an approximated transistor current model less accurate in ohmic region than the current predicted by the SPICE. Second, the conductance and transconductance is chosen to match the IV characteristics of the SPICE BSIM3v3 model in a region of large current and a region of small current, thus, the accuracies of the average power predictions in some circuit topologies may be better than the others for the same input slopes. However, overall accuracy for slow inputs is fairly well controlled within 10% error of SPICE in average for all circuits under tests. 62 4.4 Model Accuracy of Inverter Driving Inverter Gate Load Figure 4.11 Inverter driving gate load Load capacitance is not the dominant factor any more since the inverter gate capacitance is comparable to the driver inverter size. The channel capacitive current from the parasitic capacitances is comparable to the zeroorder switching current drawn from the power supply current when the inverter driving a small load, and now the channel capacitive current has more impacts on the average power than previous case for the inverter driving large capacitance load. 4.4.1 Model Accuracy in AMI CMOS 0.5μm Process (Lmin = 0.6μm) Figure 4.12 Accuracy of the PWL model in inverter gate K = 2 driving inverter load (WP/Wn=2.4μm/2.4μm L=0.6μm) 63 Figure 4.13 Accuracy of the PWL model in inverter gate K=1 driving inverter load (WP/Wn=2.4μm/2.4μm L=0.6μm) 4.4.2 Model Accuracy in TSMC CMOS 0.18μm Process (Lmin = 0.18μm) Figure 4.14 Accuracy of the PWL model in inverter gate driving inverter load (K = 4) 64 Figure 4.15 Accuracy of the PWL model in inverter gate driving inverter load (K = 2) Figure 4.16 Accuracy of the PWL model in inverter gate driving inverter load (K = 1) 4.5 Summary This chapter has illustrated the simplified transistor switching current model in predicting the average power dissipation of the inverter driving different load capacitances. As indicated by [8], modeling of the CMOS transistors as series of resistances and capacitances can approximate the transistor performances very accurately in digital CMOS applications. Even though the transistor in the ohmic region is not as accurate as the transistor in saturation, the piecewise linear model has achieved average power predictions within 5% of errors of SPICE for input transition times below 500pico 65 second. It is encouraging that the simplified switching current (IV) and (CV) models can achieve the target accuracy when the input is switching in a high speed, which is common for most large integrated circuits. There are two discrepant average power simulations from SPICE in each plot. The average power predicted by the piecewise linear model is much closed to the SPICE’s average power evaluated from the power supply current than from the total transistor devices. The discrepancies in the average power simulations from the SPICE are reduced when the transistors shrink to a 0.18μm process from a 0.5μm process. 66 CHAPTER 5 AVERAGE POWER ANALYSIS OF COMPLEX GATES WITH A PIECEWISE LINEAR MODEL 5.0 Introduction In Chapter four, the piecewise linear model is applied to the inverter gate, and the piecewise linear model for the average power evaluation is within 10% average error of SPICE for a wide range of input slopes, different capacitor loads, different transistor sizes and load capacitances, and different process technologies in submicron AMIS 0.5μm and deep submicron TSMC0.18μm process. The piecewise linear model is applicable not only to predict a simple inverter gate, but also extendable to other circuit topologies. The piecewise linear model has shown its scalable and portable among submicron and deep submicron processes by using different set of model parameters. Appendix II includes model parameters used in piecewise linear model for AMIS 0.5μm and TSMC 0.18μm processes. 5.1 Average Power Analysis of Twoinput NAND Gate In this chapter, the applications of the piecewise linear model are extended beyond an inverter gate analysis. Complex gates, such as a twoinput NAND gate and an OAI gate are common digital CMOS circuits and are used as the test circuits in this 67 chapter. NAND gate uses the same model as to evaluate the power supply current into the circuit, but the two dimensional G and C matrices is written according to the drain nodes in each piecewise linear region. Similar to the inverter analysis, the power supply current drawn from the supply into the circuit is evaluated from pFETs that are switching. The average power predicted by the model is compared with SPICE by varying input slopes, different transistor sizes, output loads, and process technologies. 5.1.1 Twoinput NAND Gate Driving Load Capacitance Fig. 5.1 is the twoinput NAND gate with input signals A and B. The gate drives a constant 100fF load. Average power of NAND gates is evaluated when only input A is switching for a complete cycle. Multiple inputs can be handled by making in V a column matrix, but the output node driving the load is critical for evaluating average power from the power supply. The pullup parallel connected transistors are the same size and so does the pulldown series connected transistors. The width ratio of the PMOS transistor to NMOS transistor changes from K = 4, 2, and 1. Figure 5.1 Twoinput NAND driving load capacitance 68 Energy per cycle is calculated with different input transition time and a different load for the twoinput NAND with the input signal ‘A’ switched from a cycle. Switching input signal ‘B’ resemble an inverter driving a capacitive load. Therefore, switching B is not discussed. 5.1.2 Model Accuracy of Twoinput NAND in AMI 0.5μm Process (Lmin = 0.6μm) The average power of NAND gate is evaluated when the input A is switching for a complete cycle and the input of the lower NMOS transistor stay high. Fig. 5.2 shows the average power of NAND gates against various input slopes. Input rise time varies from 50ps to 1500ps and width ratio of PMOS transistors to NMOS transistors varies from K = 4, 2, and 1. Average error was within 3% of SPICE for small input slopes at the high switching frequencies and within 10% for large input slopes at the slower switching frequencies. Figure 5.2 Accuracy of the PWL model for twoinput NAND K = 4 (Wp/Wn = 9.6μm/2.4μm) driving 100fF load 69 Figure 5.3 Accuracy of the PWL model for twoinput NAND K = 2 (Wp/Wn = 4.8μm/2.4μm) driving 100fF load Figure 5.4 Accuracy of the PWL model for twoinput NAND gate K = 2 (Wp/Wn = 4.8μm/2.4μm) driving inverter load 70 Figure 5.5 Accuracy of the PWL model for twoinput NAND gate K = 1 driving inverter load (Wp/Wn = 2.4μm/2.4μm) 5.1.3 Model Accuracy of Twoinput NAND in TSMC 0.18μm Process Figure 5.6 Accuracy of the PWL model for twoinput NAND gate K = 4 (Wp/Wn = 2.88μm/0.72μm) driving 100fF load 71 Figure 5.7 Accuracy of the PWL model for twoinput NAND gate K = 2 (Wp/Wn = 1.44μm/0.72μm) driving 100fF load Figure 5.8 Accuracy of the PWL model for twoinput NAND gate K = 1 (Wp/Wn = 0.72μm/0.72μm) driving 100fF load 72 Figure 5.9 Accuracy of the PWL model for twoinput NAND gate K = 4 driving inverter load (Wp/Wn=2.88μm/1.44μm L=0.18μm) Figure 5.10 Accuracy of the PWL model for twoinput NAND gate K = 2 driving inverter load (Wp/Wn=1.44μm/0.72μm L=0.18μm) 73 Figure 5.11 Accuracy of the PWL model for twoinput NAND gate K = 1 driving inverter load (Wp/Wn=0.72μm/0.72μm L=0.18μm) 5.2 Average Power Analysis of OAI Gate Fig. 5.12 is an OAI gate with input A, B, and C. Input A = 0→1, B = 1, and C = 0 are assumed when the average power of OAI gates is evaluated. The model allows multiple inputs by making VIN as a column matrix, but only the supply node and the drain of pFET connected to the power supply are necessary for evaluating average power from the power supply. The width of PMOS transistors to NMOS transistors varies from K = 4, 2, 1 driving a constant 100fF load with different input slopes. A submicron 0.5μm process and deep submicron 0.18μm process parameters are used to confirm the model’s accuracy. 5.2.1 Average Power Analysis of OAI Gate Driving Load Capacitance 74 Figure 5.12 OAI gate driving 100fF load 5.2.1.1 Model Accuracy of OAI gate in AMI 0.5μm Process Average power of OAI gate is evaluated based on one switching cycle. Inputs A switches for a complete cycle while the input B is tied to VDD and the input C is tied to ground. Accuracy for OAI gates driving a constant 100fF with different transistor K ratio is still within 3% error of SPICE for small input slopes and in 10% error of SPICE for large input slopes in average. 75 Figure 5.13 Accuracy of the PWL model in OAI gate K = 4 (Wp/Wn = 9.6μm/2.4μm) driving 100fF load in 0.5μm process Figure 5.14 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 4.8μm/2.4μm) driving 100fF load in 0.5μm process 76 Figure 5.15 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 2.4μm/2.4μm) driving 100fF load in 0.5μm process 5.2.1.2 Model Accuracy of OAI Gate in TSMC 0.18μm Process Threeinput OAI gate is tested in TSMC 0.18μm process as well to measure the model’s accuracy in different process technologies. Accuracy of OAI gate driving a constant 100fF with different transistor K ratio is within 5% of SPICE for small input slopes and within 10% of SPICE for large input slopes. 77 Figure 5.16 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 2.88μm/0.72μm) driving 100fF load in 0.18μm process Figure 5.17 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 1.44μm/0.72μm) driving 100fF load in 0.18μm process 78 Figure 5.18 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 0.72μm/0.72μm) driving 100fF load in 0.18μm process 5.2.2 Average Power Analysis of OAI Gate Driving Inverter Load In this case, average power of OAI gate is evaluated with input, A, which switches for a complete cycle whiles input, B, tied to VDD and input, C, and tied to the ground. Accuracy of the OAI gates driving inverter with different inverter ratio of K = 4, 2, and 1 is compared with SPICE with the same designs. Averaged error is within 3% of SPICE for small input slopes and within 10% of SPICE for large input slopes. 79 Figure 5.19 OAI gate driving different inverter loads 5.2.2.1 Model Accuracy of OAI Gate in AMI 0.5μm Process Figure 5.20 Accuracy of the PWL model in OAI gate K = 4 (Wp/Wn = 9.6μm/2.4μm) driving inverter load K=1 in 0.5μm process 80 Figure 5.21 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 4.8μm/2.4μm) driving inverter load K=1 in 0.5μm process Figure 5.22 Accuracy of the PWL model in OAI gate K = 1 (Wp/Wn = 2.4μm/2.4μm) driving inverter load K=1 in 0.5μm process 5.2.2.2 Model Accuracy of OAI Gate in TSMC 0.18μm Process 81 Figure 5.23 Accuracy of the PWL model in OAI gate K = 4 (Wp/Wn = 2.88μm/0.72μm) driving inverter load K= 4 in 0.18μm process Figure 5.24 Accuracy of the PWL model in OAI gate K = 2 (Wp/Wn = 1.44μm/0.72μm) driving inverter load K= 2 in 0.18μm process 82 CHAPTER 6 6.0 CONCLUSION The scaling of semiconductor process technologies has been the fuel that boosts millions of transistors to be incorporated in a single digital integrated circuit, and power dissipation is becoming a critical issue when more transistors are integrated and operated in high frequencies. Unfortunately, as the complexity of integrated circuits increases, simulating circuits with an accurate yet simple transistor model becomes very challenging. In general, lower levels of simulation utilize more detailed transistor model and provide greater accuracy, such as SPICE. However, increased accuracy is usually achieved at the expense of long computation times. This dissertation has proposed a piecewise linear transistor model to evaluate the total power dissipation from the power supply current into the circuits. The piecewise linear model includes the effect of signal input slope into the shortcircuit power and dynamic power computation. The innovation of the model in power evaluation is to include the firstorder channel capacitive currents from the transistor parasitic capacitances into a power calculation. Extensive comparisons have been done between the piecewise linear model and the SPICE BSIM3v3 model in the circuit simulation. The test circuit included an inverter gate, a twoinput NAND gate, and an OAI gate driving different load capacitances. Excellent accuracies of the piecewise linear model have been achieved for the average 83 power predictions under those test circuits for both AMI 0.5μm process and the deep submicron TSMC 0.18μm process. The proposed model has the advantage of simulation speed over SPICE running BSIM3 model, because the piecewise linear model is used to compute the power supply current into a large circuit partitioned into many resistively connected regions with only a few number of transistors and capacitors. Therefore, matrices operation is necessary only when solving the power supply current into the resistively connected nodes from the transistors connected to the power supply. However, simulation speed of the proposed model will be slower than the switchedresistor model in IRSIM since the switchedresistor model has not modeled the transistors in saturation, input slope effects, and accurate circuit dynamics comparable to SPICE’s prediction, but the proposed model will be much accurate than the switched resistor model in a power calculation. 6.1 FINDINGS Simulation inconsistencies were found in SPICE when simulating the average power dissipation by the power supply and simulating average power consumption by the transistor devices in the inverter driving different load capacitances. Discrepancies exist when more complex gates were simulated for average power, such as a twoinput NAND gate and OAI gate driving different loads. The average power provided to the circuit from the power supply is less than the sum of the average power dissipated by every transistor device in the same circuit. The discrepancies of average power from SPICE simulations come from the zeroorder transistor model in SPICE, which computes instantaneous power with the product of the zeroorder instantaneous current and drainsource voltage. 84 Solving the power simulation problem in SPICE requires an energy conserving transistor model, which is beyond the scope of this dissertation. Since the BSIM3v3 model is a well known charge conserving transistor model, accuracies of the proposed model were tested with references to the power supply current entering the circuits or the total average power of the power supply from the SPICE simulation. That is the same approach with the piecewise linear model to evaluate the total average power of a circuit from the power supply current. The piecewise linear approximations of average power to an inverter gate, a twoinput NAND gate and an OAI gate driving different load capacitances with various transistor sizes were validated by comparing the model predicted average power with the average power simulation from the power supply in SPICE, and the accuracies were within 5% average error of SPICE for fast inputs and within 10% for most slow inputs. More complex gates, threeinput OAI gate with different transistor sizes and driving different load conditions in a standard CMOS 0.5μm and 0.18μm technologies, were also verified with the same range of model accuracy. 6.2 FUTURE WORKS The main focus of this dissertation is the accuracy of the simple piecewise linear current transistor model in predicting the average power supply current and power for a standard CMOS circuit. Comprehensive tests are done for simple CMOS circuits to verify the proposed model functionality to compute the switching transient power consumption. However, the gate induced subthreshold leakage current has become a major power dissipation contributor of the total power dissipation, and in many scaled technologies leakage contributes 30% to 50% of the overall power under nominal 85 operating conditions, and leakage is becoming significant compared to switching transient power [38]. Therefore, modeling leakage current is significant for scaled CMOS technologies. The piecewise linear model is applicable for average power evaluation to any general CMOS circuits. More works are needed to verify the proposed model with a very large CMOS circuit. 86 BIBLIOGRAPHY [1] “ITRS Roadmap”, http://public.itrs.net/ [2] “MOSIS”, http://www.mosis.com/ [3] Avant StarHspice Manual Release 1999.4 Dec.1999 [4] Cheng Y., Hu, C., Mosfet Modeling & BSIM3 User’s Guide, Boston, MA, Kluwer Academic Publishers, 1999 [5] Ward D.E. “ChargeBased Modeling of Capacitance in MOS Transistors,” Ph.D. Dissertation, Stanford University, CA, 1981 [6] Ward D.E. and Dutton R.W., “A Charge Oriented Model for MOS Transistor Capacitance,” IEEE J. Solid State Circuits, vol. SC13, pp703708, 1978 [7] Meyer J.E., “MOS Models and Circuit Simulation,” RCA Review, vol.32, pp.42 63, 1979 [8] Neil H.E. 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H., Kramer J., Indiveri G., Analog VLSI: Circuits and Principles, MIT Press, Cambridge, Massachusetts, 2002 [22] Sakurai, T., Newton, A.R., “AlphaPower Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formula,” IEEE J. Solid State Circuits, pp584594 [23] Vemuru, S.R., and Scheinberg N. “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. Circuits and Systems, pp762765, 1994 [24] Hirata, A., Onodera, H., and Tamara, H., “Estimation of ShortCircuit Power Dissipation and Its Influence on Propagation Delay for Static CMOS Gates,” IEEE Proc. International Symposium on Circuits and Systems, pp751754, 1996 [25] Tsividis Y., Operation and Modeling of the MOS Transistor, 2nd E., McGraw Hill, 1999 [26] William Liu, Mosfet Model for SPICE Simulation, John Wiley & Sons, 2001. [27] Zill, D.G., A First Course in Differential Equations, Brooks/Cole Publishing Company, 1997 [28] Johnson, Louis, G., “Circuit Power Consumption Model,” lecture note, http:// fp.okstate.edu/lgjohn/6263/lectures/powmod.pdf, 2005 [29] Cirit, M. A., “The Meyer Model Revisited: Why is Charge Not Conserved,” IEEE Trans. on ComputerAided Design, Vol.8, No.10, 1989 [30] Fossum, J.G., Jeong H., Veeraraghavan S., “Significance of the ChannelCharge Partition in the Transient MOSFET Model,” IEEE Trans. on Electron Devices, Vol., ED33, No.10, 1986 89 [31] Harry Veendrick, “DeepSubmicron CMOS ICs from basics to ASICs,” Kluwer Academic Publishers, 2nd Edition, 2000 [32] Yang P., Epler D.B., Chatterjee P.K., “An Investigation of the Charge Conservation Problem or Mosfet Circuit Simulation,” IEEE Journal of SolidState Circuits, Vol. SC18, No.1, Feb., 1983 [33] L.G. Johnson, “Delay of CMOS Logic Gates” handouts, pp128, 2005 [34] IRSIM version 9.7 switchlevel simulator, http://opencircuitdesign.com/irsim. [35] Trevor Mudge, “Power: A firstclass architectural design constraint,” IEEE computer, pp 5258, 2001 [36] Jian Chang, “A Piecewise Linear Delay Modeling of CMOS circuits,” Ph.D. dissertation, Oklahoma State University, 2006 [37] Sameer, L.G. Johnson, “Quasistatic first order energy conserving MOSFET model,” Oklahoma State University, to be published. [38] Siva G. Narendra, Anantha Chandrakasan, “Leakage in nanometer CMOS technologies,” Springer, 2006 [39] Russell Kao, Mark Horowitz, “Piecewise linear model for RSIM,” Western research laboratory, WRL technical note TN40, May 1995 [40] Nihar R. M, “Gate triggering: a new framework fro minimizing glitch power dissipation in static CMOS ICs, IEEE 2000 [41] Dirk Rabe, “Short circuit power consumption of glitches,” ISLPED, IEEE 1996 [42] M. Favalli and L. Benini, “Analysis of glitch power dissipation in CMOS ICs,” IEEE 2000. 90 APPENDICES 91 Appendix A I. AVERAGE POWER SIMULATIONS IN SPECTRE SPICE I.1 SPICE Simulation Inconsistency of Average Power In the SPICE, average power measured from the power supply or from devices is computed from the integration of instantaneous power waveform over one switching cycle. We ran into simulation discrepancies in SPICE between simulating average power dissipation from the power supply and from the transistor devices in the same circuit (Figure A.1 and A.2). SPICE shows that average power dissipation by the devices is higher than the average power actually drawn from the power supply. The discrepancies may come from the zeroorder quasistatic SPICE transistor model, which computes power consumption from a quasistatic zeroorder instantaneous current multiplied by drainsource voltage. Overestimation of average power in SPICE transistor models leads to the issue of nonenergy conserving transistor model in SPICE, which neglects of the firstorder channel capacitive currents. The transistor model (BSIM) and Spectre simulator has the same problem by not taking into account of the firstorder channel capacitive currents into the transistor parasitic capacitances as indicated in HSPICE simulator manual [3]. 92 Average power dissipation simulation from the power supply can be written as equations (I.1), and the average power simulation from devices can be written as equation (I.2). DD 1 T E Pavg ( vd d ) i vd d ( t ) * V ( t )d t T 0 T = ∫ = (I.1) n n Dnn Dnn Dpn Dpn m 1 m 1 1 T 1 T Pavg(device) i (t) *V (t)dt i (t) *V (t)dt T = 0 T = 0 = Σ ∫ + Σ ∫ (I.2) SPICE simulation discrepancies are shown in Figure A.1 and A.2. Figure A.3 and A.4 demonstrate the simulation tool of SPECTRE SPICE in simulating the average power of inverter from the power supply and the transistor devices respectively. Figure A.1 Average Power Simulation of Inverter in SPICE 93 Figure A.2 SPICE power waveform/cycle of Fig.A.1 with 1ns input slope. Dot in red: total device power; solid green line: supply power. Dashdot in blue: the supply current. I.2 SPECTRE SPICE circuit net list for an inverter driving 100fF load simulator lang=spectre model ami06N bsim3v3 type = n +version = 3.1 tnom = 27 tox = 1.41E8 model ami06P bsim3v3 type = p +version = 3.1 tnom = 27 tox = 1.41E8 // Library name: inverter_lib // Cell name: inverter // View name: extracted _inst0 (OUT IN ps pb) ami06P w=9.6e06 l=6e07 as=1.44e11 ad=1.44e11 \ ps=1.26e05 pd=1.26e05 m=1 region=sat _inst1 (OUT IN gnd gnd) ami06N w=2.4e06 l=6e07 as=3.6e12 ad=3.6e12 \ ps=5.4e06 pd=5.4e06 m=1 region=sat _inst2 (OUT gnd) capacitor c=100e15 m=1 // power supplies VPWR(vdd 0) vsource dc=5.0 VGND(gnd 0) vsource dc=0.0 94 // inputs VIN(IN 0) vsource dc=5.0 type=pulse val0=5 val1=0\ period=13n rise=1500p fall=1500p width=5n // current test meter VTEST1(vdd ps) vsource dc=0.0 type=pulse val0=0 val1=0 VTEST2(vdd pb) vsource dc=0.0 type=pulse val0=0 val1=0 opts1 options pwr=total save=all setting1 options save=all opts options currents=all opts2 options pwr=total save=all save _inst0:pwr save _inst1:pwr save VPWR:pwr save VGND:pwr // controls inverter tran step=1p start=0n stop=13n errpreset=conservative save OUT IN I.3 Average Power Simulation in SPECTRE Figure A.3 Average Power Simulation from the Power Supply in SPECTRE 95 Figure A.4 Average Power Simulation from Total Device Power in SPECTRE SPICE 96 Appendix B MODEL PARAMETER EXTRACTIONS FOR AMI 0.5μm AND TSMC 0.18μm PROCESSES I. Model Parameters Extraction The piecewise linear current model has a total of six parameters: an , ap , VTn , Tp V , Gsat , andGohmic . The parameters of a piecewise linear transistor model can be extracted directly from SPICE ID − VGS and ID − VDS curves for transistors used in the circuit. There are many techniques associated with VTn and VTp extractions from transistor I/V curves from [4]. The VTn and VTp in the piecewise linear model are extrapolated from SPICE ID − VGS family curves at the maximum slope of VGS curves to IDS = 0 point. The tangent line across IDS = 0 is the threshold voltage on the VGS curve as shown in Fig.B.1 and Fig. B.2. An averaged VTn and VTp in equation (B.1) are computed from the threshold voltages extrapolated from ID − VGS curves. T1 T2 T3 T4 Tm T V V V V ....V V m + + + = (B.1) Transistor ID − VGS curves are generated in SPICE with BSIM3v3 transistor model in a region of greatest current, for AMIS 0.5μm process, 2.5 < VGS < 5.0 and 2.5 < VDS < 5.0 . 97 The rationale is that most of change of voltage at the output of CMOS circuit is proportional to the output transistor biased in the high current range [39], because the rate of voltage change at the output depends on the magnitude of the current. The modeling errors in regions of low drain current (when the transistor in the ohmic region) usually produce smaller timing errors than errors in regions of high current (when the transistor is in saturation) [39]. Hence, the proposed piecewise linear transistor model uses an average value for each parameter to minimize the timing error in regions of high current as indicated in [39]. Figure B.1 Threshold voltage extraction from high VDSN curves in 0.5μm process Figure B.2 Threshold voltage extraction from low VDSN curves in 0.5μm process 98 The maximum slope of the ID −VGS curve is the large signal transconductance of the transistor G. An averaged transconductance was determined by taking the average slopes from ID −VGS curves at highVDS and low VDS curves. Since five ID −VGS curves were plotted at a high VDS and five ID −VGS curves were plotted for a low VDS , a total of four extrapolated G(N)SAT and G(P)SAT were averaged to obtain an average GNSAT , GPSAT. The conductance at the ohmic region for nFET and pFET devices, G(N)OHM , and G(P)OHM, were derived using the same approach with ID −VDS curves. In this case, the average conductance can be computed as equation (B.3) from ID −VDS curves and as shown in Figure 3.3 and Figure 3.4. Similarly, average transconductance (slopes of curves) can be extracted from ID −VGS curves shown in Figure B.1 and Figure B.2. Gnsat1 Gnsat2 Gnsat4 Gn(p)sat 4 + + + = K (B.2) Gohmic1 Gohmic2 Gohmic4 Gn(p)ohm 4 + + + = K (B.3) Quasistatic dc current scaling factors an and ap for nFET and pFET are computed by Gn(p)ohm an(p) Gn(p)sat = (B.4) Appendix II includes all parameters extracted from SPICE simulations in AMI 0.5μm and TSMC 0.18μm process for the piecewise linear model. 99 The model parameters for the piecewise linear (PWL) model were extracted from I/V family curves of various transistor sizes from the AMI CMOS 0.6um submicron technology and a TSMC 0.18μm deep submicron technology. i. Extracted PWL transistor parameters for AMI 0.5μm process Wp (um) Rsp (Ω/ ) VTp (V) ap 1.2 2.1×104 1.8 1.251763 2.4 2.1×104 1.6 1.396283 4.8 2.1×104 1.49 1.348792 9.6 2.1×104 1.386 1.352994 Table B.1 Falling input PMOS parameters for AMI 0.5μm process Wp (um) Rsp (Ω/ ) VTp (V) ap 1.2 3.3×104 1.292 2.9 2.4 3.3×104 1.241 2.8 4.8 3.3×104 1.243 2.0 9.6 3.3×104 1.161 1.2 Table B.2 Rising input PMOS parameters for AMI 0.5μm process 100 Wn (um) Rsn (Ω/ ) VTn (V) an 1.2 1.7×104 1.34 1.38442 2.4 1.7×104 1.1 1.64235 4.8 1.7×104 0.99 1.03714 9.6 1.7×104 0.96 1.4 



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