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FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL By SAMEER SHARMA Bachelor of Science in Electrical Engineering Punjab Engineering College Chandigarh, India 1994 Master of Science in Electrical and Computer Engineering Oklahoma State University Stillwater, Oklahoma December, 2003 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY May, 2008 ~ii~ FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL Dissertation Approved: Dr. Louis G. Johnson Dissertation Adviser Dr. George Scheets Dr. James E. Stine, Jr. Dr. H. K. Dai Dr. Gordon Emslie Dean of the Graduate College ~iii~ TABLE OF CONTENTS CHAPTER PAGE I. INTRODUCTION .................................................................................................................................... 1 1.1 MODELING PROCESS ............................................................................................................ 1 1.2 SCOPE ....................................................................................................................................... 4 1.3 OUTLINE ................................................................................................................................... 5 II. LITERATURE REVIEW ........................................................................................................................ 7 2.1 MEYER’S MODEL ..................................................................................................................... 8 2.2 CHARGE BASED MODELS ................................................................................................... 11 2.3 TRANSCAPACITIVE MODEL .............................................................................................. 15 2.4 MEHMET MODEL ................................................................................................................... 15 III. FIRST ORDER QUASISTATIC CHANNEL CAPACITANCE MODEL .................................... 18 3.1 STEADY STATE OPERATION .............................................................................................. 18 3.2 QUASISTATIC OPERATION ................................................................................................ 19 3.3 MODELING EQUATIONS ...................................................................................................... 21 IV. MOSFET POWER............................................................................................................................... 27 4.1 SOURCES OF POWER DISSIPATION ................................................................................ 28 4.2 POWER AND ENERGY MODELING ISSUES .................................................................... 29 4.3 POWER MEASUREMENT TECHNIQUES .......................................................................... 30 4.4 POWER EQUATIONS ............................................................................................................ 35 4.5 ENERGY FUNCTION CALCULATION ................................................................................. 37 V. FIRST ORDER CURRENT COMPONENTS AND CAPACITANCE CALCULATION .............. 40 ~iv~ CHAPTER PAGE 5.1 FIRST ORDER CURRENT COMPONENTS ....................................................................... 40 5.2 CAPACITANCE DERIVATION .............................................................................................. 42 5.3 EQUIVALENT CIRCUIT ......................................................................................................... 47 VI. COMPARISON AND DISCUSSION .................................................................................................. 49 6.1 MODEL VERIFICATION AND ADVANTAGES .................................................................... 49 6.2 ENERGY PUMPING ............................................................................................................... 50 6.3 TOTAL FIRST ORDER POWER ........................................................................................... 52 6.4 SIMULATION EXAMPLE ........................................................................................................ 52 VII. DEPENDENCE OF THE BSIM ABULK PARAMETER ON THE SOURCE POTENTIAL .... 56 7.1 EVALUATION OF EXTRA CURRENT COMPONENTS .................................................... 57 7.2 SIMULATION EXAMPLE ........................................................................................................ 58 7.3 CONCLUSION ......................................................................................................................... 63 REFERENCES ........................................................................................................................................... 64 APPENDICES ............................................................................................................................................ 72 ~v~ LIST OF TABLES TABLE PAGE Table 3.1 NMOS Zero and First Order Charges and Currents………………….. 25 Table 4.1 Power Equations ………………………………………………………. 37 Table 4.2 Energy Function ………………………………………………………. 39 Table 5.1: Storage and Dissipative Current Components ……………………...... 42 Table 5.3: Total Capacitances…………………………………………………..… 44 Table 5.4: Conserved Capacitances………………………………………………. 45 Table 5.5: Dissipative Capacitances……………………………………………… 46 ~vi~ LIST OF FIGURES FIGURE PAGE Figure 1.1: Energy Imbalance ……………………………………………………. 3 Figure 2.1: Meyer Capacitance Model……………………………………………. 8 Figure 2.2: Channel Current Calculations………………………………………… 9 Figure 2.3: Current Representation in Meyer’s Model……………………………. 11 Figure 2.4: Channel Charge approximation using Ward’s Model………………… 12 Figure 2.5: Transcapacitance Approximation…………………………………… 15 Figure 2.6: Small Signal Representation of Mehmet’s Model……………………. 17 Figure 3.1: Bulk and SOI CMOS Structures…………………………………….... 18 Figure 3.2: Voltage, Charge and Current Waveforms…………………………...... 20 Figure 3.3: Four terminal MOSFET Structures…………………………………… 22 Figure 4.1: Leakage Current Components………………………………………… 28 Figure 4.2: Dynamic Power ………………………………………………………. 30 Figure 4.3: Transient Waveforms …………………………………………………. 31 Figure 4.4: Capacitor based Power Measurement Technique …………………… 34 Figure 4.5: Power Dissipation in MOS Transistor ……………………………….. 34 Figure 4.6: MOS Channel Power Calculation….. ……………………………….. 35 Figure 5.1: First order dissipative and conserved current components ……..……. 41 Figure 5.2: Total, Conserved and Dissipative Capacitances vs vds …….………… 44 Figure 5.3: Equivalent Circuit …………………………………………………… 47 ~vii~ FIGURE PAGE Figure 6.1: Terminal capacitances vs vds ………………………….…….……….. 50 Figure 6.2: Capacitance vs vds …………..………………………………………... 50 Figure 6.3: Gate pumping action……… ……………………………….………... 51 Figure 6.4: Average conserved gate and channel power vs frequency…………. 51 Figure 6.5: Idealized voltage waveforms ……………………………….………. 53 Figure 6.6: Total power vs. frequency……………………………………………. 54 Figure 6.7: Current plots………………………………………….………………. 55 Figure 6.8: Power plots…………….. …………………………………………..... 55 Figure 7.1: Terminal capacitances vs vds ……………………………….………. 59 Figure 7.2: Extra power dissipation …………..…………………………………. 60 Figure 7.3: Threshold voltage and bulk charge parameter……………….……. 61 Figure 7.4: Zero order currents………………………………..……………….…. 61 Figure 7.5: First order currents……… ……………………………….………….. 62 ~viii~ LIST OF SYMBOLS SYMBOLS NAMES qc …………………………………………….. channel charge per unit length qc0 …………………………………………….. zero order channel charge per unit length qc1 …………………………………………….. first order channel charge per unit length qs …………………………………………….. source charge per unit length qd …………………………………………….. drain charge per unit length qg ……………………………………………. gate charge per unit length L ……………………………………………. channel length W ……………………………………………. channel width cox ……………………………………………. oxide capacitance per unit length v fb ……………………………………………. flat band voltage vt0 ……………………………………………. threshold voltage at zero source bias vt ……………………………………………. threshold voltage φ ……………………………………………. fermi potential tox ……………………………………………. oxide thickness vcb ……………………………………………. channel terminal voltage vgb ……………………………………………. gate terminal voltage vsb ……………………………………………. source terminal voltage ~ix~ SYMBOLS NAMES vdb ……………………………………………. drain terminal voltage 1 k ……………………………………………. body effect coefficient 2 k ……………………………………………. body effect coefficient Ic0 ……………………………………………. zero order (static) current ID ……………………………………………. static drain current IS ……………………………………………. static source current IG ……………………………………………. static gate current IB ……………………………………………. static substrate current I (t) ……………………………………………. total channel current id1 ……………………………………………. first order drain current is1 ……………………………………………. first order source current ig1 ……………………………………………. first order gate current ib1 ……………………………………………. first order substrate current id1,cons……………………………………………. first order conserved drain current is1,cons ……………………………………………. first order conserved source current id1,diss ……………………………………………. first order dissipative drain current is1,diss……………………………………………. first order dissipative source current Pc0 ……………………………………………. average power P ……………………………………………. total instantaneous power Pc ……………………………………………. instantaneous channel power Pc0 ……………………………………………. static power ~x~ SYMBOLS NAMES Pc1,diss……………………………………………. first order dissipative channel power Pc1,cons……………………………………………. first order conserved channel power Pg1,cons……………………………………………. first order gate power CL ……………………………………………. externally load capacitor Cgb ……………………………………………. gate to bulk capacitance Cgs ……………………………………………. gate to source capacitance Cgd ……………………………………………. gate to drain capacitance Csb ……………………………………………. source to bulk capacitance Csg ……………………………………………. source to gate capacitance Csd ……………………………………………. source to drain capacitance Cdb ……………………………………………. drain to bulk capacitance Cdg ……………………………………………. drain to gate capacitance Cds ……………………………………………. drain to drain capacitance Ccsb ……………………………………………. conserved source to bulk capacitance Ccsg ……………………………………………. conserved source to gate capacitance Ccsd ……………………………………………. conserved source to drain capacitance Ccdb ……………………………………………. conserved drain to bulk capacitance Ccdg ……………………………………………. conserved drain to gate capacitance Ccds ……………………………………………. conserved drain to drain capacitance Cdsb ……………………………………………. dissipative source to bulk capacitance ~xi~ SYMBOLS NAMES Cdsg ……………………………………………. dissipative source to gate capacitance Cdsd ……………………………………………. dissipative source to drain capacitance Cddb ……………………………………………. dissipative drain to bulk capacitance Cddg ……………………………………………. dissipative drain to gate capacitance Cdds ……………………………………………. dissipative drain to drain capacitance Pc1, diss, B…………………………………………. BSIM first order dissipative channel power Pc1, cons, B …………………………………………. BSIM first order conserved channel power Pg1, cons, B…………………………………………. BSIM first order gate power Pg1,cons Extra ……………………………………….. extra first order channel conserved power Pc1,diss Extra ……………………………………….. extra first order channel dissipative power P1,cons Extra ………………………………………. extra first order conserved power ~xii~ ACKNOWLEDGMENTS I would like to express sincere thanks to my advisor Dr. Louis G. Johnson for his guidance, encouragement and the research opportunity. I would also like to extend appreciation to my committee members Dr. George Scheets, Dr. Yumin Zhang, Dr. James E. Stine Jr. and Dr. H. K. Dai for their invaluable knowledge and guidance. Additional thanks go to all my colleagues in VLSI Design Group for helpful discussions on circuit simulation, device modeling and power estimation. Finally, I would like to acknowledge the support from my wife Srijana and two daughters Vidhi and Tanya for their patience and encouragement throughout my studies. ~1~ CHAPTER I I. INTRODUCTION 1.1 MODELING PROCESS Modeling is a process of accurately representing the behavior of a device to be used in a circuit simulator. Designers need these reliable and accurate models for circuit development. With the growth of CMOS technology, MOSFET modeling has taken a centre stage and the accurate modeling of MOS transistor channel capacitance has been an ongoing effort. First, Meyer’s [1.1] reciprocal gatecapacitive model, then Ward’s [1.2] chargebased, nonreciprocal capacitance model have been used. Many papers have also been written on the comparison of these models. Some [1.31.6] claim that Meyer’s model fails due to charge nonconservation which justifies the usage of chargebased models while others claim [1.71.9] that the charge nonconservation is mainly due to the faulty mathematical modeling of the simulation software. As pointed out by Fossum [1.10], it is not clear whether we have explored all other possibilities. We may be able to achieve a better result with a different channel partition or may be with no partition at all. Recent papers on fielddependent mobility [1.33] and laterally asymmetrical doping [1.34] have now shown inconsistencies in Ward’s model, which artificially partitions the channel charge into the source and the drain components. Many ideas have also been suggested for estimation of energy and power taking into consideration the input slew dependency [1.11], propagation delay [1.12], short circuit power [1.13] and supply current measurements [1.141.16]. One of the most popular and widely adapted, Berkeley ShortChannel IGFET (BSIM) Capacitive Model [1.17, 1.18] has tried to include many of the above mentioned modeling techniques to estimate the behavior of Insulated Gate Field Effect Transistors (IGFET). However, the BSIM ~2~ capacitive model fails to include the first order transcapacitive currents due to the charge redistribution in the channel that causes the actual output waveform and the delay to deviate from the BSIM stimulation results [1.19]. In reality, the MOS device is a highly nonlinear four terminal device and modeling it as a simple energy storage device leaves a lot to be desired. When the inversion layer is formed, the IR drop from the resistive components and charge redistribution current causes power dissipation in the channel. This makes the assumption that the capacitive model does not contribute any net power dissipation in the channel inconsistent for use in energy prediction. If the BSIM model is not consistent, one may ask as why it is still being used? The reason is: the BSIM quasistatic models are analog friendly, continuous and have good IV characteristic. These IV models are derived from the channel charge that is calculated correctly to the first order. Power is also derived from the channel charge. The problem, however, is that the power is derived only to zero order. In other words, the BSIM capacitive model calculates static power dissipation, which is nothing but the multiplication of zero order current and steady state voltage. Though the BSIM capacitive model includes first order corrections in dynamic power calculation, it leaves out some important terms. We can think the process of dynamic power calculation of the BSIM model as being nothing but an easy way of calculating the zero order power by using the change in the energy of the capacitors during charging and discharging. The BSIM capacitive model assumes that the first order terms are the energy storage terms (like capacitors and inductors) that do not dissipate energy, which in reality is not the case. Hence it is not appropriate to look at the change in the energy of the capacitors in the channel as there is no energy function for the channel. It causes an error and gives a different number for power from the supply power than the dissipated power from all the devices, clearly a violation of energy conservation principles. This effect is pointed out in Fig. 1.1 which is a plot of switching frequency and the energy imbalance for different width ratios of transistors in a inverter. As seen, for higher switching frequencies (small rise/fall times) the energy imbalance is more pronounced. ~3~ In reality, it is very difficult to estimate the usefulness of SPICE simulation in the power estimation of a real circuit. In digital applications, it is well known that the glitches can contribute half the power, and how accurately we can predict the power spike depends on how accurately we can predict the glitches. Therefore, it did not make a whole lot of difference, as SPICE was not predicting the power accurately anyway. Even if it were able to predict the power, it is not possible to extrapolate to a real circuit with glitches that are not exactly the same as SPICE calculated. However, in the world of Pentiums [1.20], Core Duos [1.21] and QuantiSpeed Architecture processors [1.22], where the gates are switching around 300 billion times a second [1.23], it becomes essential to calculate the higher order transients to accurately predict the device power and switching dynamics. Figure 1.1: Energy Imbalance It should also be pointed out that scholars working in the MOS devicemodeling are aware of the transport current components flowing in the channel. Many papers [1.24 1.27] and chapters [1.281.30] have been written about the charging and transport current components. However, all of them assume that it is not possible to separate the dissipative and energy storage components and have come up with many theories and models to envision the transient effects. One of the models by LimFossum [1.31, 1.32] has the first order transient transcapacitive current and 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0.10 1.00 10.00 100.00 1000.00 % Error Rise/Fall time in psec Error (10 Wp) Error (4Wp) Error (2Wp) Error( Wp/2) Error (Wp) ~4~ suggests the difference between nonreciprocal capacitive elements to be responsible for these transport currents. This however has some drawbacks. First, if these were the total transcapacitive currents, its product with the drain to source voltage should have been the total dissipative power, which is not the case. Second, LimFossum used Ward’s charge partition model to find the source and drain charge components, which makes their model dependent on the accuracy of the charge partition. 1.2 SCOPE The object of the research is to realize the inconsistency in the current MOSFET modeling and develop efficient models for accurate intrinsic capacitance and power dissipation estimation. An ideal model would be to consider all non linear effects and solve a complete nonlinear differential equation for the channel in three dimensions. In that case, we see a packet of charge traveling down the channel as a function of time. Although such models are valuable, from the simulation perspective, the process is ineffective as the simulation times are very long. To be computationally efficient, we need compact models that describe the electrical behavior analytically and are able to represent the nonlinear channel in a reasonable time without sacrificing modeling accuracy. Furthermore, the fast scaling of frequency for semiconductor integrated circuits that was seen in the last few decades has been saturating. One of the reasons is the increase in power dissipation. Power limits the scaling. The high power dissipation due to small device geometry has thrown off course the roadmap of future development of semiconductor technologies. When the devices are switching rapidly, the power dissipation per unit area goes up causing excessive heating. Unless a sophisticated cooling system is implemented, the device may no longer be operational. The reality is: we have reached a power limited scaling regime. Scaling now is no longer determined by the device size, but by how much power the chip can dissipate at a particular working frequency. However, the lack of suitable device models to measure this power dissipation has provided a plethora of research avenues. The conventional MOSFET models have some inherent issues and are not consistent for power and energy prediction as they: ~5~ • Fail to include the first order power dissipation due to channel charge redistribution • Give a net nonzero power in the channel that has no physical basis from the terms that should be conserved This makes the MOSFET modeling very important going forward into the nanometer regime. Given that the accuracy of the simulation depends on the physical representation of the device, it is very important that we have a reliable mathematical model that is able to represent the device behavior. Designers need these accurate models for circuit development. 1.3 OUTLINE The outline of the dissertation is as follows: Chapter 2 describes the conventional MOSFET models used in transient analysis and computer simulation. The analysis of these models gives a general overview and a good background on device modeling. Some of these models are still being used for device simulation. The Meyer’s model, Ward’s charge partition model, Mehmet model and Transcapacitance models and its effectiveness are considered. Some of the advantages and the shortcomings are also discussed. Chapter 3 describes a one dimensional MOSFET current model with current continuity equations. These equations have been used to compute the channel currents and channel charges as well as currents at the source and the drain terminals for a charge conserving, quasistatic, channel capacitance model. The calculation of channel currents without charge partition allows the computation of the instantaneous channel power, which further helps in separating the dissipating and energy conserving current components. Chapter 4 describes the details of power estimation. Zero and the first order instantaneous power is computed by integrating the power density over the entire channel. This leads to the derivation of closedform analytical expressions for the conserved and dissipative current components from the first order drain and source currents. The energy function calculations from the first order ~6~ conserved power components are also shown. Chapter 5 describes the derivation of capacitances from the first order drain (id1) and source (is1) current components. These capacitances are then separated into conserved and dissipative components. An improved equivalent circuit is also developed by following the method used by LimFossum. The results are verified using the BSIM Capacitive and LimFossum fully depleted SOI models for currents and charges in chapter 6. Even though these models used a charge partition instead of solving exactly as we have, all models predict the same source and drain currents, and hence the same terminal capacitances. However, we are able to separate out these capacitances into conserved and dissipative components. Chapter 7 describes the inconsistencies of the BSIM capacitive model for energy and power prediction. We have shown that the dependence of the BSIM bulk charge parameter on the source potential causes extra power dissipation in the channel that has no physical basis. This leads to an inconsistent power model where energy supplied from the gate does not balance out with the energy generated at the channel. ~7~ CHAPTER II II. LITERATURE REVIEW This chapter describes some of the MOS models that have been used in circuit simulators to analyze the transient response. Historically, MOS devices have been modeled with capacitor and over the last few decades, many such capacitive models have been proposed to effectively represent the charges at the four terminals of a FET device. The problem however is the difficulty in representing the terminal charges by a single model. This is because; MOS transistors not only conduct current in a steady state but also conduct when the terminal voltages are varying. The time dependence of currents and voltages of a MOSFET makes representation using steady state (DC) conditions insufficient. A solution is possible by superimposing zero order steady state DC (IV) representation over a capacitance (CV) model to characterize the transients as ( ) 0( ) 1( , ) I t I v i v dv c c dt = + where 0( ) c I v is the steady state (DC) current and depends only on the instantaneous terminal voltages. ic1(t) is the transient transport component and is zero under steady state conditions. For simulation purposes, the capacitance (CV) model is developed by expanding the transient current as 1( ) i t dq c dv c dt dt = = In the subsequent sections, some of these models have been discussed in chronological order of the history of device modeling. ~8~ 2.1 MEYER’S MODEL In 1971, Meyer [2.1] proposed the first large signal model for MOS transistors in terms of physical device parameters. Figure 2.1: Meyer Capacitance Model The model represents the charge storing property of MOS transistors using three nonlinear voltage dependent capacitors, as shown in Fig. [2.1]. These capacitors are defined in terms of the total gate charge Qg. Meyer’s model is a simple charge conservation model as it restricts the sum of the gate charge Qg and channel charges Qc o be zero, and is based on the following five assumptions. • The total gate charge Qg is a function of the terminal voltage under steady state conditions. • The gate capacitances are found as: Q C g gs vgs ∂ = ∂ Qg Cgd vgd ∂ = ∂ Qg Cgb vgb ∂ = ∂ (2.1) Cgg Cgs Cgd Cgb = + + Where vgs, vgd and vgb are the gate to source, gate to drain and gate to bulk voltages. • The drain to bulk, source to bulk and drain to source capacitances are assumed to be zero. Cds Cdb Csb 0 = = = Csd Cbd Cbs 0 = = = ~9~ • It is assumed that the capacitance matrix is symmetrical, which is necessary to conserve energy. Cgd Cdg = Cgs Csg = Cgb Cbg = • The total source, drain and bulk capacitances are calculated as: Cdd Cds Cdg Cdb = + + Css Csg Csd Csb = + + Cbb Cbs Cbd Cbg = + + These five assumptions give the capacitance matrix as shown below; 0 0 0 0 0 0 Cgd Cgs Cgb Cgd Cgs Cgb Cgd Cgd Cgs Cgs Cgb Cgb ⎡ + + − − − ⎤ ⎢ ⎥ ⎢ − ⎥ ⎢ ⎥ ⎢ − ⎥ ⎢ ⎥ ⎢ − ⎥ ⎢⎣ ⎥⎦ To calculate the total gate charge (Qg ), a gradual channel approximation is used. The charge per unit area at any position x along the channel is given in by Q(x) Cox (Vgb Vt V (x)) = − − Figure 2.2: Channel Current Calculation where Vgb is the gate voltage, Vt is the threshold voltage, V(x) is the potential at position x along the channel, and Cox is the gate oxide capacitance per unit area . The steady state drain current ~10~ Ic0 is found using ( ) ( ) 0 I WQ x dV x c dx = μ where W is the channel width and μ is the mobility. Integrating from source (x=0) to drain (x=L); ( 2 2) 0 2 I C W V V c ox L gs gd = μ − (2.2) where L is the channel length. Gate charge is given by ( )3 ( )3 2 3 ( )2 ( )2 ( )2 ( )2 Vgd Vt Vgs Vt Qg WLCox Vgd Vt Vgs Vt Vgd Vt Vgs Vt ⎡ − − ⎤ ⎢ ⎥ = ⎢ − ⎥ ⎢ − − − − − − ⎥ ⎣ ⎦ (2.3) Using (2.1) and (2.2), capacitances are calculated as ( )2 2 1 3 ( )2 Vgd Vt Cgs WLCox Vgs Vt Vgd Vt ⎡ − ⎤ ⎢ ⎥ = ⎢ − ⎥ ⎢ − + − ⎥ ⎣ ⎦ (2.4) ( )2 2 1 3 ( )2 Vgs Vt Cgd WLCox Vgs Vt Vgd Vt ⎡ − ⎤ ⎢ ⎥ = ⎢ − ⎥ ⎢ − + − ⎥ ⎣ ⎦ (2.5) Cgb 0 = Finally, current through each capacitor is computed as dVgs Igs Cgs dt = dVgd Igd Cgd dt = dVgb Igb Cgb dt = Fig. 2.4 shows the current representation of Meyer’s model. Currents I1 and I2 in the channel are assumed to be bidirectional, one being dependent on gatetosource and other being dependent on gatetodrain. This is also known as “Twocurrentsource MOS model”. ~11~ Figure 2.3: Current Representation in Meyer's model The major drawback of Meyer’s model is the exclusion of the source to bulk and drain to bulk capacitances resulting from substrate charges. 2.2 CHARGE BASED MODELS Ward [2.22.4] claimed that Meyer’s model failed the charge conservation test for circuits that required charge storage. They identified the presence of nonlinear reciprocal capacitances and exclusion of the source to bulk and drain to bulk capacitances as being the source of charge nonconservation in the circuit simulation. They based their findings using current equation ( ) ( ) dV i t C v gs dt = (2.6) Here the capacitance term is dependent on the terminal voltages of the source, drain and the gate and has been evaluated at some appropriate voltage i.e. C(v) is not defined as a time dependent variable and can follow any path and as a result may lead to some arbitrary charge value. The best possible solution with average value of capacitor taken at two time intervals may also lead to an incomplete charge prediction. Integrating from the present time point t0 to the next time point t1, equation (2.6) can be written as 1 ( 1) ( ) ( ) ( ) 0 0 t vt ∫t i t dt = ∫v t C v dv (2.7) If C(v) is considered a constant, equation (2.7) reduces to 1 ( ) ( )[ ( ) ( )] 0 1 0 t ∫t i t dt = C v V t −V t (2.8) ~12~ The capacitance value forC(v) that’s been used here is computed at time t0. Ward assumes this being the reason for charge pumping, as there may be some residual charge at time t0. He suggests that even if the capacitive values are calculated at time t1 or smaller time steps, it will not guarantee charge conservation. To overcome the assumed charge neutrality limitations, he suggested the chargepartition model [2.2]. The chargepartition model is based on the fixed charge distribution in the MOSFET terminals. The model tries to split the total channel charge Qc into source (Qs) and drain (Qd) charges rather than splitting the total distributed capacitance into reciprocal gatetosource and gatetodrain capacitances. The current is then computed as the derivative of charge as dt i(t) = dQ(t) Using similar integration approach as equation (2.7) 1 ( ) ( ) ( ) 0 1 0 t ∫t i t dt = Q t −Q t (2.9) Though Q(t0) and Q(t1) are complex functions of time, it can be obtained at any time by terminal voltage at that instant. Figure 2.4: Channel Charge Approximation using Ward's model The emphasis of the charge model was the use of charge as a state variable for the computation of charge at the MOSFET terminals. Ward was also able to put in perspective a current continuity equation I ( y,t) W Q( y,t) y t ∂ ∂ = − ∂ ∂ with the boundary conditions on V(y) as V (0) Vs = and ( ) V L Vd = ~13~ to calculate the source and drain charges together with the source and drain currents, and the transport current. Using the current continuity equation, the current at any point y on the channel is evaluated as ( , ) ( ) ( , ) 0 y Q y t I y t Is t W dy t ∂ − =−∫ ∂ (2.10) where Is (t) I (0,t) = is the source current, and L is the length of the channel. Considering only drift current for I ( y,t) and solving for Is (t) , equation (2.10) reduces to two current components I ( y,t) WQ( y,t) V ( y,t) y μ ∂ = − ∂ and (2.11) ( ) ( , ) ( , ) ( , ) (1 ) ( , ) 0 0 W L V y t d L y Is t y t Q y t dy W Q y t dy L y dt L μ ∂ ⎡ ⎤ = − ∫ + ⎢ ∫ − ⎥ ∂ ⎢⎣ ⎥⎦ (2.12) Substituting y=L to obtain the drain current ( ) ( , ) ( , ) ( , ) ( ) ( , ) 0 0 W L V y t d L y Id t y t Q y t dy W Q y t dy L y dt L μ ∂ ⎡ ⎤ = − ∫ + ⎢ ∫ ⎥ ∂ ⎢⎣ ⎥⎦ (2.13) Since the drain and source current can be assumed to have transport and charge components, they can be represent using ( ) ( ) ( ) dQs t Is t IT t dt = − + (2.14) ( ) ( ) ( ) dQd t Id t IT t dt = + (2.15) From equations (2.13) (2.14) and (2.15), (1 ) 0 L y Qs W Qdy L = ∫ − (2.16) ( ) 0 L y Qd W Qdy L = ∫ (2.17) Many modifications have been made since Ward proposed the original charge model in 1981. Almost all these models consider “charge” as a state variable and use nonreciprocal capacitors. Some models have partitioned the channel charge into drain and source components in the ratio ~14~ of 40/60 while others use a 50/50 model. However, none of these models addresses the actual cause of charge nonconservation. Yang, Berton and Chatterjee [2.5], while investigating the charge conservation problem, observed that the nonconservation of charge in circuit simulator SPICE is due to the integration problem independent of device physics. They think the error is due to the choice of voltage as a state variable for simulation, and also due to the nonlinearities in the MOS capacitances and its dependence on four different terminal voltages. Sakallah, Yen and Greenberg [2.6] also support the view that the charge nonconservation in the Meyer capacitance model has nothing to do with the device physics or a faulty capacitive model, “rather by the mathematical error of characterizing a multidimensional function by an incomplete subset of its partial derivatives.” They conclude that the charge nonconservation can be eliminated if circuit simulators are given non trivial models. They also followed modeling using Ward’s approach and proceeded by splitting total channel charge into source and drain instead of splitting total distributed capacitance between the gate and the channel into reciprocal gatetosource and gatetodrain capacitances. As mentioned earlier, the charge splitting techniques have been revised many a time, and have been classified into two groups with respect to the bulk charges included in the model [2.7] for efficient MOSFET modeling. They are I. Depletion Charge Model (DSM) II. Simplified Charge Model (SCM) In DCM, bulk charge is considered to be proportional to the square root of a voltage, while SCM is a more simplified DCM model, with slight compromise in bulk to drain and bulk to source capacitances. Although chargebased models provided an alternate way to model MOSFET’s, it was still not able to explain the charge nonconservation of the Meyer capacitance model. Roots and Hughes [2.8] in 1988 and Snider [2.9] in 1995 suggested a transcapacitance model, which came close in identifying the conservation problem. ~15~ 2.3 TRANSCAPACITIVE MODEL Roots and Hughes [2.8] in 1988 and later Snider [2.9] was able to explain the charge nonconservation of the Meyer capacitance model using the concept of transcapacitance. According to them, a capacitive gate to source MOS elements that depends on both gate to source and gate to drain voltages would transport a nonzero charge. They predicted the violation of charge conservation due to the omission of recharging effect of capacitances and tried to compensate the charge by adding an extra element in the circuit and called it a transcapacitance element. Their model concluded that: 1. Current equation dt I = C dV alone does not account for all the currents in MOS transistors as capacitances are controlled by more than one source. 2. These capacitances appear to dissipate energy if transcapacitance terms are ignored. Figure 2.5: Transcapacitance Approximation 2.4 MEHMET MODEL In 1989, Mehmet A. Cirit [2.10] was able to show the root cause of charge nonconservation in the gatecapacitance model proposed by Meyer. He points out that the “Meyer model is a firstorder inaccurate approximation to MOS capacitances.” Since the MOS capacitance is dependent on several variables, faults in the modeling of such an element causes the SPICE simulator to neglect nonlinear first order capacitive terms. Considering the gate to source transient current equation igs Cgs tvgs = ∂ ~16~ its partial derivative gives i C Vgs C Vgs gs gs gs δ δ • • = + . (2.20) Since gate capacitance is dependent on gate to source, gate to drain and gate to bulk voltages, including these effects, equation (2.20) can be modified as Cgs Cgs Cgs i C Vgs Vgs V Vgs Vgd Vgs V gs gs V gs V V gb gs gd gb δ δ δ δ δ δ δ δ δ δ δ • • • • = + + + (2.21) If α is 1/h, where h is the time interval, and voltage varies by an amount δV, the corresponding change in its time derivative V • can be estimated asδ V =αδV • . Substituting these values in equation (2.21), equation (2.21) can be rewritten as Cgs Cgs Cgs i C V Vgs V Vgs Vgd Vgs V gs gs Vgs gs Vgd Vgb gb δ δ δ δ αδ δ δ δ δ δ δ • • • = + + + (2.22) Similarly, gate to drain and gate to substrate current can be written as Cgd Cgd Cgd i C V Vgd V Vgd Vgd Vgd V gd gd V gs V V gb gs gd gb δ δ δ δ αδ δ δ δ δ δ δ • • • = + + + (2.23) Cgb Cgb Cgb i C V Vgb V Vgb Vgd Vgb V gb gb V gs V V gb gs gd gb δ δ δ δ αδ δ δ δ δ δ δ • • • = + + + (2.24) The first term in (2.222.24) is frequency dependent, while rests of the terms are due to nonlinear capacitances and look like resistors in the channel. As circuit simulators only considered the frequency dependent terms for circuit evaluation, Mehmet assumed that this incomplete representation was the root cause of charge pumping in circuit simulators, and proposed a model to include ignored nonlinear terms that caused an extra charge in the channel. ~17~ Figure 2.6: Small Signal Representation of Mehmet Model Fig. 7 shows a small signal representation of Mehmet model for Cgs where C C gs gsgs Vgs δ δ = Cgs Cgsgd Vgd δ δ = Cgs Cgsgb Vgb δ δ = (2.25) Cgd Cgdgs Vgs δ δ = Cgd Cgdgd Vgd δ δ = Cgd Cgdgb Vgb δ δ = (2.26) Cgb Cgbgs Vgs δ δ = Cgb Cgbgd Vgd δ δ = Cgb Cgbgb Vgb δ δ = (2.27) Mehmet used this model in the circuit simulator Lspice and observed the charge conservation. He concluded that the Meyer gate capacitance model can be made to conserve charge by considering all first order terms. He also pointed out that the substrate charges might be easily included in the Meyer capacitance model to simulate the MOS devices more accurately. It should be noted that in any MOSFET model, charge or capacitance, the charge neutrality condition is built into the derivation [2.11] and may seem unreasonable to come up with a charge nonconservation problem. Whichever modeling techniques are used, the main goal is to come up with an analytical description of MOS device behavior with emphasis on equations that are continuous in all regions of device operation. ~18~ CHAPTER III III. FIRST ORDER QUASISTATIC CHANNEL CAPACITANCE MODEL This chapter describes the mathematical equations used to analyze the MOS transistor for the research work. The current continuity equations are presented without the channel charge partition to compute the steady state and dynamic current components. These currents then become the basis for IV and CV models to be used in the circuit simulators. 3.1 STEADY STATE OPERATION In the steady state, the gate and substrate are assumed to have no direct conductive path to the channel. Leakage through the gate oxide as well as recombination current between the substrate and the channel are neglected. Figure 3.1: BULK and SOI CMOS Structures It is very important that the body charges are properly modeled [3.1, 3.2, 3.3] and its effects are included for steady state and the transient simulations. These effects cause an uneven distribution of channel charge between the source and the drain regions, and the regions in between, which in turn causes uneven distribution of the gate and substrate charges. To model all these skewed distributions, it will be convenient to describe the charges by its density per unit length. Considering only the intrinsic part of the MOS transistor, which is responsible for all the transistor action, the zero order charge per unit length at the terminals can be written as ~19~ q jb0 f (vgb, vcb ) where j g, c = = (3.1) In terms of drift current, current flow in the device can be seen due to the transport of electrons from the source to the drain terminal. Taking steady state values, Ic0 ID = (3.2) IS ID = − (3.3) IG 0 = (3.4) IB 0 = (3.5) where Ic0 is the steady state channel current, which becomes ID at the drain end and –IS at the source end. The steady state gate IG and substrate currents IB are zero as the transistors are assumed to be leakage free. These terminal currents can be expressed as some function of terminal voltages and can be written as Ic0 f (vD, vG, vS ,vB) = (3.6) 3.2 QUASISTATIC OPERATION Equation (3.4) was calculated with the assumption that the terminal voltages were steady. In a real circuit, transistors operate under dynamic conditions where terminal voltages are varying. To calculate the charge under such conditions, quasistatic operations are assumed. The voltages are allowed to vary slowly in quasistatic operation. Though the gate, substrate and the channel charges are still the functions of instantaneous voltages and can be represented using equation (3.1), however, the currents can not be predicted using equation (3.6). With similar assumption of leakage free gate oxide and negligible recombination current, the first order gate (ig1) and substrate (ib1) currents are no longer zero. They are given at any location x along the channel by the gate (qg) and bulk (qb) charge densities as: ig (x,t) d qg (x,t) dt = (3.7) ~20~ ib (x,t) d qb (x,t) dt = (3.8) In the quasistatic operation, even though the charge distribution in the channel remains the same, there exists a conducting path between the source and the drain terminals. Charge enters from the source terminal and leaves the drain terminal, which makes channel partition schemes misleading to understand the device physics. It is also challenging to represent the channel charge and compute the first order source (is1) and drain (id1) terminal currents due to two reasons: • It is unrealistic to consider the charges in the channel as being partitioned between source and drain and • Charge redistribution causes extra dissipation in the channel. The unrealistic partition can be resolved by solving for the total charge in the channel instead of separating it into source and drain charges. Fig. 3.2 shows a voltage, charge magnitude and current waveforms. The current waveforms show a pair of first order components together with a steady state DC component. The origin of these first order components not predicted by DC operation can be explained using a test quasistatic voltage at the gate terminal. Figure 3.2: Voltage, Charge and Current Waveforms ~21~ A rising input at the gate terminal from time t0 to t1 causes the first order currents. Compared to first order drain current (id1), first order source current (is1) is more in this interval as more electrons are pumped from the source terminal and fewer electrons are removed from the drain. Between the intervals t1 to t2, current settles into a steady state value of Ic0. On the other hand, for a falling waveform between the interval t2 to t3, first order drain current becomes more than the first order source current as more electrons are sucked out from the drain terminal. These transients that show up during the switching are also responsible for the channel charge redistribution, which in turn also contributes to power dissipation. To properly analyze the MOS transistors and develop CV models to be used in circuit simulators, we then need to consider these first order currents together with the steady state values. As mentioned above, the charge redistribution also contributes to the power dissipation, which suggests the presence of first order dissipative and conserved components. We have been able to identify and separate out these components. This is explained in detail in chapter 4 with derivations. 3.3 MODELING EQUATIONS In order to obtain an analytical solution, the current flow is considered in one dimension parallel to the surface of the device. The equations for both Bulk and SOI processes are developed with some assumptions. The body charge is assumed to have square root dependence for the Bulk process, while the charge expressions for SOI MOSFET assumes that the region under the channel is completely depleted of mobile charges. These simplified assumptions helps us to make use of a linear relationship between the body and the surface potential to compute the energy function without partitioning the channel charge. The linear bodysurface relation also provides a simplified charge model and terminal currents. It should be noted that solving the model involves complicated algebraic calculations that are practically impossible without modern mathematics tools like “Mathematica” [3.4]. ~22~ Fig. 3.3 shows NMOS BULK and SOI transistors. The charge per unit length ( qc ) at a position x along the channel is given by qc (x) cox (vgb v fb vcb(x) qb(x) / cox ) = − − − −φ + (3.9) Similarly, the bulk charge (back gate) per unit length ( qb ) at x can be written as ( 1 2 ( )), ( ) ( 1 ( 1) ( ( ) )), cox k k vcb x SOI qb x cox k vsb Abulk vcb x vsb BULK φ − + ⎧⎪ = ⎨ − + + − − ⎪⎩ (3.10) where v fb , vgb and vcb are flat band, gate and channel voltages with respect to the body. Abulk [3.13] is the bulk charge coefficient, 1 k and 2 k are body effect coefficients. cox w (cox / A) = is the oxide capacitance per unit length and w is the channel width. The bulk charge is approximated using first two terms of Taylor’s expansion around the source terminal vsb . The linear dependence of back gate for a fully depleted SOI MOSFET is included in the k1 term. Charge conservation is insured by defining the gate charge per unit length g q as qg (qb qc ) = − + (3.11) It will be convenient to define the channel charge per unit length at the source (x=0) qs and the drain (x=L) qd and their time derivatives as qs cox vgst = − and (3.12) Figure 3.3: Four terminal (a) BULK NMOSFET and (b) SOI NMOSFET Structure ~23~ d q c d v dt s ox dt gst = − (3.13) where vgst vgb vt vsb = − − (3.14) In equation (3.14), vt is the threshold voltage. The body effect parameters are included by considering the dependence of source terminal on the threshold voltage [3.5, 3.6] by defining 0 2 , ( ) 0 1( ), vt k vsb SOI vt vsb vt k vsb BULK φ φ + ⎧⎪ = ⎨ + + − ⎪⎩ (3.15) where 1 , 0 , 1 v fb k SOI vt v k BULK fb φ φ φ + + ⎧⎪ = ⎨ + + ⎪⎩ (3.16) At the drain end, qd coxvgdt = − and (3.17) d q c d v dt d ox dt gdt = − where (3.18) (1 2) ( ), ( ) ( ), vgb vt vsb k vdb vsb SOI vgdt x vgb vt vsb Abulk vdb vsb BULK − − − + − ⎧⎪ = ⎨ − − − − ⎪⎩ (3.19) It is assumed that positive current flows into the drain and velocity saturation effects are neglected. The derivative of Abulk with vsb is assumed to be negligible. These assumptions are necessary for energy conservation [3.7] and simplified capacitance equations [3.8]. Even though the equations are simplified, accuracy is not significantly compromised [3.8]. The results are expected to be accurate for a substrate referenced system [3.9]. Drift current at a distance x along the channel can be written as ic (x,t) qc (x,t) d vcb (x) dx = μ (3.20) Charge conservation is assured using the continuity equation d ic (x,t) d qc (x,t) dx dt = − (3.21) ~24~ where qc qc0 qc1 = + In equation (3.21), qc0 is a function of terminal voltages and qc1 is a function of first order time derivatives of terminal voltages. Using (3.20) in (3.21) gives d [qc (x,t) d vcb (x)] d qc (x,t) dx dx dt μ = − (3.22) Taking the spatial derivatives of charge per unit length as a function of potential along the channel, equation (3.9) and (3.10) reduces to (1 2), ( , ) ( ); ; , d d k SOI qc x t Cc vcb x Cc coxK K dx dx Abulk BULK + ⎧⎪ = = =⎨⎪⎩ (3.23) Substituting d vcb (x) dx in (3.22) and rearranging terms gives [ ( , ) ( , )] ( , ) d d Cc d qc x t qc x t qc x t dx dx μ dt = − (3.24) Equation (3.24) can be solved iteratively to compute the current and the charge in the channel. In terms of the steady state (zero order) charge per unit length at any position x along the channel, equation (3.24) reduces to ( 0 0) 0 d q d q dx c dx c = (3.25) Performing integration from source(x=0) to drain (x=L), zero order charge along the channel becomes ( 2(1 / ) 2 / qc0 qs x L qd x L = − − + (3.26) and the steady state drift current component simplifies to 0 0 0 I q d q C c dx c c μ = (3.27) Equation (3.27) gives the usual equation for static current neglecting velocity saturation, which is shown in Table 1. The first order current and charge can be found by keeping terms of first order in time derivatives in equation (3.24) ~25~ ( 0 1 1 0 ) 0 d d d Cc d qc qc qc qc qc dx dx dx μ dt + =− (3.28) Rearranging the terms, equation for the first order channel charge simplifies to 1 ( ( [ ] ) ) 1 0 1 0 0 Cc d qc qc x dx dx c x c qc dt μ = − ∫ ∫ + + (3.29) and the first order channel current reduces to 1 ( 0 1 1 0) i q d q q d q c C c dx c c dx c c μ = + (3.30) Finally, equation (3.30) can be solved to compute the first order channel current at the source is1 = ic1 (x=0) and the drain id1 = is1 (x=L) ends in all regions of operation. We have assumed pinchoff saturation which occurs when qd 0 = . The drain voltage at saturation can now be estimated by setting vgdt (x) 0 = to get vgst vds K ≥ as a boundary between the linear and the saturation regions. In the cutoff, it is assumed that the channel current is zero, which is made possible by setting both the charge densities d q and s q to zero. Table 1 summarizes the charge and current in all regions of operations. These results obtained without partitioning the channel charge are in agreement with LimFossum [3.10] and the BSIM capacitive model [3.11, 3.12] which were obtained using Ward’s [3.2] partition. Therefore, we have verified that Ward’s partition is correct when the voltage dependence of Abulk is ignored. Table 3.1: NMOS Zero and First Order Charges and Currents Linear Saturation CutOff Conditions 0 0 0 qc vgdt vgst < > > 0 0 0 qc vgdt vgst < = > 0 0 0 qc vgdt vgst = = = qs coxvgst − c v ox gst − 0 qd coxvgdt − 0 0 ~26~ Ic0 2 2 2 ( ) 2 (1 ) gst gdt cox v v L k μ − + 2 2 2 (1 ) gst cox v L k μ + 0 is1 2 2 3 2 2 2 [2 ( )( 3 ) 15( ) ( )(8 9 3 )] ox gdt gdt gdt gdt gst gst gdt gst gst gst gdt gdt gst gst c L d v v v v v v v v dt v d v v v v v dt + + + + + + 2 5 c L d v ox dt gst 0 id1 2 2 3 2 2 2 [ ( )(3 9 8 ) 15( ) 2 ( )( 3 )] ox gdt gdt gdt gdt gst gst gdt gst gst gst gdt gdt gst gst c L v d v v v v v v v dt v d v v v v v dt + + + + + + 4 15 c L d v ox dt gst 0 ~27~ CHAPTER IV IV. MOSFET POWER This chapter discusses the origin of MOS transistor leakage and describes the power computation techniques for conserved and dissipative components without the channel charge partition. The existence of an energy function is also validated. The conserved and dissipative power components then become the basis of conserved and dissipative current components in chapter 5. The fast scaling of operation frequency for semiconductor integrated circuits that was seen in the last few decades cannot continue. One of the reasons is the increase in power dissipation. Power limits the scaling. The high power dissipation due to small device geometry has thrown off course the roadmap of future development of semiconductor technologies as predicted in the International Technology Roadmap for Semiconductors [4.1]. When the devices are switching rapidly, the power dissipation per unit area goes up causing excessive heating. Unless a sophisticated and expensive cooling system is implemented, the device may no longer be operational. The reality is: we have reached a power limited scaling regime. Scaling now is no longer determined by the device size, but by how much power the chip can dissipate at a particular working frequency. However, the lack of suitable device models to measure this power dissipation has provided a plethora of research avenues. The conventional MOSFET models have some inherent issues and are not consistent for power and energy prediction as they: • Fail to include the first order power dissipation due to channel charge redistribution, ~28~ • Give a net nonzero power in the channel that has no physical basis from the terms that should be conserved. This makes the MOSFET modeling very important going forward into the nanometer regime for low power design techniques and poweraware architectures [4.3]. Given that the accuracy of the simulation depends on the physical representation of the device, it is very important that we have a reliable mathematical model that is able to represent the device behavior. Designers need these accurate models for circuit development. 4.1 SOURCES OF POWER DISSIPATION There are three sources of power dissipation in the MOS transistor [4.34.6]. The first source of power dissipation is due to the transistor switching that is related to the charging and discharging of the external load capacitors. The second source is from the shortcircuit power due to the current flow from the supply to the ground. These two dissipations are related to the transitions at the gate [4.7]. The third source is the leakage power. Transistor scaling has reduced the threshold voltage and increased the gate leakage resulting in higher static power. Fig. 4.1 shows all these leakage sources that are taking up the power budget. Some of these sources have dominant effects on the transistor performance in the nanometer regime [4.7, 4.8]. Figure 4.1: Leakage Current Components [4.5] ~29~ I1 PN junctions reverse bias current I2 Subthreshold leakage I3 Drain Induced barrier lowering I4 GateInduced drain leakage I5 Punchthrough I6 Narrow width effect I7 Gate oxide tunneling I8 Hot carrier injection 4.2 POWER AND ENERGY MODELING ISSUES Meyer [4.9] was the first to present a capacitive model. Ward and Dutton [4.10] pointed out the assumed charge non conservation problems in Meyer’s model. To solve these problems in transient simulation, they proposed a charge partitioning scheme with a charge conservation constraint. Sheu et al. [4.11] and Chung [4.12] made many improvements later to better derive IV and CV characteristics. One of the industry standards, the BSIM capacitive model includes many of these models to estimate the behavior of MOS transistors. The BSIM model assumes that the MOSFET capacitance is an energy storage device and uses the conserved charges (to first order) to predict the currents and voltages at different nodes. The same charge (to zero order) is also used to predict the channel power. This makes the BSIM capacitive a zero order, quasistatic power dissipation model. The model Assumes that the first order terms only contribute to energy storage Uses channel charge partition scheme and the bulk charge parameter has a nonlinear dependence on the source potential. Both these ideas leave a lot to be desired. First, the dissipative power has some higher order terms due to the charge redistribution. These higher order dissipative components become significant at higher frequencies and modify the total power dissipated in the channel [4.13]. This is explained later in section 4.5. Second, the nonlinear dependence of Abulk on vsb does not ~30~ allow the derivation of energy function from all of the conserved components [Appendix A7.2]. These effects causes the BSIM capacitive model to predict a different number for instantaneous power measured from the supply than the power dissipated in the device, clearly a violation of energy conservation principles. If an analytical closed form solution for the stored energy function is desired using nonreciprocal capacitors, the FET charge equation has to be solved for a linear source dependence of the bulk without the channel charge partition. These inconsistencies make the current BSIM capacitive model nonideal for energy estimation. 4.3 POWER MEASUREMENT TECHNIQUES Many models have been suggested for the estimation of power, like using supply current measurements [4.14], input slew dependency [4.15], propagation delay [4.16], short circuit power [4.17] and nonconventional capacitorbased methods [4.18] CMOS VDD CL t Vin Ip In Vout Figure 4.2: Dynamic Power Fig 4.2 shows one of simplest techniques used to calculate the transistor power consumption. Power is consumed when the gate drives the output out V to a new value. Assuming that the input in V changes very fast, only one transistor turns on at a time. When the output goes high, the ~31~ current flows through the PFET and goes only to the capacitor. The current component that goes down the NFET has been neglected. Similarly when the output settles to a low value, it is assumed that the current goes through the NFET. Though the PFET is not quite turned off yet, the current that is coming through the PFET is neglected. vin vout Ip In t t t t 0 T/2 T Figure 4.3: Transient Waveforms Fig 4.3 shows the transient waveforms. The output looks more like a RC time constant due to the presence of the capacitance, charging up the output from 0 to T/2 and then discharging from T/2 to T. If we look at the corresponding current plots for falling input transient, it is only the PFET that is providing the capacitor current p I . For the rising input transient, capacitor current n I is through the NFET. It should be noted that the currents mentioned above are the magnitudes of the drain current. The instantaneous power dissipation is then calculated by solving for I and V and multiplying them together. It is also assumed that the capacitors are purely energy storage devices and does not contribute to net power dissipation. Hence, during the falling input transition, power dissipation is only in the PFET. Similarly during the rising input transition, power dissipation is only in the NFET. Using these assumptions, the average power Pc0 for a complete cycle is computed using 1 / 20 [ ] 0 /2 T T Pc I pVDSpdt InVDSndt T T = ∫ + ∫ (4.1) ~32~ where VDSp and VDSn are the outputs at the PFET and NFET respectively. During the falling transition as PFET charges the capacitor, actual positive current flows from the device to the capacitor. This makes the PFET drain current p I negative. ( out ) p L I C dV dt = − (4.2) where L C is the output load. The corresponding output voltage at the PFET, DSp V becomes ( ) DSp out DD DD out V =V −V = − V −V (4.3) where DD V is the supply voltage. From (4.2) and (4.3), power dissipated in the PFET, PFET P is computed using / 2 0 T PFET p DSp P = ∫ I V dt (4.4) Similarly, the current through the NFET, n I is negative of the capacitive current. ( out ) n L I C dV dt = − (4.5) and the corresponding output voltage, DSn V is DSn out V =V (4.6) From (4.5) and (4.6), power dissipated in the NFET, NFET P is given by / 2 T NFET n DSn T P = ∫ I V dt (4.7) The average power, c0 P for a complete cycle is estimated using equations (4.4) and (4.7) as 1 [ ] Pc0 T PPFET PNFET = + (4.8) Substituting , , n p DSn I I V and DSp V in equation (4.8), the average power equation reduces to 1 / 2 0 [ ( ) ( ) ] 0 /2 T dVout T dVout Pc CL VDD Vout dt CL Voutdt T dt T dt = ∫ − + ∫ − (4.9) ~33~ Because of the fact that the transistor currents are related to the charging and discharging of the currents of the capacitor, the power integrals can be replaced from integrals over dt to an integral over dv . This gives a closed form expression for the dynamic power independent of i(t) and v(t) . 2 Pc0 f CL V DD = (4.10) There are, however, some issues in regards to the dynamic power equation (4.10). These issues are: • The MOS channel is not purely an energy storage device and has no energy function. For an energy function to exist, second order partials have to be equal. This is shown in the Appendix [A4.5A4.7]. • The MOS capacitors dissipate power and the transcapacitive terms used in the charge model includes both dissipative and conserved components. Therefore, it is not appropriate to look at the change in the energy of the external load capacitor L C in the channel as a true measure of power. Dynamic power predicted using equation (4.10) is in fact an easy way of computing the zero order power by looking at the change in energy during charging and discharging of external capacitors. Fig. 4.4 shows another capacitor based technique used for power measurement. In this type of power measurement, switch S is closed and the load capacitor CL is allowed to attain the supply voltageVDD . The switch is then opened and the CMOS gate is allowed to undergo a transition. This causes some energy consumption in the circuit, which is captured by the measuring device as a decrease in supply voltage ( Δv ). Energy dissipated in the circuit can now be estimated using 1 2 1 ( )2 2 2 Energy CLV DD CL VDD v = − − Δ (4.11) where 1 2 2 CL v Δ is the energy consumed by the circuit. This method of energy prediction is very accurate [4.18]. However, this energy prediction is not possible during the design phase. Hence, ~34~ there is a need for a verification tool that can simulate the real world behavior of the transistor during the design phase. VDD Switch S CL Measuring Device CMOS Figure 4.4: Capacitor based Power Measurement Technique This makes the next and subsequent sections of power derivation one of the most important findings of our research, where the energy function is derived from a symmetrical charge conserving FET models. Before going through the derivation, it however, becomes important to discuss the extra source of transistor power dissipation that was not included in section 4.1. It also becomes important to check the validity of the quasistatic approximation in the model derivation. Figure 4.5: Power Dissipation in MOS Transistor When the gate undergoes a transition, from vss to vdd or vdd to vss, the resistive drop (IR) and the charge redistribution cause the power dissipation in the channel. Usually, the zero order steady state current is used to determine the power dissipation. The additional power dissipation from ~35~ the channel charge redistribution is ignored. This is because, in the quasistatic model, charge redistribution is assumed to happen instantaneously with no propagation delays. However, the channel charge density still changes as an indirect function of time through the dependence on time varying terminal voltages. This allows the use of the quasistatic model to predict the charge redistribution and the associate power dissipation as long it satisfies tR > 20 T0 [4.19] where R t is the waveform rise time and 0 T is the time taken by electrons to reach the drain from the source terminal (transit time). Moreover, the conventional charge model is based on the assumption that the MOSFET capacitors do not contribute any net power dissipation in the channel. But, as shown in Appendix [A4], it is not the case. The channel capacitances are not energy conserving. They do have some power dissipative terms due to the charge redistribution in the channel. These higher order dissipative terms become significant at higher frequencies, which make it necessary to include their effects on total power for efficient power dissipation prediction. 4.4 POWER EQUATIONS Fig: 4.6: MOSFET Channel Power Calculation Fig 4.6 shows a MOS device. Considering a slice of thickness Δx , MOS channel can be thought of having two power components, due to: • Fig. 4.6 a: The current i(x) flowing through the slice of thickness Δx having a potential Δv , which looks like a series resistance and results in the power dissipation of iΔv . ~36~ • Fig. 4.6b: The rate of change of charge that is building in the slice due to the difference in current Δi . This power change vΔi is the energy stored in the charge at the potential v(x) . The instantaneous power going into the transistor channel c P can then be estimated using ( ( ) ( )) ( ( )) ( )] ( )( ( ))] 0 0 0 L d L d L d Pc ic x vcb x dx ic x vcb x dx ic x vcb x dx dx dx dx = ∫ = ∫ + ∫ (4.12) where the first integral represents change in stored energy and second term represents power dissipation. Keeping nonzero terms to first order in time derivatives, equation (4.13) can be expanded as: Pc Pc0 Pc1,diss Pc1,cons = + + where 0 ( 0( )) 0 L d Pc Ico vcb x dx dx = ∫ [Appendix 4.1] (4.13) 1, 1( 0( )) 0 L d Pc diss ic vcb x dx dx = ∫ [Appendix 4.2] (4.14) 1, 0( 1) 0 L d Pc cons vcb ic dx dx = ∫ [Appendix 4.3] (4.15) The total instantaneous power P into the transistor is the sum of channel power Pc and gate power Pg1,cons . P Pc Pg1, cons = + (4.16) where the gate power is Pg1,cons ig1vgb = (4.17) where ig1 (Appendix: A3.3) is the first order gate current component. ~37~ Equation (4.13) represents the usual zero order power dissipation. Equation (4.14) represents the first order power dissipation due to the transcapacitive transient current components and equation (4.15) represents the first order conserved power in the channel. Since the gate power estimated in equation (4.17) is assumed to be purely reactive and leakage free, it becomes necessary to add its contribution together with the conserved components from the channel to obtain a closed form solution for the stored energy function. Table 2 summarizes the power components and Appendix (A4) shows the derivation of these equations. We have used vgbt0 vgb vt0 = − . Table 4.1: Power Equations Power Linear Region Saturation Region Cutoff Region Pc0 ( 2 2 ) 2 cox v v v LK ds gst gdt μ − 2 2 cox v v LK ds gst μ 0 Pc1, diss ( )[3 2 30( )3 3 2 7 ( ) ] coxL d vds vgst vgdt vgdt vgdt v v dt gdt gst v d v v d v d v v gst dt gst gdt dt gdt dt gst gst − + + + + 10 coxL d vds vgst dt 0 Pc1, cons [ 3( ) 6 4( ( 2 ) (2 ))( 0)] ( )2 coxL d d vgdt vgdt vgst vgst K dt dt v d v v v v d v v v v gdt dt gdt gdt gst gst dt gst gdt gst gbt vgdt vgst − − + + + + + + 6 ( 3 ) coxL d vgst dt vdb vsb − + 0 4.5 ENERGY FUNCTION CALCULATION Energy is defined as the capacity to do work. In a MOSFET, work is done to transfer the charge from the source to the drain terminal. However, energy prediction is very tricky for MOS devices ~38~ as it is difficult to separate the charging (effective work) and the dissipative components of the electrons. This makes it difficult to predict how much energy is lost in the channel and how much energy is used as the effective work. To make the matter worse, the bias at the gate terminal forces these charge movements. For the model derivation, the gate is assumed to be leakage free. It is also assumed that there is no net charge transfer from the gate to the channel. However, energy is still supplied from the gate to drive the channel charges. It then becomes necessary to add the contribution from the gate together with the channel charges. As these charges are conserved over a complete cycle, it is possible to derive a closed form analytical solution for an energy function from these conserved charges. The separation of conserved components make it possible to estimate total power dissipation by leaving out energy storage terms that do not contribute to power dissipation, making the solution simple, straightforward and computationally efficient. The conserved component of channel power was given by equation (4.15). It can also be written as: 1, P dE E dV c cons dt V V dt ∂ = =Σ ∂ (4.18) Equation (4.18) can be expanded to represent channel power in the form of energy as 1, E dvgb E dv E dv P c c db c sb c cons v dt v dt v dt gb db sb ∂ ∂ ∂ = + + ∂ ∂ ∂ (4.19) where Ec is some function of voltages vgb, vsb, vdb . Since the channel receives energy from the gate during switching transient, it can be shown [APPENDIX A4.5] that the energy from the channel alone is not conserved. Hence an energy function is not possible in equation (4.19). Taking similar approach, gate power is represented using ~39~ 1, Eg dvgb Eg dv Eg dv P db sb g cons v dt v dt v dt gb db sb ∂ ∂ ∂ = + + ∂ ∂ ∂ (4.20) where Eg is also some function of vgb, vsb, vdb . Since gate is supplying the energy to the channel, it can also be shown that the gate alone has no energy function [APPENDIX A4.6]. An Energy function is possible only when the conserved components are combined [APPENDIX A4.7]. Pcons Pg1, cons Pc1, cons = + (4.21) Using equations (4.19), (4.20) and (4.21) ( , , ) ; , , E E Eg v v v c j g s d v gb sb db v v jb jb jb ∂ ∂ ∂ = + = ∂ ∂ ∂ (4.22) It can be shown that equation (4.22) can be solved [APPENDIX A4.7] to compute the energy function. Table 4.2 summarizes the energy function. Table 4.2 ENERGY FUNCTION Linear Saturation CutOff Qg ( 2 ( )2 12( ( ) / 2) vdb vsb coxL vgb v fb vsb K vdb vsb vgst K vdb vsb φ − − − − − − + − − ( ) 3 ) coxL vgb vfb vgst vsb K φ − − − − ( 0 ) coxL vgb v fb vgbt K φ − − − E f 1 2 2 {( 1)( ) 4 ( )2 ( )2} 0 coxL K vdb vsb vgbt vdb vgbt vsb Qgvt − + + − + − + 2 1 {( 1)( 0 4 2 ) ( )2} 0 0 vgbt cox L K K vsb vgbt vsb Qg vt − + + − + 2 2 0 ( 1) 0 coxL vgbt K K Qgvt − + ~40~ CHAPTER V V. FIRST ORDER CURRENT COMPONENTS AND CAPACITANCE CALCULATION In this chapter, total capacitance equations are derived from the first order drain (id1) and source (is1) current components. These total capacitances are then separated into conserved and dissipative components. Finally, an equivalent circuit is developed by following the method used by LimFossum [5.1] and results are verified for currents and charges. 5.1 FIRST ORDER CURRENT COMPONENTS As seen in Table 3.1, first order currents are functions of voltages and their time derivatives (dv/dt). However, the coefficient of dv/dt instead of being purely storage capacitance is also responsible for some of the power dissipation in the channel. This suggests that the first order drain (id1) and the source (is1) currents consist of two separate components; one that contributes to power dissipation in the channel, and another that is responsible for the energy storage. Taking this approach, the first order drain and source currents obtained in chapter 3 can be expanded as id1 id1,cons id1,diss = + (5.1) is1 is1,cons is1,diss = + (5.2) where id1,diss and is1,diss are the dissipating, while id1,cons and is1,cons are the energy storing components of first order drain and source currents. Fig. 5.1 shows this concept where first order currents id1 and is1 are separated into two components. Since the gate and the substrate currents are nondissipative in the absence of leakage, there is no need to separate them. ~41~ id1,diss id1,cons is1,cons is1,diss Figure 5.1: First order dissipative and conserved current components The dissipative current components in equations (5.1) and (5.2) are due to the first order power dissipation in the channel from the charge redistribution. It is estimated by dividing the dissipative power obtained using equation (3.1) with the total channel potential as: 1, 1, 1, , P i c diss i i d diss v s diss tt diss ds = =− = (5.3) where itt,diss is the transient transport current that is responsible for the first order power dissipation in the channel, and is defined as positive going into the drain. The energy storage components are now easily computed by subtracting the dissipated component from the first order drain and source current components. id1,cons id1 id1,diss = − (5.4) is1,cons is1 is1,diss = + (5.5) Equations (5.4) and (5.5) can also be verified by solving conserved channel power equation (4.16) obtained in chapter 4 as: Pc1,cons id1,consvdb is1,consvsb = + (5.6) Table 5.1 summarizes these first order, energy conserving and dissipative drain and source ~42~ current components in three regions of transistor operation. Table 5.1: Storage and Dissipative Current Components Linear Saturation CutOff id1, diss ( ) [3( 2 2 ) 30( )3 7 ( )] coxL vgst vgdt d d vgdt vgdt vgst vgst v v dt dt gdt gst v v d v d v gdt gst dt gdt dt gst − + + + + 10 coxL d vgst dt 0 is1, diss id1, diss − id1, diss − 0 id1,cons [ (3 5 ) 6( )2 (3 )] cox L d vgdt vgdt vgdt vgst v v dt gdt gst v d v v v gst dt gst gdt gst + + + + 6 coxL d vgst dt 0 is1,cons [ ( 3 ) 6( )2 (5 3 )] coxL d vgdt vgdt vgdt vgst v v dt gdt gst v d v v v gst dt gst gdt gst + + + + 2 coxL d vgst dt 0 5.2 CAPACITANCE DERIVATION In the following section, capacitance equations are derived that are continuous and valid in all regions of transistor operation. Conventional MOS transistor model assume the MOS channel is an energy storage device and ignores the dissipative components due to the channel charge redistribution and convection effects. It is shown [5.3] that the dissipative components have significant contributions at high ~43~ frequencies and energy conserving capacitance representation of MOSFET is misleading. However, MOS transistors can still be represented as an energy storage device if the dissipative components are separated from the total capacitances. Ours is a first step towards such a complete model, which is able to separate the total capacitance into the dissipative and conserved components. Representing the first order current ii1 in terms of capacitance: 1 ( ) ; , , , . , ii Cii tvib Cij tv jb i j g d s j ib = ∂ − Σ ∂ = ≠ (5.9) where Cii , Cij’s are total capacitances and vib , vjb are the terminal voltages with respect to the body voltage. Table 5.3 summarizes these total capacitances, which are calculated by representing id1 and is1 in the above mentioned form. Table 5.4 and 5.5, on the other hand shows the independent energy storage and dissipative capacitances. This is one of the most important findings of our research, as all other capacitive models have mixed conserved and dissipative terms. However, in our model, the energy conserving capacitances are estimated simply from the conserved current components that were calculated using equations (5.4) and (5.5). 1, ( ) ; , , , . , ii cons Ccii tvib Ccij tv jb i j g d s j ib = ∂ − Σ ∂ = ≠ (5.10) where Ccii,Ccij are the conserved components of the capacitor. In equation (5.9) and all the subsequent equations, the subscript notation ‘c’ or ‘d’ stands for conserved or dissipative components. Fig. 5.2 shows the normalized capacitance plots against different values of channel potential in 180 nm process parameters. The capacitance plot consists of total, conserved and dissipative capacitances that are calculated using respective currents. ~44~ 0.25 0.5 0.75 1 1.25 1.5 1.75 0.2 0.2 0.4 0.6 Cgs Ccsg Csg Cdg Ccdg Cddg Cdsg Cdds Ccds Cds Cgd Csd Cdsd Ccsd Figure 5.2 Total, Conserved and Dissipative Capacitances vs vds Table 5.3: Total Capacitances TOTAL CAPACITANCES Linear Saturation CutOff Cgb ( )2 2 3(1 ) ( )2 2 k vgdt vgst coxL k v v gdt gst − + + 2 2 3(1 ) k c L + k ox 2 2 (1 ) k coxL + k Cgd 2 ( 2 ) 3 ( )2 vgdt vgst coxLvgdt vgdt vgst + + 0 0 Cgs 2 (2 ) 3 ( )2 vgdt vgst coxLvgst vgdt vgst + + 2 3 coxL 0 Csg 2 8 3 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 2 coxL 0 Csb 2 k Ccsg 2 k Ccsg 0 ~45~ Csd 2 (1 ) ( 3 ) 6 ( )2 k vgdt vgdt vgst coxL vgdt vgst + + + 0 0 Cdg 3 2 8 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 6 coxL 0 Cdb 2 k Ccdg 2 k Ccdg 0 Cds 2 (1 ) (3 ) 6 ( )2 k vgst vgdt vgst coxL vgdt vgst + + − + 2 1 6 k c L ox + − 0 Table 5.4: Conserved Capacitances CONSERVED CAPACITANCES Linear Saturation CutOff Cgb 2 2 ( )2 3(1 ) ( )2 k vgdt vgst coxL k v v gdt gst − + + 2 2 3(1 ) k c L + k ox 2 2 (1 ) k coxL + k Cgd 2 ( 2 ) 3 ( )2 vgdt vgst coxLvgdt vgdt vgst + + 0 0 Cgs 2 (2 ) 3 ( )2 vgdt vgst coxLvgst vgdt vgst + + 2 3 coxL 0 Ccsg 2 8 3 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 2 coxL 0 Ccsb 2 k Ccsg 2 k Ccsg 0 Ccsd 2 (1 ) ( 3 ) 6 ( )2 k vgdt vgdt vgst coxL vgdt vgst + + − + 0 0 ~46~ Ccdg 3 2 8 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 6 coxL 0 Ccdb 2 k Ccdg 2 k Ccdg 0 Ccds 2 (1 ) (3 ) 6 ( )2 k vgst vgdt vgst coxL vgdt vgst + + − + 2 1 6 k c L ox + − 0 Table 5.5: Dissipative Capacitances DISSIPATIVE CAPACITANCES Linear Saturation CutOff Cddg ( )(3 2 14 3 2 ) 3 30 coxL vgst vgdt vgdt vgdtvgst vgst vgdt vgst − + + ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 1 10 coxL 0 Cdds 2 (1 ) ( ) (7 3 ) 3 30 k coxL vgst vgdt vgst vgdt vgst vgdt vgst + − + − ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 2 1 10 k c L ox + − 0 Cddb 2 ( )(3 2 14 3 2 ) 3 30 coxk L vgst vgdt vgdt vgdtvgst vgst vgdt vgst − + + − ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 2 10 k c L ox − 0 Cdsg Cddg − Cddg − 0 Cdsd 2 (1 ) ( ) (3 7 ) 3 30 k coxL vgdt vgst vgdt vgdt vgst vgdt vgst + − + ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 0 0 Cdsb Cddb − Cddb − 0 ~47~ 5.3 EQUIVALENT CIRCUIT Cgs Cbs Cbd Cgd itt,cons itt,diss Ic0 Source Drain Gate Substrate is ig id ib Cgb MOSFET ig is ib id Figure 5.3: Equivalent Circuit We have developed an equivalent circuit in this section by following the method used by Lim Fossum [5.1]. Tables [5.35.5] showed that the capacitances are not reciprocal, which makes the capacitance representation using two terminal reciprocal capacitances impossible if these capacitances are made to represent the total first order drain current. However, equation (5.4) can be rewritten with reciprocal capacitors [Appendix A5.13] as id1, cons Cgd tvdg Cbd tvdb itt, cons = ∂ + ∂ + (5.11) where itt, cons (Cgd Ccdg ) tvgb (Ccsd Ccds ) tvsb Ccsd tvds = − ∂ + − ∂ + ∂ (5.12) The dissipative component of current from equation (5.3) can also be written in terms of dissipative capacitances as id1, diss Cddd tvdb Cddg tvgb Cdds tvsb itt,diss is1, diss = ∂ − ∂ − ∂ = =− (5.13) Fig.5.3 shows an equivalent circuit of a four terminal MOSFET. The circuit is equivalent to Lim Fossum’s, but we have broken the transcapacitive transport current itt into conserved and ~48~ dissipative components. There are three current components flowing from the drain to the source terminal. The current component responsible for the first order power dissipation in the channel is represented by itt,diss. The conserved current component is represented by itt,cons. Ic0 represents the steady state zero order current. Two terminal reciprocal capacitances Cgd, Cgs, Cbd, Cbs and Cgb represents the conserved gate to drain, gate to source, substrate to source, substrate to drain and gate to substrate capacitances respectively. These reciprocal capacitances do not conserve energy by themselves; the conserved component of itt must be included. Cddd, Cddg, Cdds in equation (5.13) represents the dissipative drain to drain, drain to gate and drain to source capacitances respectively. ~49~ CHAPTER VI VI. COMPARISON AND DISCUSSION In this section we compare our results with LimFossum’s SOI model [6.16.3] and the BSIM Capacitive Model [6.46.5]. We also discuss the mechanism of net transfer of energy from the gate to the channel and show that the higher order dissipative terms modify the total power equation and have significant effects at higher frequencies. 6.1 MODEL VERIFICATION AND ADVANTAGES Our model verifies that Ward’s [6.6] method of channel charge partitioning works correctly when the bulk charge has a linear dependence on the channel potential (vsb). Our model also verifies LimFossum’s equations for a fully depleted SOI MOSFET that uses Ward’s partition scheme. It predicts the same source and drain currents, and hence the same terminal capacitances ( ij C ) as shown in Fig. 6.1. However, we are able to partition these total terminal capacitances into conserved ( Ccij ) and dissipated ( Cdij ) components. The partitioning approach to capacitances offers several advantages over conventional transcapacitances: • The energy stored in the conserved capacitances can be predicted. • They can be made to agree with Meyer’s [6.7] capacitances if the body effect and body bias are ignored. Fig 6.1 and Fig 6.2 shows the capacitances. The total capacitance shown in Fig 6.1 is separated into conserved and dissipative capacitances in Fig 6.2 and is written as Cij Ccij Cdijwhere i, j g, s,d = + = ~50~ 0.25 0.5 0.75 1 1.25 1.5 1.75 0.2 0.2 0.4 0.6 ox cap c L vds 0.25 0.5 0.75 1 1.25 1.5 1.75 0.2 0.2 0.4 0.6 ox cap c L vds Figure 6.1: Terminal capacitances vs vds Figure 6.2: Capacitance vs vds Our other significant contribution has been in the power estimation. Our models have improved the device power estimation by implementing two important concepts: • First order terms have to be included for power dissipation estimation as they become significant at higher frequencies. • Stored components can be ignored for computationally efficient power dissipation estimation. The average device power computation is then possible by taking dissipative current times voltage and integrating them over time. 6.2 ENERGY PUMPING It is important to understand the pumping action of the gate to understand the power components from different sources. When the gate undergoes a rising (falling) transition, electrons (holes) are sucked out of the source terminal and stored in the channel. During the falling transition, these electrons (holes) are pushed out of the channel into the drain terminal. Even though the gate charge integrates out and there is no net charge transfer, there is transfer of energy from the gate to the channel. The gate acts as a energy source which allows the electrons (holes) to move in the channel, while the channel acts as a recipient of this energy. Moreover, if power calculations are done using only the channel current components, it may appear that the MOS transistors are generating extra energy in the channel. In reality, power is pumped from the gate to the channel and when the gate contributions are added, the conserved ~51~ terms cancel out. However, if the gate contributions are neglected, the channel ends up looking like an energy generator. Therefore it is not appropriate to integrate the channel currents alone for the power computation. Contributions from the gates need to be included. Fig. 6.3 shows the pumping action of the gate. Figure 6.3: Gate pumping action 1×1010 2×1010 3×1010 4×1010 5×1010 0.00003 0.00002 0.00001 0.00001 0.00002 0.00003 Pg1,cons Pc1,cons Figure 6.4: Average conserved gate and channel power vs. frequency Fig. 6.4 shows the average conserved gate ( Pg1,cons ) and channel ( Pc1,cons ) power plots against frequency for 180 nm process parameters. The positive power from the gate shows that energy is flowing from the gate to the channel, while the negative channel power shows the energy generation at the channel. Since these average powers are equal and opposite, they cancel out over a complete cycle and contribute no net energy in the channel. This is all possible due to the existence of an energy function for the conserved components. The existence of ~52~ energy function validates the notion that the conserved terms do not contribute any net power dissipation in the channel. It also makes it possible to leave out power terms that do not contribute to net power dissipation in the total power equation, making the simulation simple and computationally efficient. This is explained in detail in the following section. 6.3 TOTAL FIRST ORDER POWER It is possible to derive the total first order MOS power by using the equation P ig1vgb id1vdb is1vsb = + + (6.1) The problem here is the complexity in the first order current terms. Other than the first order gate current, first order drain and source currents have both the conserved and dissipative terms, which are not separated. As mentioned in previous chapters, the gate and the conserved components of drain and source currents contribute no net power dissipation in the channel. Its presence just adds the extra complexity and slows down the simulation process. The separation of the first order terms into energy conserving and power dissipating terms on the other hand, simplifies the equation as energy conserving terms are taken out from the simulation. The total first order power then reduces to P id1,dissvdb is1, dissvsb = + (6.2) It should also be pointed out that leaving the gate component altogether and using the equation P id1vdb is1vsb = + (6.3) is not a very good option. In that case, as mentioned in section (6.1), the conserved channel power component acts as an independent source of energy. Equations using such models are inconsistent and should be avoided. 6.4 SIMULATION EXAMPLE A simple simulation is used to show the importance of first order power using only the dissipative components. Fig. 6.5 shows the idealized voltage waveforms for the drain and the gate terminals used to turn a transistor on then off. ~53~ Figure 6.5: Idealized voltage waveforms The average dissipative power from the first transition (vds=vdd) when vgb goes from low at t0 to high at t1 is computed by 1 1 1 ( 1, 1, ) ( 0 1) ( 1 0) 0 t Pc t id dissvdb is dissvsb dt t t t t = ∫ + → − (6.4) If we assume the source and the substrate are at the same potential (vsb=0), equation (6.4) can be rewritten as 1 1 ( ) 1( ) ( ) 0 1, 0 1 1 0 t Pc t id dissvdb dt t t t t = ∫ → − (6.5) In the second power dissipating transition, when the gate terminal is high, the drain swings from high at t1 to low at t2. The dissipative power equation (6.4) reduces to 1 2 1( ) ( ) 1, 1 2 2 2 1 t Pc id dissvdbdt t t t t t = ∫ → − (6.6) During the interval t2 to t4, there is no power dissipation in the channel (vdb=0). Even though energy flows from the gate to the channel as vgb changes, the energy is transferred to the channel carriers and is not dissipated. The final power transition occurs when the drain waveform swings from low at t4 to high at t5. As the gate voltage has already reached a steady low value, the power equation becomes ~54~ 1 5 1( ) ( ) 1, 4 5 5 4 4 t Pc id dissvdb dt t t t t t = ∫ → − (6.7) The total dissipative power for a complete cycle is computed taking the sum of all these powers 1 ( 0 1) ( 1 2) ( 4 5) Pc P t t P t t P t t = → + → + → (6.8) For a complete cycle, energy is conserved. This allows us to leave out the conserved component from the power equation for computationally efficient power dissipation prediction. Nonetheless, the total dissipative powers predicted by equation (6.8) have first order terms. These first order dissipative components become significant at higher frequencies and modify the total power dissipated in the channel as shown in Fig 6.6. The total power is no longer constant, and at high frequencies becomes dependent on the switching frequencies. 1×1010 2×1010 3×1010 4×1010 5×1010 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 P Pc0 Pc1,diss Fig 6.6: Total power vs. frequency The result also shows that we need to be extra careful while doing the power measurements. It is not appropriate to look only at the channel dissipation; the first order power dissipation does have contributions from the gate. If the power dissipation is estimated by just considering the total channel power, there would be an extra negative component from the conserved energy. In that case, the channel would seem to act as an energy generator. Fig 6.7 and Fig 6.8 shows the current and the corresponding power plots. ~55~ Figure 6.7: Current Plots Figure 6.8: Power Plots 0.0031 0.0021 0.0011 0.0001 0.0009 0.0019 0 1E12 2E12 3E12 4E12 5E12 6E12 7E12 8E12 id0 id1D is1D id1C is1C ig1 T(sec) I(A) 0.008 0.006 0.004 0.002 0 0.002 0.004 0.006 0 1E12 2E12 3E12 4E12 5E12 6E12 7E12 8E12 p0 p1 D p1 C T(sec) P(W) ~56~ CHAPTER VII VII. DEPENDENCE OF THE BSIM ABULK PARAMETER ON THE SOURCE POTENTIAL In this chapter, the capacitive model is extended to include the source potential (vsb) dependence of the bulk charge coefficient Abulk. Until this chapter, the BSIM bulk parameter, Abulk [Appendix A7.1], was assumed to be constant with respect to the source potential, which made the derivation of the energy function possible. It also made the evaluation of the terminal capacitances straightforward, sacrificing very little accuracy. However for circuits where vsb is not constant and bulk parameter dependence is included, unlike the Lim and Fossum model, the BSIM capacitive model fails to give an energy function for the conserved power components [Appendix A7.2]. The energy supplied from the gate does not balance with the energy generated in the channel and an extra power component shows up in the channel that has no physical basis. The term that gives energy storage in our model (equation (4.21)) does not give energy storage in BSIM, which makes the BSIM model inconsistent for power and energy prediction. In general, when the conserved power components are integrated over a complete switching cycle and the transistor is returned to the original state, there is a non nonzero power contribution. This is where the inconsistency of the BSIM model is evident. The BSIM bulk charge coefficient has vsb dependence and when this is included, the BSIM model: • Generates extra current that has no physical basis • Gives a net nonzero power that shows up in the channel from the terms that are supposed to be conserved, • Fails to give an energy function from all of the conserved components ~57~ It should also be pointed out that we are not finding the energy function for the total transistor power, as not all the power components are conserving. It is also not true that the BSIM model has no energy function. It has a quasienergy function; the same term that shows up in our model (Chapter 4) also show up in the BSIM model. Obviously for those terms there is an energy function. But, the BSIM model also has some extra terms due to the vsb dependence that do not show up in our model, which makes it impossible to find an energy function for all of the conserved components. In other words, the quasiconserving BSIM model is inconsistent. It generates extra power in the channel that has no physical basis. Though the extra term has no physical rationale, it is thought to be from the incomplete mathematical representation of the square root dependence of the bulk charge on the channel potential vcb, which the BSIM model tries to linearise using the first two terms of a Taylor’s expansion. It can then be assumed that if the higher order terms are included that were left out in the Taylor’s expansion, the BSIM model should provide the correct energy function. Nonetheless, the good news is that we can still apply our model to BSIM by comparing the energy differences between the models. By doing so, we should be able to separate out the energy function from all the terms except for those that have vsb dependence and also evaluate the physically inconsistent extra dissipating components. 7.1 EVALUATION OF EXTRA CURRENT COMPONENTS Our conserved components of the gate ( ig1, cons ), source ( is1, cons ) and the drain ( id1, cons ) currents are given in Appendix (A3.3.5), and the respective BSIM components ( ig1cons, B , is1cons, B and id1cons, B ) can be evaluated including the source potential dependence on the bulk charge parameter using the equations given in Appendix (7.3). ~58~ The difference in the first order gate current due to the source dependence of the BSIM bulk charge parameter is then given by ig1, cons Extra ig1cons, B ig1, cons = − (7.1) Similarly, the difference in the conserved first order drain current is given by id1, cons Extra id1cons, B id1cons = − (7.2) and the difference in the first order source current is given by is1, cons Extra is1, cons, B is1, cons = − (7.3) These extra conserved first order gate, drain and the source currents predicted by equations (7.1 7.3) causes extra power in the channel that has no physical basis, and can be estimated using Pg1,cons Extra Pg1,cons,B Pg1,cons = − (7.5) Pc1,cons Extra Pc1,cons,B Pc1,cons = − (7.6) P1,cons Extra Pg1,cons Extra Pc1,cons Extra = + (7.7) where Pg1, cons, B ig1, cons, B vgb = and Pc1, cons, B id1, cons, B vdb is1, cons, B vsb = + 7.2 SIMULATION EXAMPLE In this section, a simple simulation example is presented using a pass transistor logic. Though it is not straightforward to separate the conserved and the dissipative power components in the BSIM model (due to the channel charge partition), the example does show the existence of extra power due to vsb dependence of Abulk. A pass transistor is chosen because they have a high vsb swing which makes the BSIM models’ unphysical effect (generation of extra power) more ~59~ pronounced. For the BSIM model to be consistent, it is assumed that the difference from the first order dissipative power should give the correction term. This correction term should then balance out the extra power component generated in the channel. vdd vdd vddvt vdb vgb vsb t0 t1 t2 t3 t4 t5 Time Voltage G D S Figure 7.1: Pass transistor simulation Voltage Waveforms (180nm process parameters) Fig. 7.1 shows the idealized voltage waveforms for the drain, gate and the source terminals. The drain terminal is assumed to be high ( vdd ) during the entire simulation, while the gate and the source potentials are varied to calculate the extra power component. In the first transition (t0 to t1), the gate terminal goes from low (0) at t0 to high ( vdd ) at t1, while the source potential remains low (0). The transistor enters the saturation as soon as the gate to source potential vgb vsb − becomes greater than the threshold voltage vt . The extra energy Et1 , calculated from the extra power (eq. (7.7)) is then given by 1 1 1, 0 t Et P cons dt t Extra = ∫ (7.8) During the second transition (t1 to t2), the gate terminal stays high ( vdd ) and the pass transistor remains in the saturation. The source terminal on the other hand, goes from low (0) to high ( vdd vt − ) and the extra energy Et2 becomes ~60~ 2 2 1, 1 t Et P cons dt t Extra = ∫ (7.9) The transistor now enters cutoff (at t2) and remains there even though the gate and source terminals come back to their original states at t4 and t5. The extra energies during these transitions are given by 3 3 1, 2 t Et P cons dt t Extra = ∫ 4 4 1, 3 t Et P cons dt t Extra = ∫ (7.10) 5 5 1, 4 t Et P cons dt t Extra = ∫ Combining all, total energy difference ( Et ) can be written as Et Eti where i 1 to 5 i = Σ = (7.11) For a complete cycle, energy should have been conserved and there should have been no contribution. But as shown by equation (7.11) and Fig 7.2, this is not the case. There is some extra power in the channel P1, cons Extra , which is more than the first order dissipative power Pc1,diss . The correction term from the difference in first order dissipative power Pc1, diss Extra that we thought would negate the extra channel power was nonexistent. 1×109 2×109 3×109 4×109 5×109 5×107 1×106 1.5 ×106 2×106 2.5 ×106 3×106 3.5 ×106 Figure 7.2: Extra power dissipation ~61~ Fig. 7.2 also shows that the frequency dependence of power components becomes significant at higher frequencies and also raises the first order power dissipation to a new value P1, which includes the first order dissipative power ( Pc1,diss ) and all other extra unphysical components ( P1,cons Extra and Pc1,diss Extra ). It also proves that the energy pumped from the gate does not balance out in the channel as was the case when Abulk was assumed to be a constant. In this particular case, the channel acts as an independent energy generator. This error, together with the noninclusion of first order dissipative power makes the BSIM model inconsistent for energy and power prediction. Fig. 7.3 compares the differences in the bulk charge parameters (Abulk vs. 1+k2) and the threshold voltages (Vt,B and Vt) between BSIM and our models, while Fig. 7.4 shows the zero order current plot for the simulation example mentioned above. From the plots 7.3 and 7.4, it is evident that our parameters match very well with the BSIM parameters when the zero order current is dominant. Figure 7.3: Abulk vs. (1+k2) and Vt’s (Top) Figure 7.4: Zero order current plots (Bottom) ~62~ Fig 7.5 shows the instantaneous first order gate, drain and source current components. Here also, the plots matches very well and the difference is evident only in the first order source current, which as mentioned above, is due to the dependence of source potential and other extra components on the BSIM bulk charge parameter Abulk [Appendix 7]. Figure 7.5: First order currents ~63~ 7.3 CONCLUSION Conventional MOS models for circuit simulation assume that the channel capacitances do not contribute to net power dissipation. Numerical integration of channel currents and instantaneous terminal voltages however shows the existence of first order dissipating terms. Given that the accuracy of the simulation depends on the physical representation of the device, it is very important that we have a reliable mathematical model that is able to represent the device behavior. Designers need these accurate models for circuit development. To overcome the limitation of conventional charge based models, a selfconsistent, first order, quasistatic, power dissipation model has been developed that is able to • Predict the exact solution to first order 1D channel equations for MOSFETs without a channel charge partition approximation provided that the charge has a linear dependence on the channel potential. • Validate the terminal currents as being the same as Ward’s channel charge partition approximation. • Validate that Ward’s partition scheme is correct as long as the charge has a linear dependence on the channel potential. • Derive the first order channel charge (qc1 ) and current (ic1) as a function of position (x) inside the channel. • Derive the first order power dissipation and conserved components. • Estimate energy function. • Separate the terminal current into conserved and dissipative components. • Identify the inconsistencies in the BSIM power model. In conclusion, there is a need to extend this work to include channel charge with a nonlinear voltage dependence that does not generate extra power dissipation in the channel that has no physical basis. ~64~ REFERENCES [1.1] J.E. Meyer, “MOS models and circuit simulation,” RCA Rev., vol. 32, pp. 4263, 1971. [1.2] D.E.Ward, “ChargeBased Modelling of Capacitance in MOS Transistors”, Stanford Electronics Lab., Stanford University, Tech. Rep. F20111, June 1981. [1.3] A.D. Snider, “Charge conservation and the transcapacitance element: an exposition,” IEEE Transaction on Education. Vol.38, no.4, November 1995. [1.4] K.A. Sakallah, YaoTsung Yen, and S.S.Greenberg, “A firstorder charge conserving MOS capacitance model,” IEEE Transactions on ComputerAided Design, vol. 9, pp. 99 108, January 1990. [1.5] S. S. Chung, “A chargebased capacitance model of shortchannel MOSFET’s,” IEEE Transactions on ComputerAided Design, vol. 8, no. 1, January 1989. [1.6] B.J. Sheu, W. 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[5.2] Daniel Foty, “MOSFET Modelling with Spice, Principles and Practice”, Prentice Hall, 1997. [5.3] S. Sharma, L.G. Johnson, “First Order, QuasiStatic, Channel Capacitance Model”…. [5.4] Yuhua Cheng and Chenming Hu, “MOSFET modeling and BSIM3 user’s guide”, Kluwer Academic Publishers, 1999. [5.5] McAndrew, C.C., Zaneski, G, Layman, P.A., Ayyar, S.G., “Accurate characterization of MOSFET overlap/fringing capacitance for circuit design”, Proceedings of the 1994 International Conference on Microelectronic Test Structures, March 2225, 1994. Pages: 1520 [5.6] Cho, D.H.; Kang, S.M.; Kim, K.H.; Lee, S.H., “An accurate intrinsic capacitance modeling for deep submicrometer MOSFET's”, IEEE Transactions on Electron Devices, Vol.42, Iss.3, March 1995, Pages: 540548 [5.7] J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective”, 2nd Edition, Prentice Hall, 2003 [6.1] H. K. Lim and J. G. Fossum, “A chargebased largesignal model for thinfilm SOI MOSFET’s”, IEEE Journal of SolidState Circuits, Vol. Sc20, no.1, February 1985. ~71~ [6.2] H. K. Lim and J. G. Fossum, “Threshold Voltage of ThinFilm SilicononInsulator (SOI) MOSFET’s”, IEEE Transactions on Electron Devices, Vol. Ed30, No. 10, October 1983. [6.3] H. K. Lim and J. G. Fossum, “Currentvoltage characteristics of thinfilm SOI MOSFET’s in strong inversion, “ IEEE Trans. Electron Devies, vol ED22, pp. 10171023, Nov. 1975. [6.4] BSIM Group, “BSIMSOI3.1 MOSFET Model  Users’ Manual”, 2003. [6.5] Xuemei et.al, “BSIM4.3.0 MOSFET Model  Users’ Manual”, 2006. [6.6] D.E.Ward, “ChargeBased Modelling of Capacitance in MOS Transistors”, Stanford Electronics Lab., Stanford University, Tech. Rep. F20111, June 1981. [6.7] J.E. Meyer, “MOS models and circuit simulation,” RCA Rev., vol. 32, pp. 4263, 1971. ~72~ APPENDICES APPENDIX 1: 180 NMOS SPICE model parameters A1.1 180nm NMOS SPICE Parameters .model NMOS NMOS +Level = 49 +Lint = 4.e08 Tox = 4.e09 Clc= 0.0000001 Cle= 0.6 +Vth0 = 0.3999 Rdsw = 250 Dwc= 0 Vfbcv= 1 +lmin=1.8e7 lmax=1.8e7 wmin=1.8e7 wmax=1.0e4 +Tref=27.0 version =3.1 Cf= 1.069e10 Dlc= 4E08 +Xj= 6.0000000E08 Nch= 5.9500000E+17 +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 +wwn= 0.00 ll= 0.00 +lw= 0.00 lwl= 0.00 wint= 0.00 +wl= 0.00 ww= 0.00 wwl= 0.00 +Mobmod= 1 binunit= 2 xl= 0 +xw= 0 binflag= 0 +Dwg= 0.00 Dwb= 0.00 +K1= 0.5613000 K2= 1.0000000E02 +K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000 +Dvt2= 8.0000000E03 Dvt0w= 0.00 Dvt1w= 0.00 +Dvt2w= 0.00 Nlx= 1.6500000E07 W0= 0.00 +K3b= 0.00 Ngate= 5.0000000E+20 +Vsat= 1.3800000E+05 Ua= 7.0000000E10 Ub= 3.5000000E18 +Uc= 5.2500000E11 Prwb= 0.00 +Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E02 +A0= 1.1000000 Keta= 4.0000000E02 A1= 0.00 +A2= 1.0000000 Ags= 1.0000000E02 B0= 0.00 +B1= 0.00 +Voff= 0.12350000 NFactor= 0.9000000 Cit= 0.00 +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 +Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000 +Pclm= 5.0000000E02 Pdiblc1= 1.2000000E02 Pdiblc2= 7.50000E03 +Pdiblcb= 1.3500E02 Drout= 1.7999999E02 Pscbe1= 8.66000E+08 +Pscbe2= 1.00000E20 Pvag= 0.2800000 Delta= 1.0000000E02 +Alpha0= 0.00 Beta0= 30.0000000 +kt1= 0.3700000 kt2= 4.0000000E02 At= 5.5000000E+04 +Ute= 1.4800000 Ua1= 9.5829000E10 Ub1= 3.3473000E19 +Uc1= 0.00 Kt1l= 4.0000000E09 Prt= 0.00 +Cj= 0.00365 Mj= 0.54 Pb= 0.982 +Cjsw= 7.9E10 Mjsw= 0.31 Php= 0.841 +Cta= 0 Ctp= 0 Pta= 0 +Ptp= 0 JS=1.50E08 JSW=2.50E13 +N=1.0 Xti=3.0 Cgdo=2.786E10 +Cgso=2.786E10 Cgbo=0.0E+00 Capmod= 2 +NQSMOD= 0 Elm= 5 Xpart= 1 +Cgsl= 1.6E10 Cgdl= 1.6E10 Ckappa= 2.886 ~73~ APPENDIX 2: 180 PMOS SPICE model parameters A2.1 180nm PMOS SPICE Parameters .model PMOS PMOS +Level = 49 +Lint = 3.e08 Tox = 4.2e09 +Vth0 = 0.42 Rdsw = 450 +lmin=1.8e7 lmax=1.8e7 wmin=1.8e7 +wmax=1.0e4 Tref=27.0 version =3.1 +Xj= 7.0000000E08 Nch= 5.9200000E+17 +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 +wwn= 0.00 ll= 0.00 +lw= 0.00 lwl= 0.00 wint= 0.00 +wl= 0.00 ww= 0.00 wwl= 0.00 +Mobmod= 1 binunit= 2 xl= 0.00 +xw= 0.00 +binflag= 0 Dwg= 0.00 Dwb= 0.00 +ACM= 0 ldif=0.00 hdif=0.00 +rsh= 0 rd= 0 rs= 0 +rsc= 0 rdc= 0 +K1= 0.5560000 K2= 0.00 +K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000 +Dvt2= 1.0000000E02 Dvt0w= 0.00 Dvt1w= 0.00 +Dvt2w= 0.00 Nlx= 9.5000000E08 W0= 0.00 +K3b= 0.00 Ngate= 5.0000000E+20 +Vsat= 1.0500000E+05 Ua= 1.2000000E10 Ub= 1.0000000E18 +Uc= 2.9999999E11 Prwb= 0.00 +Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E03 +A0= 2.1199999 Keta= 2.9999999E02 A1= 0.00 +A2= 0.4000000 Ags= 0.1000000 B0= 0.00 +B1= 0.00 +Voff= 6.40000000E02 NFactor= 1.4000000 Cit= 0.00 +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 +Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000 +Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2= 8.0000000E05 +Pdiblcb= 0.1450000 Drout= 5.0000000E02 Pscbe1= 1.0000000E20 +Pscbe2= 1.0000000E20 Pvag= 6.0000000E02 Delta= 1.0000000E02 +Alpha0= 0.00 Beta0= 30.0000000 +kt1= 0.3700000 kt2= 4.0000000E02 At= 5.5000000E+04 +Ute= 1.4800000 Ua1= 9.5829000E10 Ub1= 3.3473000E19 +Uc1= 0.00 Kt1l= 4.0000000E09 Prt= 0.00 +Cj= 0.00138 Mj= 1.05 Pb= 1.24 +Cjsw= 1.44E09 Mjsw= 0.43 Php= 0.841 +Cta= 0.00093 Ctp= 0 Pta= 0.00153 +Ptp= 0 JS=1.50E08 JSW=2.50E13 +N=1.0 Xti=3.0 Cgdo=2.786E10 +Cgso=2.786E10 Cgbo=0.0E+00 Capmod= 2 +NQSMOD= 0 Elm= 5 Xpart= 1 +Cgsl= 1.6E10 Cgdl= 1.6E10 Ckappa= 2.886 +Cf= 1.058e10 Clc= 0.0000001 Cle= 0.6 +Dlc= 3E08 Dwc= 0 Vfbcv= 1 ~74~ APPENDIX 3: MOSFET CURRENT EQUATIONS The zero and first order channel charges as well as currents were used in chapter 3. However, the derivations were not shown, which is given in this appendix. It should also be pointed out that these derivations are very tedious and results would not have been possible without the help of sophisticated tools like Mathematica. A3.1 Zero Order Current Component In equation (3.27), the zero order charge qc0 at a distance x along the channel is given by ( 2(1 / ) 2 / qc0 qs x L qd x L = − − + where L is the length of the channel. qs and qd are the source and the drain charges per unit length as given in (3.14) and (3.18). These charges can be substituted into the steady state current equation (3.28) to represent Ic0 in terms of voltages. ( 2 2) ( 2 2) 02 2 Ic qd qs vgst vgdt LcoxK LCc μ μ = − = − (A3.1) In pinchoff saturation, the drain charge density ( qd ) is zero. This reduces the zero order current (A3.1) to 2 0 2 cox Ic vgst LK μ = (A3.2) The corresponding drain to source potential in saturation ( vdssat ) can be estimated by setting vgdt vgb vt vsb K(vdb vsb ) 0 = − − − − = so that vgb vt vsb vdssat K − − = where 2 1 k SOI K Abulk BULK ⎧ + → = ⎨ → ⎩ as defined in (3.24). ~75~ In cutoff, it is assumed that there is no channel current, which is made possible by setting the source charge density qs to zero. Ic0 0 = (A3.2) (A3.1), (A3.2) and (A3.3) give the usual equations for the steady state current neglecting velocity saturation effects. A3.2 First Order Channel Charge and Channel Current The derivation of first order channel charge and current components are one of the most important findings of our research. The first order channel charge allows calculating the first order channel current without a charge partition, which can be used to calculate the first order drain and source currents. The first order channel current also makes it possible to derive the energy stored and dissipative power components. Since it is crucial component of our research, a detailed derivation is presented in this appendix. Taking charge density as a function of potential along the channel, and keeping terms of first order in time derivatives, the current continuity equation (3.25) can be written as ( 0 1 1 0 ) 0 d d d Cc d qc qc qc qc qc dx dx dx μ dt + =− (A3.2.1) Rearranging the terms, first order channel charge per unit length becomes 1 [ ] 1 0 1 0 0 Cc d qc qc x dxdx c x c qc dt μ = − ∫ ∫ + + (A3.2.2) where c1 and c0 are constants of integration, and can be calculated using the boundary condition qc1 0 = at x = 0 and x = L 0 0[ ] 0 (4 5 2 2 ) 4 2 4 15( 2 2)3 Cc d c qc x dxdx dt x q q d q q d q q d q Cc d s dt d d dt s s dt s L qs q q d s μ μ = ∫ ∫ → − + = − + (A3.2.3) ~76~ 1 0[ ] ( ( 5 5 3 2 4 5) (4 5 5 2 3 5) ) 4 15( 2 2)3 Cc d c qc x dxdx dt x L q d q q q q q q q q q q d q Cc d dt d d d s s s d d s s dt s L qd qs μ μ = ∫ ∫ → − − + − − + = − + (A3.2.4) Substituting the values of c0, c1 and qc0 in (A3.2.2), the first order charge at any point x along the channel becomes 4(4 5 2 2 ) 1 {4 ( 1 2 2 ( 2 2)3 ( ) 15 (( 5 5 4 3 2( ) 4 2 3( ) 4(4 ) 4 ( 4 )) ) /( )2( )3) L q q q d q q d q q d q q C L s d s dt d d dt s s dt s c c q q qs L x qd x d s L q d q q d q q q d q d q q q d q d q d dt d s dt s d s dt d dt s d s dt d dt s q q d q d q q q d q d q x q q q q d s dt d dt s d s dt d dt s d s d s μ − + = − + − + − + − + − + + − + − + + + − + 2 2 3/ 2 1 ( ) 2 2 ( (4 5 ) ( 2 2)3 ( )( )( ) ))) qs L x qd x d d d Lqs qd qs qd qd qs qs qs q q L dt dt dt d s q q q q q d q q d q x d s d s d dt d s dt s − ⎛ − + ⎞ ⎜ ⎟ − + − ⎜⎜ ⎟⎟ − ⎝ ⎠ − + − (A3.2.5) The first order channel current at any position x along the channel can now be estimated using 1 ( 0 1 1 0) i q d q q d q c C c dx c c dx c c μ = + (A3.2.6) Taking derivatives of qc0 and qc1, and substituting the corresponding values, (A3.2.6) expands to {4( ( 4 3 4 2 2 4 3 4 4) 1 15( )2( )3 (4 4 4 3 4 2 2 3 4)} 10( )( 2(1 ) 2 { (2 (3 2 2) ) ( 2 2)( ) } i L q d q q q q q q q q q c q q q q d dt d d d s d s d s s d s d s q d q q q q q q q q q d dt s d d s d s d s s q q q x q x d s s L d L q q d q q q q d q q q q d q q d q x S d dt d s d s dt s d s d dt d s dt s = + − − − + − + + + − − − + − + − − − − − (A3.2.7) As mentioned above, this is one of the most important findings of our research and can be solved to find the first order drain ( ic1 id1, x L) − = → and source (ic1 is1, x 0) = → current components, which are shown in Table 3.1. These results obtained without partitioning the channel charge are ~77~ in agreement with previous results (LimFossum and BSIM) which were obtained using Ward’s partition. Therefore we have verified that Ward’s partition is correct when the voltage dependence of Abulk is ignored and the channel charge is linearly dependent on vcb. A3.3 First Order Gate Current We present here the derivation of the gate current. These derivations are not different than what have been done already and can be found in the literature. The total gate charge (Qg ) can be estimated by integrating the gate charge density from the source (x=0) to the drain terminals (x=L) as 0 L Qg qgdx = ∫ (A3.3.1) where channel current equation ( , ) ( , ) ( ) 0 L vdb ic x t dx qc x t dvcb x vsb ∫ = μ ∫ can be solved to get ( , ) ( ) 0 ( , ) L vdb q x t dx c dv x v i x t cb sb c ∫ = μ ∫ (A3.3.2) Replacing 0 L ∫ dx in (A3.3.1), it can be rewritten as ( , ) ( , ) ( ) 0 vdb Qg qg x t qc x t dvcb x ic vsb μ = ∫ (A3.3.3) which can be solved to get the total gate charge. ( )2 2 ( ) 12( ) 2 vdb vsb K vdb vsb Qg coxL vgb v fb vsb K vdb vsb vgst φ ⎛ ⎞ ⎜ − − ⎟ = ⎜ − − − − + ⎟ ⎜ − ⎟ ⎜ − ⎟ ⎝ ⎠ (A3.3.4) The first order drift current flowing in the gate terminal can now be calculated from ~78~ 1 d dvgb dQg dv dQg dv dQg i Q db sb g dt g dt dv dt dv dt dv gb db sb = = + + (A3.3.5) Taking the derivatives, the first order gate current in the linear region becomes (3( 1) ( )2 2 ( 2 ) 2 (2 ) ) 1 3 ( )2 K d v v v v d v v v v v v d v i c L dt gb gdt gst gdt dt gdt gdt gst gst gdt gst dt gst g ox K v v gdt gst − + + + + + = + (A3.3.6) In pinchoff saturation, when qd 0 = , ig1 reduces to 1 (3( 1) 2 ) 3 coxL d d ig K vgb vgst K dt dt = − + (A3.3.7) In cutoff, though the drift components of the drain and the source currents are zero, the gate still has some current, which can be estimated by setting qs 0 = in equation (A3.3.5) 1 ( 1) coxL d ig K vgb K dt = − (A3.3.8) ~79~ APPENDIX 4: MOSFET POWER EQUATIONS This appendix describes the detailed derivations of MOS power components that were used in chapter 4. To avoid confusion with the general definition of the static and dynamic power terms, channel power components are defined as the zero and the first order powers in the dissertation. It should be pointed out that the zero order power defined in equation (4.14) is different than the static power. In general, static power is defined as being independent of time (time invariant). However, the zero order power that has been used in this research is time variant. Although there is no explicit time dependence, it depends on the terminal voltages that change in time. The first order power on the other hand, depends on the time derivatives of the terminal voltages, while the dynamic power that has been used in the literature depends on energy stored in external capacitances which is dissipated by both zero order and first order power in the transistor. A4.1 Zero order power The zero order power is given in equation (4.14) as 0 [ 0( 0( ))] 0 L d Pc Ic vcb x dx dx = ∫ (A4.1.2) since Ic0 is independent of the position along the channel x, equation (A4.1.1) reduces to Ic0vds where Ic0 is given in equation (A4.1) as ( 2 2) 0 2 Ic cox vgst vgdt KL μ = − (A4.1.2) From (A4.1.2) and (A4.1.1) ( 2 2) 0 2 Pc coxvds vgst vgdt LK μ = − (A4.13) In pinch off saturation, the change density at the drain is assumed to be zero, which reduces (A4.1.3) to 2 0 2 Pc coxvdsvgst LK μ = (A4.1.4) In cutoff region, when the source charge density becomes zero, equation (A4.1.4) further reduces to 0. ~80~ A4.2 First order dissipated power In equation (4.15), the first order channel dissipated power is given by 1, [ 1( 0( ))] 0 L d Pc diss ic vcb x dx dx = ∫ (A4.2.1) where ic1 is the first order channel current given by (A3.2.7). Solving the integral, (A4.2.1) reduces to ( )2(3 2 3 2 1, 30 ( )3 7 ( ) ) P L q q q d q q d q c diss C q q d s d dt d s dt s c d s q d q d q q d dt d dt s s = − + + + + (A4.2.2) where , , , q q d q d q d s dt d dt s are defined in the List of Symbols. Substituting the values of qd ,qs , d qd , d qs dt dt in terms of ' ' v s and d v s dt as given in (3.14), (3.15), (3.18) and (3.19) into (A4.2.2) gives ( )(3 2 3 2 1, 30( )3 7 ( ) ) coxL d d Pc diss vds vgst vgdt v gdt vgdt v gst vgst v v dt dt gdt gst v d v d v v gdt dt gdt dt gst gst = − + + + + (A4.2.3) In pinchoff saturation region, as qd 0 = equation (A4.2.3) reduces to 1, 10 coxL d Pc diss vds vgst dt = (A4.2.4) and in cutoff, the first order dissipative power becomes Pc1,diss 0 = A4.3 FIRST ORDER CONSERVED POWER The first order channel conserved power is given in (4.16) by ~81~ 1, [ 0( 1)] 0 L d Pc cons vcb ic dx dx = ∫ (A4.3.1) where ic1is the first order channel current and vcb0 is the zero order channel potential. Integrating, equation (A4.3.1) expands to 1, [ 3( ) 6 4( ( 2 ) (2 ))( ) ] ( )2 coxL d d Pc cons vgdt vgdt vgst vgst K dt dt v d v v v v d v v v v gdt dt gdt gdt gst gst dt gst gdt gst gbt vgdt vgst = − − + + + + + + (A4.3.2) In pinchoff saturation, with qd 0 = , equation (A4.3.3) reduces to 1, ( 3 ) 6 coxL d Pc cons vgst vdb vsb dt = − + (A4.3.3) and in cutoff, it becomes Pc1,cons 0 = A4.4 Energy function validation for the gate Clairaut’s theorem states that, “If two second order partials are continuous, their derivatives will be equal”. The same theorem can be used to check the equality of second order partial and verify the existence of an energy function for the conserved power. Using equation (4.18), the conserved first order gate power is given by (3( 1) ( )2 1, 1 3 ( )2 2 ( 2 ) 2 (2 ) ) coxL d Pg cons ig vgb vgb K vgb vgdt vgst K v v dt gdt gst v d v v v v v v d v gdt dt gdt gdt gst gst gdt gst dt gst = = − + + + + + + (A4.4.1) In terms of energy, the conserved power can be written as ~82~ 1, E dv Eg dvgb Eg dv Eg dv P db sb g cons v dt v dt v dt v dt gb db sb ∂ ∂ ∂ ∂ = = + + ∂ ∂ ∂ ∂ (A4.4.2) Comparing (A4.4.1) and (A4.4.2), the derivatives of the gate energy with respect to voltages give 2 (2 ) 3( )2 Eg coxLvgbtvgst vgdt vgst vsb v v gdt gst ∂ − + = ∂ + (A4.4.3) 2 ( 2 ) 3( )2 Eg coxLvgbtvgdt vgdt vgst vdb v v gdt gst ∂ − + = ∂ + (A4.4.2) 2( )2 1 (6 ) 6 ( )2 Eg vgdt vgst coxLvgbt vgb K v v gdt gst ∂ − = − ∂ + (A4.4.3) As mentioned earlier, an energy function exists if and only if the second order partials of (A4.4.3) (A4.4.5) are equal. Comparing (A4.4.3)(A4.4.5) ( ) ( ) Eg Eg vsb vgb vgb vsb ∂ ∂ ∂ ∂ ≠ ∂ ∂ ∂ ∂ ( ) ( ) Eg Eg vdb vgb vgb vdb ∂ ∂ ∂ ∂ ≠ ∂ ∂ ∂ ∂ It is found that the pa
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Title  First Order Quasi Static Mosfet Channel Capacitance Model 
Date  20080501 
Author  Sharma, Sameer 
Keywords  First Order Quasistatic Mosfet; First Order Power Dissipation Mos Models; Mosfet Channel Capacitances; Mosfet Equivalent Circuit; Mosfet Energy Function 
Department  Electrical Engineering 
Document Type  
Full Text Type  Open Access 
Abstract  Conventional MOS models for circuit simulation assume that the channel capacitances do not contribute to net power dissipation. Numerical integration of channel currents and instantaneous terminal voltages however shows the existence of first order dissipating terms. Given that the accuracy of the simulation depends on the physical representation of the device, it is very important that we have a reliable mathematical model that is able to represent the device behavior. Designers need these accurate models for circuit development. To overcome the limitation of conventional charge based models, a selfconsistent, first order, quasistatic, power dissipation model has been developed that is able to Predict the exact solution to first order 1D channel equations for MOSFETs without a channel charge partition approximation provided that the charge has a linear dependence on the channel potential. Validate the terminal currents as being the same as Ward's channel charge partition approximation. Validate that Ward's partition scheme is correct as long as the charge has a linear dependence on the channel potential. Derive the first order channel charge (qc1 ) and current (ic1) as a function of position (x) inside the channel. Derive the first order power dissipation and conserved components. Estimate energy function. Separate the terminal current into conserved and dissipative components. Identify the inconsistencies in the BSIM power model. In conclusion, there is a need to extend this work to include channel charge with a nonlinear voltage dependence that does not generate extra power dissipation in the channel that has no physical basis. 
Note  Dissertation 
Rights  © Oklahoma Agricultural and Mechanical Board of Regents 
Transcript  FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL By SAMEER SHARMA Bachelor of Science in Electrical Engineering Punjab Engineering College Chandigarh, India 1994 Master of Science in Electrical and Computer Engineering Oklahoma State University Stillwater, Oklahoma December, 2003 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY May, 2008 ~ii~ FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL Dissertation Approved: Dr. Louis G. Johnson Dissertation Adviser Dr. George Scheets Dr. James E. Stine, Jr. Dr. H. K. Dai Dr. Gordon Emslie Dean of the Graduate College ~iii~ TABLE OF CONTENTS CHAPTER PAGE I. INTRODUCTION .................................................................................................................................... 1 1.1 MODELING PROCESS ............................................................................................................ 1 1.2 SCOPE ....................................................................................................................................... 4 1.3 OUTLINE ................................................................................................................................... 5 II. LITERATURE REVIEW ........................................................................................................................ 7 2.1 MEYER’S MODEL ..................................................................................................................... 8 2.2 CHARGE BASED MODELS ................................................................................................... 11 2.3 TRANSCAPACITIVE MODEL .............................................................................................. 15 2.4 MEHMET MODEL ................................................................................................................... 15 III. FIRST ORDER QUASISTATIC CHANNEL CAPACITANCE MODEL .................................... 18 3.1 STEADY STATE OPERATION .............................................................................................. 18 3.2 QUASISTATIC OPERATION ................................................................................................ 19 3.3 MODELING EQUATIONS ...................................................................................................... 21 IV. MOSFET POWER............................................................................................................................... 27 4.1 SOURCES OF POWER DISSIPATION ................................................................................ 28 4.2 POWER AND ENERGY MODELING ISSUES .................................................................... 29 4.3 POWER MEASUREMENT TECHNIQUES .......................................................................... 30 4.4 POWER EQUATIONS ............................................................................................................ 35 4.5 ENERGY FUNCTION CALCULATION ................................................................................. 37 V. FIRST ORDER CURRENT COMPONENTS AND CAPACITANCE CALCULATION .............. 40 ~iv~ CHAPTER PAGE 5.1 FIRST ORDER CURRENT COMPONENTS ....................................................................... 40 5.2 CAPACITANCE DERIVATION .............................................................................................. 42 5.3 EQUIVALENT CIRCUIT ......................................................................................................... 47 VI. COMPARISON AND DISCUSSION .................................................................................................. 49 6.1 MODEL VERIFICATION AND ADVANTAGES .................................................................... 49 6.2 ENERGY PUMPING ............................................................................................................... 50 6.3 TOTAL FIRST ORDER POWER ........................................................................................... 52 6.4 SIMULATION EXAMPLE ........................................................................................................ 52 VII. DEPENDENCE OF THE BSIM ABULK PARAMETER ON THE SOURCE POTENTIAL .... 56 7.1 EVALUATION OF EXTRA CURRENT COMPONENTS .................................................... 57 7.2 SIMULATION EXAMPLE ........................................................................................................ 58 7.3 CONCLUSION ......................................................................................................................... 63 REFERENCES ........................................................................................................................................... 64 APPENDICES ............................................................................................................................................ 72 ~v~ LIST OF TABLES TABLE PAGE Table 3.1 NMOS Zero and First Order Charges and Currents………………….. 25 Table 4.1 Power Equations ………………………………………………………. 37 Table 4.2 Energy Function ………………………………………………………. 39 Table 5.1: Storage and Dissipative Current Components ……………………...... 42 Table 5.3: Total Capacitances…………………………………………………..… 44 Table 5.4: Conserved Capacitances………………………………………………. 45 Table 5.5: Dissipative Capacitances……………………………………………… 46 ~vi~ LIST OF FIGURES FIGURE PAGE Figure 1.1: Energy Imbalance ……………………………………………………. 3 Figure 2.1: Meyer Capacitance Model……………………………………………. 8 Figure 2.2: Channel Current Calculations………………………………………… 9 Figure 2.3: Current Representation in Meyer’s Model……………………………. 11 Figure 2.4: Channel Charge approximation using Ward’s Model………………… 12 Figure 2.5: Transcapacitance Approximation…………………………………… 15 Figure 2.6: Small Signal Representation of Mehmet’s Model……………………. 17 Figure 3.1: Bulk and SOI CMOS Structures…………………………………….... 18 Figure 3.2: Voltage, Charge and Current Waveforms…………………………...... 20 Figure 3.3: Four terminal MOSFET Structures…………………………………… 22 Figure 4.1: Leakage Current Components………………………………………… 28 Figure 4.2: Dynamic Power ………………………………………………………. 30 Figure 4.3: Transient Waveforms …………………………………………………. 31 Figure 4.4: Capacitor based Power Measurement Technique …………………… 34 Figure 4.5: Power Dissipation in MOS Transistor ……………………………….. 34 Figure 4.6: MOS Channel Power Calculation….. ……………………………….. 35 Figure 5.1: First order dissipative and conserved current components ……..……. 41 Figure 5.2: Total, Conserved and Dissipative Capacitances vs vds …….………… 44 Figure 5.3: Equivalent Circuit …………………………………………………… 47 ~vii~ FIGURE PAGE Figure 6.1: Terminal capacitances vs vds ………………………….…….……….. 50 Figure 6.2: Capacitance vs vds …………..………………………………………... 50 Figure 6.3: Gate pumping action……… ……………………………….………... 51 Figure 6.4: Average conserved gate and channel power vs frequency…………. 51 Figure 6.5: Idealized voltage waveforms ……………………………….………. 53 Figure 6.6: Total power vs. frequency……………………………………………. 54 Figure 6.7: Current plots………………………………………….………………. 55 Figure 6.8: Power plots…………….. …………………………………………..... 55 Figure 7.1: Terminal capacitances vs vds ……………………………….………. 59 Figure 7.2: Extra power dissipation …………..…………………………………. 60 Figure 7.3: Threshold voltage and bulk charge parameter……………….……. 61 Figure 7.4: Zero order currents………………………………..……………….…. 61 Figure 7.5: First order currents……… ……………………………….………….. 62 ~viii~ LIST OF SYMBOLS SYMBOLS NAMES qc …………………………………………….. channel charge per unit length qc0 …………………………………………….. zero order channel charge per unit length qc1 …………………………………………….. first order channel charge per unit length qs …………………………………………….. source charge per unit length qd …………………………………………….. drain charge per unit length qg ……………………………………………. gate charge per unit length L ……………………………………………. channel length W ……………………………………………. channel width cox ……………………………………………. oxide capacitance per unit length v fb ……………………………………………. flat band voltage vt0 ……………………………………………. threshold voltage at zero source bias vt ……………………………………………. threshold voltage φ ……………………………………………. fermi potential tox ……………………………………………. oxide thickness vcb ……………………………………………. channel terminal voltage vgb ……………………………………………. gate terminal voltage vsb ……………………………………………. source terminal voltage ~ix~ SYMBOLS NAMES vdb ……………………………………………. drain terminal voltage 1 k ……………………………………………. body effect coefficient 2 k ……………………………………………. body effect coefficient Ic0 ……………………………………………. zero order (static) current ID ……………………………………………. static drain current IS ……………………………………………. static source current IG ……………………………………………. static gate current IB ……………………………………………. static substrate current I (t) ……………………………………………. total channel current id1 ……………………………………………. first order drain current is1 ……………………………………………. first order source current ig1 ……………………………………………. first order gate current ib1 ……………………………………………. first order substrate current id1,cons……………………………………………. first order conserved drain current is1,cons ……………………………………………. first order conserved source current id1,diss ……………………………………………. first order dissipative drain current is1,diss……………………………………………. first order dissipative source current Pc0 ……………………………………………. average power P ……………………………………………. total instantaneous power Pc ……………………………………………. instantaneous channel power Pc0 ……………………………………………. static power ~x~ SYMBOLS NAMES Pc1,diss……………………………………………. first order dissipative channel power Pc1,cons……………………………………………. first order conserved channel power Pg1,cons……………………………………………. first order gate power CL ……………………………………………. externally load capacitor Cgb ……………………………………………. gate to bulk capacitance Cgs ……………………………………………. gate to source capacitance Cgd ……………………………………………. gate to drain capacitance Csb ……………………………………………. source to bulk capacitance Csg ……………………………………………. source to gate capacitance Csd ……………………………………………. source to drain capacitance Cdb ……………………………………………. drain to bulk capacitance Cdg ……………………………………………. drain to gate capacitance Cds ……………………………………………. drain to drain capacitance Ccsb ……………………………………………. conserved source to bulk capacitance Ccsg ……………………………………………. conserved source to gate capacitance Ccsd ……………………………………………. conserved source to drain capacitance Ccdb ……………………………………………. conserved drain to bulk capacitance Ccdg ……………………………………………. conserved drain to gate capacitance Ccds ……………………………………………. conserved drain to drain capacitance Cdsb ……………………………………………. dissipative source to bulk capacitance ~xi~ SYMBOLS NAMES Cdsg ……………………………………………. dissipative source to gate capacitance Cdsd ……………………………………………. dissipative source to drain capacitance Cddb ……………………………………………. dissipative drain to bulk capacitance Cddg ……………………………………………. dissipative drain to gate capacitance Cdds ……………………………………………. dissipative drain to drain capacitance Pc1, diss, B…………………………………………. BSIM first order dissipative channel power Pc1, cons, B …………………………………………. BSIM first order conserved channel power Pg1, cons, B…………………………………………. BSIM first order gate power Pg1,cons Extra ……………………………………….. extra first order channel conserved power Pc1,diss Extra ……………………………………….. extra first order channel dissipative power P1,cons Extra ………………………………………. extra first order conserved power ~xii~ ACKNOWLEDGMENTS I would like to express sincere thanks to my advisor Dr. Louis G. Johnson for his guidance, encouragement and the research opportunity. I would also like to extend appreciation to my committee members Dr. George Scheets, Dr. Yumin Zhang, Dr. James E. Stine Jr. and Dr. H. K. Dai for their invaluable knowledge and guidance. Additional thanks go to all my colleagues in VLSI Design Group for helpful discussions on circuit simulation, device modeling and power estimation. Finally, I would like to acknowledge the support from my wife Srijana and two daughters Vidhi and Tanya for their patience and encouragement throughout my studies. ~1~ CHAPTER I I. INTRODUCTION 1.1 MODELING PROCESS Modeling is a process of accurately representing the behavior of a device to be used in a circuit simulator. Designers need these reliable and accurate models for circuit development. With the growth of CMOS technology, MOSFET modeling has taken a centre stage and the accurate modeling of MOS transistor channel capacitance has been an ongoing effort. First, Meyer’s [1.1] reciprocal gatecapacitive model, then Ward’s [1.2] chargebased, nonreciprocal capacitance model have been used. Many papers have also been written on the comparison of these models. Some [1.31.6] claim that Meyer’s model fails due to charge nonconservation which justifies the usage of chargebased models while others claim [1.71.9] that the charge nonconservation is mainly due to the faulty mathematical modeling of the simulation software. As pointed out by Fossum [1.10], it is not clear whether we have explored all other possibilities. We may be able to achieve a better result with a different channel partition or may be with no partition at all. Recent papers on fielddependent mobility [1.33] and laterally asymmetrical doping [1.34] have now shown inconsistencies in Ward’s model, which artificially partitions the channel charge into the source and the drain components. Many ideas have also been suggested for estimation of energy and power taking into consideration the input slew dependency [1.11], propagation delay [1.12], short circuit power [1.13] and supply current measurements [1.141.16]. One of the most popular and widely adapted, Berkeley ShortChannel IGFET (BSIM) Capacitive Model [1.17, 1.18] has tried to include many of the above mentioned modeling techniques to estimate the behavior of Insulated Gate Field Effect Transistors (IGFET). However, the BSIM ~2~ capacitive model fails to include the first order transcapacitive currents due to the charge redistribution in the channel that causes the actual output waveform and the delay to deviate from the BSIM stimulation results [1.19]. In reality, the MOS device is a highly nonlinear four terminal device and modeling it as a simple energy storage device leaves a lot to be desired. When the inversion layer is formed, the IR drop from the resistive components and charge redistribution current causes power dissipation in the channel. This makes the assumption that the capacitive model does not contribute any net power dissipation in the channel inconsistent for use in energy prediction. If the BSIM model is not consistent, one may ask as why it is still being used? The reason is: the BSIM quasistatic models are analog friendly, continuous and have good IV characteristic. These IV models are derived from the channel charge that is calculated correctly to the first order. Power is also derived from the channel charge. The problem, however, is that the power is derived only to zero order. In other words, the BSIM capacitive model calculates static power dissipation, which is nothing but the multiplication of zero order current and steady state voltage. Though the BSIM capacitive model includes first order corrections in dynamic power calculation, it leaves out some important terms. We can think the process of dynamic power calculation of the BSIM model as being nothing but an easy way of calculating the zero order power by using the change in the energy of the capacitors during charging and discharging. The BSIM capacitive model assumes that the first order terms are the energy storage terms (like capacitors and inductors) that do not dissipate energy, which in reality is not the case. Hence it is not appropriate to look at the change in the energy of the capacitors in the channel as there is no energy function for the channel. It causes an error and gives a different number for power from the supply power than the dissipated power from all the devices, clearly a violation of energy conservation principles. This effect is pointed out in Fig. 1.1 which is a plot of switching frequency and the energy imbalance for different width ratios of transistors in a inverter. As seen, for higher switching frequencies (small rise/fall times) the energy imbalance is more pronounced. ~3~ In reality, it is very difficult to estimate the usefulness of SPICE simulation in the power estimation of a real circuit. In digital applications, it is well known that the glitches can contribute half the power, and how accurately we can predict the power spike depends on how accurately we can predict the glitches. Therefore, it did not make a whole lot of difference, as SPICE was not predicting the power accurately anyway. Even if it were able to predict the power, it is not possible to extrapolate to a real circuit with glitches that are not exactly the same as SPICE calculated. However, in the world of Pentiums [1.20], Core Duos [1.21] and QuantiSpeed Architecture processors [1.22], where the gates are switching around 300 billion times a second [1.23], it becomes essential to calculate the higher order transients to accurately predict the device power and switching dynamics. Figure 1.1: Energy Imbalance It should also be pointed out that scholars working in the MOS devicemodeling are aware of the transport current components flowing in the channel. Many papers [1.24 1.27] and chapters [1.281.30] have been written about the charging and transport current components. However, all of them assume that it is not possible to separate the dissipative and energy storage components and have come up with many theories and models to envision the transient effects. One of the models by LimFossum [1.31, 1.32] has the first order transient transcapacitive current and 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0.10 1.00 10.00 100.00 1000.00 % Error Rise/Fall time in psec Error (10 Wp) Error (4Wp) Error (2Wp) Error( Wp/2) Error (Wp) ~4~ suggests the difference between nonreciprocal capacitive elements to be responsible for these transport currents. This however has some drawbacks. First, if these were the total transcapacitive currents, its product with the drain to source voltage should have been the total dissipative power, which is not the case. Second, LimFossum used Ward’s charge partition model to find the source and drain charge components, which makes their model dependent on the accuracy of the charge partition. 1.2 SCOPE The object of the research is to realize the inconsistency in the current MOSFET modeling and develop efficient models for accurate intrinsic capacitance and power dissipation estimation. An ideal model would be to consider all non linear effects and solve a complete nonlinear differential equation for the channel in three dimensions. In that case, we see a packet of charge traveling down the channel as a function of time. Although such models are valuable, from the simulation perspective, the process is ineffective as the simulation times are very long. To be computationally efficient, we need compact models that describe the electrical behavior analytically and are able to represent the nonlinear channel in a reasonable time without sacrificing modeling accuracy. Furthermore, the fast scaling of frequency for semiconductor integrated circuits that was seen in the last few decades has been saturating. One of the reasons is the increase in power dissipation. Power limits the scaling. The high power dissipation due to small device geometry has thrown off course the roadmap of future development of semiconductor technologies. When the devices are switching rapidly, the power dissipation per unit area goes up causing excessive heating. Unless a sophisticated cooling system is implemented, the device may no longer be operational. The reality is: we have reached a power limited scaling regime. Scaling now is no longer determined by the device size, but by how much power the chip can dissipate at a particular working frequency. However, the lack of suitable device models to measure this power dissipation has provided a plethora of research avenues. The conventional MOSFET models have some inherent issues and are not consistent for power and energy prediction as they: ~5~ • Fail to include the first order power dissipation due to channel charge redistribution • Give a net nonzero power in the channel that has no physical basis from the terms that should be conserved This makes the MOSFET modeling very important going forward into the nanometer regime. Given that the accuracy of the simulation depends on the physical representation of the device, it is very important that we have a reliable mathematical model that is able to represent the device behavior. Designers need these accurate models for circuit development. 1.3 OUTLINE The outline of the dissertation is as follows: Chapter 2 describes the conventional MOSFET models used in transient analysis and computer simulation. The analysis of these models gives a general overview and a good background on device modeling. Some of these models are still being used for device simulation. The Meyer’s model, Ward’s charge partition model, Mehmet model and Transcapacitance models and its effectiveness are considered. Some of the advantages and the shortcomings are also discussed. Chapter 3 describes a one dimensional MOSFET current model with current continuity equations. These equations have been used to compute the channel currents and channel charges as well as currents at the source and the drain terminals for a charge conserving, quasistatic, channel capacitance model. The calculation of channel currents without charge partition allows the computation of the instantaneous channel power, which further helps in separating the dissipating and energy conserving current components. Chapter 4 describes the details of power estimation. Zero and the first order instantaneous power is computed by integrating the power density over the entire channel. This leads to the derivation of closedform analytical expressions for the conserved and dissipative current components from the first order drain and source currents. The energy function calculations from the first order ~6~ conserved power components are also shown. Chapter 5 describes the derivation of capacitances from the first order drain (id1) and source (is1) current components. These capacitances are then separated into conserved and dissipative components. An improved equivalent circuit is also developed by following the method used by LimFossum. The results are verified using the BSIM Capacitive and LimFossum fully depleted SOI models for currents and charges in chapter 6. Even though these models used a charge partition instead of solving exactly as we have, all models predict the same source and drain currents, and hence the same terminal capacitances. However, we are able to separate out these capacitances into conserved and dissipative components. Chapter 7 describes the inconsistencies of the BSIM capacitive model for energy and power prediction. We have shown that the dependence of the BSIM bulk charge parameter on the source potential causes extra power dissipation in the channel that has no physical basis. This leads to an inconsistent power model where energy supplied from the gate does not balance out with the energy generated at the channel. ~7~ CHAPTER II II. LITERATURE REVIEW This chapter describes some of the MOS models that have been used in circuit simulators to analyze the transient response. Historically, MOS devices have been modeled with capacitor and over the last few decades, many such capacitive models have been proposed to effectively represent the charges at the four terminals of a FET device. The problem however is the difficulty in representing the terminal charges by a single model. This is because; MOS transistors not only conduct current in a steady state but also conduct when the terminal voltages are varying. The time dependence of currents and voltages of a MOSFET makes representation using steady state (DC) conditions insufficient. A solution is possible by superimposing zero order steady state DC (IV) representation over a capacitance (CV) model to characterize the transients as ( ) 0( ) 1( , ) I t I v i v dv c c dt = + where 0( ) c I v is the steady state (DC) current and depends only on the instantaneous terminal voltages. ic1(t) is the transient transport component and is zero under steady state conditions. For simulation purposes, the capacitance (CV) model is developed by expanding the transient current as 1( ) i t dq c dv c dt dt = = In the subsequent sections, some of these models have been discussed in chronological order of the history of device modeling. ~8~ 2.1 MEYER’S MODEL In 1971, Meyer [2.1] proposed the first large signal model for MOS transistors in terms of physical device parameters. Figure 2.1: Meyer Capacitance Model The model represents the charge storing property of MOS transistors using three nonlinear voltage dependent capacitors, as shown in Fig. [2.1]. These capacitors are defined in terms of the total gate charge Qg. Meyer’s model is a simple charge conservation model as it restricts the sum of the gate charge Qg and channel charges Qc o be zero, and is based on the following five assumptions. • The total gate charge Qg is a function of the terminal voltage under steady state conditions. • The gate capacitances are found as: Q C g gs vgs ∂ = ∂ Qg Cgd vgd ∂ = ∂ Qg Cgb vgb ∂ = ∂ (2.1) Cgg Cgs Cgd Cgb = + + Where vgs, vgd and vgb are the gate to source, gate to drain and gate to bulk voltages. • The drain to bulk, source to bulk and drain to source capacitances are assumed to be zero. Cds Cdb Csb 0 = = = Csd Cbd Cbs 0 = = = ~9~ • It is assumed that the capacitance matrix is symmetrical, which is necessary to conserve energy. Cgd Cdg = Cgs Csg = Cgb Cbg = • The total source, drain and bulk capacitances are calculated as: Cdd Cds Cdg Cdb = + + Css Csg Csd Csb = + + Cbb Cbs Cbd Cbg = + + These five assumptions give the capacitance matrix as shown below; 0 0 0 0 0 0 Cgd Cgs Cgb Cgd Cgs Cgb Cgd Cgd Cgs Cgs Cgb Cgb ⎡ + + − − − ⎤ ⎢ ⎥ ⎢ − ⎥ ⎢ ⎥ ⎢ − ⎥ ⎢ ⎥ ⎢ − ⎥ ⎢⎣ ⎥⎦ To calculate the total gate charge (Qg ), a gradual channel approximation is used. The charge per unit area at any position x along the channel is given in by Q(x) Cox (Vgb Vt V (x)) = − − Figure 2.2: Channel Current Calculation where Vgb is the gate voltage, Vt is the threshold voltage, V(x) is the potential at position x along the channel, and Cox is the gate oxide capacitance per unit area . The steady state drain current ~10~ Ic0 is found using ( ) ( ) 0 I WQ x dV x c dx = μ where W is the channel width and μ is the mobility. Integrating from source (x=0) to drain (x=L); ( 2 2) 0 2 I C W V V c ox L gs gd = μ − (2.2) where L is the channel length. Gate charge is given by ( )3 ( )3 2 3 ( )2 ( )2 ( )2 ( )2 Vgd Vt Vgs Vt Qg WLCox Vgd Vt Vgs Vt Vgd Vt Vgs Vt ⎡ − − ⎤ ⎢ ⎥ = ⎢ − ⎥ ⎢ − − − − − − ⎥ ⎣ ⎦ (2.3) Using (2.1) and (2.2), capacitances are calculated as ( )2 2 1 3 ( )2 Vgd Vt Cgs WLCox Vgs Vt Vgd Vt ⎡ − ⎤ ⎢ ⎥ = ⎢ − ⎥ ⎢ − + − ⎥ ⎣ ⎦ (2.4) ( )2 2 1 3 ( )2 Vgs Vt Cgd WLCox Vgs Vt Vgd Vt ⎡ − ⎤ ⎢ ⎥ = ⎢ − ⎥ ⎢ − + − ⎥ ⎣ ⎦ (2.5) Cgb 0 = Finally, current through each capacitor is computed as dVgs Igs Cgs dt = dVgd Igd Cgd dt = dVgb Igb Cgb dt = Fig. 2.4 shows the current representation of Meyer’s model. Currents I1 and I2 in the channel are assumed to be bidirectional, one being dependent on gatetosource and other being dependent on gatetodrain. This is also known as “Twocurrentsource MOS model”. ~11~ Figure 2.3: Current Representation in Meyer's model The major drawback of Meyer’s model is the exclusion of the source to bulk and drain to bulk capacitances resulting from substrate charges. 2.2 CHARGE BASED MODELS Ward [2.22.4] claimed that Meyer’s model failed the charge conservation test for circuits that required charge storage. They identified the presence of nonlinear reciprocal capacitances and exclusion of the source to bulk and drain to bulk capacitances as being the source of charge nonconservation in the circuit simulation. They based their findings using current equation ( ) ( ) dV i t C v gs dt = (2.6) Here the capacitance term is dependent on the terminal voltages of the source, drain and the gate and has been evaluated at some appropriate voltage i.e. C(v) is not defined as a time dependent variable and can follow any path and as a result may lead to some arbitrary charge value. The best possible solution with average value of capacitor taken at two time intervals may also lead to an incomplete charge prediction. Integrating from the present time point t0 to the next time point t1, equation (2.6) can be written as 1 ( 1) ( ) ( ) ( ) 0 0 t vt ∫t i t dt = ∫v t C v dv (2.7) If C(v) is considered a constant, equation (2.7) reduces to 1 ( ) ( )[ ( ) ( )] 0 1 0 t ∫t i t dt = C v V t −V t (2.8) ~12~ The capacitance value forC(v) that’s been used here is computed at time t0. Ward assumes this being the reason for charge pumping, as there may be some residual charge at time t0. He suggests that even if the capacitive values are calculated at time t1 or smaller time steps, it will not guarantee charge conservation. To overcome the assumed charge neutrality limitations, he suggested the chargepartition model [2.2]. The chargepartition model is based on the fixed charge distribution in the MOSFET terminals. The model tries to split the total channel charge Qc into source (Qs) and drain (Qd) charges rather than splitting the total distributed capacitance into reciprocal gatetosource and gatetodrain capacitances. The current is then computed as the derivative of charge as dt i(t) = dQ(t) Using similar integration approach as equation (2.7) 1 ( ) ( ) ( ) 0 1 0 t ∫t i t dt = Q t −Q t (2.9) Though Q(t0) and Q(t1) are complex functions of time, it can be obtained at any time by terminal voltage at that instant. Figure 2.4: Channel Charge Approximation using Ward's model The emphasis of the charge model was the use of charge as a state variable for the computation of charge at the MOSFET terminals. Ward was also able to put in perspective a current continuity equation I ( y,t) W Q( y,t) y t ∂ ∂ = − ∂ ∂ with the boundary conditions on V(y) as V (0) Vs = and ( ) V L Vd = ~13~ to calculate the source and drain charges together with the source and drain currents, and the transport current. Using the current continuity equation, the current at any point y on the channel is evaluated as ( , ) ( ) ( , ) 0 y Q y t I y t Is t W dy t ∂ − =−∫ ∂ (2.10) where Is (t) I (0,t) = is the source current, and L is the length of the channel. Considering only drift current for I ( y,t) and solving for Is (t) , equation (2.10) reduces to two current components I ( y,t) WQ( y,t) V ( y,t) y μ ∂ = − ∂ and (2.11) ( ) ( , ) ( , ) ( , ) (1 ) ( , ) 0 0 W L V y t d L y Is t y t Q y t dy W Q y t dy L y dt L μ ∂ ⎡ ⎤ = − ∫ + ⎢ ∫ − ⎥ ∂ ⎢⎣ ⎥⎦ (2.12) Substituting y=L to obtain the drain current ( ) ( , ) ( , ) ( , ) ( ) ( , ) 0 0 W L V y t d L y Id t y t Q y t dy W Q y t dy L y dt L μ ∂ ⎡ ⎤ = − ∫ + ⎢ ∫ ⎥ ∂ ⎢⎣ ⎥⎦ (2.13) Since the drain and source current can be assumed to have transport and charge components, they can be represent using ( ) ( ) ( ) dQs t Is t IT t dt = − + (2.14) ( ) ( ) ( ) dQd t Id t IT t dt = + (2.15) From equations (2.13) (2.14) and (2.15), (1 ) 0 L y Qs W Qdy L = ∫ − (2.16) ( ) 0 L y Qd W Qdy L = ∫ (2.17) Many modifications have been made since Ward proposed the original charge model in 1981. Almost all these models consider “charge” as a state variable and use nonreciprocal capacitors. Some models have partitioned the channel charge into drain and source components in the ratio ~14~ of 40/60 while others use a 50/50 model. However, none of these models addresses the actual cause of charge nonconservation. Yang, Berton and Chatterjee [2.5], while investigating the charge conservation problem, observed that the nonconservation of charge in circuit simulator SPICE is due to the integration problem independent of device physics. They think the error is due to the choice of voltage as a state variable for simulation, and also due to the nonlinearities in the MOS capacitances and its dependence on four different terminal voltages. Sakallah, Yen and Greenberg [2.6] also support the view that the charge nonconservation in the Meyer capacitance model has nothing to do with the device physics or a faulty capacitive model, “rather by the mathematical error of characterizing a multidimensional function by an incomplete subset of its partial derivatives.” They conclude that the charge nonconservation can be eliminated if circuit simulators are given non trivial models. They also followed modeling using Ward’s approach and proceeded by splitting total channel charge into source and drain instead of splitting total distributed capacitance between the gate and the channel into reciprocal gatetosource and gatetodrain capacitances. As mentioned earlier, the charge splitting techniques have been revised many a time, and have been classified into two groups with respect to the bulk charges included in the model [2.7] for efficient MOSFET modeling. They are I. Depletion Charge Model (DSM) II. Simplified Charge Model (SCM) In DCM, bulk charge is considered to be proportional to the square root of a voltage, while SCM is a more simplified DCM model, with slight compromise in bulk to drain and bulk to source capacitances. Although chargebased models provided an alternate way to model MOSFET’s, it was still not able to explain the charge nonconservation of the Meyer capacitance model. Roots and Hughes [2.8] in 1988 and Snider [2.9] in 1995 suggested a transcapacitance model, which came close in identifying the conservation problem. ~15~ 2.3 TRANSCAPACITIVE MODEL Roots and Hughes [2.8] in 1988 and later Snider [2.9] was able to explain the charge nonconservation of the Meyer capacitance model using the concept of transcapacitance. According to them, a capacitive gate to source MOS elements that depends on both gate to source and gate to drain voltages would transport a nonzero charge. They predicted the violation of charge conservation due to the omission of recharging effect of capacitances and tried to compensate the charge by adding an extra element in the circuit and called it a transcapacitance element. Their model concluded that: 1. Current equation dt I = C dV alone does not account for all the currents in MOS transistors as capacitances are controlled by more than one source. 2. These capacitances appear to dissipate energy if transcapacitance terms are ignored. Figure 2.5: Transcapacitance Approximation 2.4 MEHMET MODEL In 1989, Mehmet A. Cirit [2.10] was able to show the root cause of charge nonconservation in the gatecapacitance model proposed by Meyer. He points out that the “Meyer model is a firstorder inaccurate approximation to MOS capacitances.” Since the MOS capacitance is dependent on several variables, faults in the modeling of such an element causes the SPICE simulator to neglect nonlinear first order capacitive terms. Considering the gate to source transient current equation igs Cgs tvgs = ∂ ~16~ its partial derivative gives i C Vgs C Vgs gs gs gs δ δ • • = + . (2.20) Since gate capacitance is dependent on gate to source, gate to drain and gate to bulk voltages, including these effects, equation (2.20) can be modified as Cgs Cgs Cgs i C Vgs Vgs V Vgs Vgd Vgs V gs gs V gs V V gb gs gd gb δ δ δ δ δ δ δ δ δ δ δ • • • • = + + + (2.21) If α is 1/h, where h is the time interval, and voltage varies by an amount δV, the corresponding change in its time derivative V • can be estimated asδ V =αδV • . Substituting these values in equation (2.21), equation (2.21) can be rewritten as Cgs Cgs Cgs i C V Vgs V Vgs Vgd Vgs V gs gs Vgs gs Vgd Vgb gb δ δ δ δ αδ δ δ δ δ δ δ • • • = + + + (2.22) Similarly, gate to drain and gate to substrate current can be written as Cgd Cgd Cgd i C V Vgd V Vgd Vgd Vgd V gd gd V gs V V gb gs gd gb δ δ δ δ αδ δ δ δ δ δ δ • • • = + + + (2.23) Cgb Cgb Cgb i C V Vgb V Vgb Vgd Vgb V gb gb V gs V V gb gs gd gb δ δ δ δ αδ δ δ δ δ δ δ • • • = + + + (2.24) The first term in (2.222.24) is frequency dependent, while rests of the terms are due to nonlinear capacitances and look like resistors in the channel. As circuit simulators only considered the frequency dependent terms for circuit evaluation, Mehmet assumed that this incomplete representation was the root cause of charge pumping in circuit simulators, and proposed a model to include ignored nonlinear terms that caused an extra charge in the channel. ~17~ Figure 2.6: Small Signal Representation of Mehmet Model Fig. 7 shows a small signal representation of Mehmet model for Cgs where C C gs gsgs Vgs δ δ = Cgs Cgsgd Vgd δ δ = Cgs Cgsgb Vgb δ δ = (2.25) Cgd Cgdgs Vgs δ δ = Cgd Cgdgd Vgd δ δ = Cgd Cgdgb Vgb δ δ = (2.26) Cgb Cgbgs Vgs δ δ = Cgb Cgbgd Vgd δ δ = Cgb Cgbgb Vgb δ δ = (2.27) Mehmet used this model in the circuit simulator Lspice and observed the charge conservation. He concluded that the Meyer gate capacitance model can be made to conserve charge by considering all first order terms. He also pointed out that the substrate charges might be easily included in the Meyer capacitance model to simulate the MOS devices more accurately. It should be noted that in any MOSFET model, charge or capacitance, the charge neutrality condition is built into the derivation [2.11] and may seem unreasonable to come up with a charge nonconservation problem. Whichever modeling techniques are used, the main goal is to come up with an analytical description of MOS device behavior with emphasis on equations that are continuous in all regions of device operation. ~18~ CHAPTER III III. FIRST ORDER QUASISTATIC CHANNEL CAPACITANCE MODEL This chapter describes the mathematical equations used to analyze the MOS transistor for the research work. The current continuity equations are presented without the channel charge partition to compute the steady state and dynamic current components. These currents then become the basis for IV and CV models to be used in the circuit simulators. 3.1 STEADY STATE OPERATION In the steady state, the gate and substrate are assumed to have no direct conductive path to the channel. Leakage through the gate oxide as well as recombination current between the substrate and the channel are neglected. Figure 3.1: BULK and SOI CMOS Structures It is very important that the body charges are properly modeled [3.1, 3.2, 3.3] and its effects are included for steady state and the transient simulations. These effects cause an uneven distribution of channel charge between the source and the drain regions, and the regions in between, which in turn causes uneven distribution of the gate and substrate charges. To model all these skewed distributions, it will be convenient to describe the charges by its density per unit length. Considering only the intrinsic part of the MOS transistor, which is responsible for all the transistor action, the zero order charge per unit length at the terminals can be written as ~19~ q jb0 f (vgb, vcb ) where j g, c = = (3.1) In terms of drift current, current flow in the device can be seen due to the transport of electrons from the source to the drain terminal. Taking steady state values, Ic0 ID = (3.2) IS ID = − (3.3) IG 0 = (3.4) IB 0 = (3.5) where Ic0 is the steady state channel current, which becomes ID at the drain end and –IS at the source end. The steady state gate IG and substrate currents IB are zero as the transistors are assumed to be leakage free. These terminal currents can be expressed as some function of terminal voltages and can be written as Ic0 f (vD, vG, vS ,vB) = (3.6) 3.2 QUASISTATIC OPERATION Equation (3.4) was calculated with the assumption that the terminal voltages were steady. In a real circuit, transistors operate under dynamic conditions where terminal voltages are varying. To calculate the charge under such conditions, quasistatic operations are assumed. The voltages are allowed to vary slowly in quasistatic operation. Though the gate, substrate and the channel charges are still the functions of instantaneous voltages and can be represented using equation (3.1), however, the currents can not be predicted using equation (3.6). With similar assumption of leakage free gate oxide and negligible recombination current, the first order gate (ig1) and substrate (ib1) currents are no longer zero. They are given at any location x along the channel by the gate (qg) and bulk (qb) charge densities as: ig (x,t) d qg (x,t) dt = (3.7) ~20~ ib (x,t) d qb (x,t) dt = (3.8) In the quasistatic operation, even though the charge distribution in the channel remains the same, there exists a conducting path between the source and the drain terminals. Charge enters from the source terminal and leaves the drain terminal, which makes channel partition schemes misleading to understand the device physics. It is also challenging to represent the channel charge and compute the first order source (is1) and drain (id1) terminal currents due to two reasons: • It is unrealistic to consider the charges in the channel as being partitioned between source and drain and • Charge redistribution causes extra dissipation in the channel. The unrealistic partition can be resolved by solving for the total charge in the channel instead of separating it into source and drain charges. Fig. 3.2 shows a voltage, charge magnitude and current waveforms. The current waveforms show a pair of first order components together with a steady state DC component. The origin of these first order components not predicted by DC operation can be explained using a test quasistatic voltage at the gate terminal. Figure 3.2: Voltage, Charge and Current Waveforms ~21~ A rising input at the gate terminal from time t0 to t1 causes the first order currents. Compared to first order drain current (id1), first order source current (is1) is more in this interval as more electrons are pumped from the source terminal and fewer electrons are removed from the drain. Between the intervals t1 to t2, current settles into a steady state value of Ic0. On the other hand, for a falling waveform between the interval t2 to t3, first order drain current becomes more than the first order source current as more electrons are sucked out from the drain terminal. These transients that show up during the switching are also responsible for the channel charge redistribution, which in turn also contributes to power dissipation. To properly analyze the MOS transistors and develop CV models to be used in circuit simulators, we then need to consider these first order currents together with the steady state values. As mentioned above, the charge redistribution also contributes to the power dissipation, which suggests the presence of first order dissipative and conserved components. We have been able to identify and separate out these components. This is explained in detail in chapter 4 with derivations. 3.3 MODELING EQUATIONS In order to obtain an analytical solution, the current flow is considered in one dimension parallel to the surface of the device. The equations for both Bulk and SOI processes are developed with some assumptions. The body charge is assumed to have square root dependence for the Bulk process, while the charge expressions for SOI MOSFET assumes that the region under the channel is completely depleted of mobile charges. These simplified assumptions helps us to make use of a linear relationship between the body and the surface potential to compute the energy function without partitioning the channel charge. The linear bodysurface relation also provides a simplified charge model and terminal currents. It should be noted that solving the model involves complicated algebraic calculations that are practically impossible without modern mathematics tools like “Mathematica” [3.4]. ~22~ Fig. 3.3 shows NMOS BULK and SOI transistors. The charge per unit length ( qc ) at a position x along the channel is given by qc (x) cox (vgb v fb vcb(x) qb(x) / cox ) = − − − −φ + (3.9) Similarly, the bulk charge (back gate) per unit length ( qb ) at x can be written as ( 1 2 ( )), ( ) ( 1 ( 1) ( ( ) )), cox k k vcb x SOI qb x cox k vsb Abulk vcb x vsb BULK φ − + ⎧⎪ = ⎨ − + + − − ⎪⎩ (3.10) where v fb , vgb and vcb are flat band, gate and channel voltages with respect to the body. Abulk [3.13] is the bulk charge coefficient, 1 k and 2 k are body effect coefficients. cox w (cox / A) = is the oxide capacitance per unit length and w is the channel width. The bulk charge is approximated using first two terms of Taylor’s expansion around the source terminal vsb . The linear dependence of back gate for a fully depleted SOI MOSFET is included in the k1 term. Charge conservation is insured by defining the gate charge per unit length g q as qg (qb qc ) = − + (3.11) It will be convenient to define the channel charge per unit length at the source (x=0) qs and the drain (x=L) qd and their time derivatives as qs cox vgst = − and (3.12) Figure 3.3: Four terminal (a) BULK NMOSFET and (b) SOI NMOSFET Structure ~23~ d q c d v dt s ox dt gst = − (3.13) where vgst vgb vt vsb = − − (3.14) In equation (3.14), vt is the threshold voltage. The body effect parameters are included by considering the dependence of source terminal on the threshold voltage [3.5, 3.6] by defining 0 2 , ( ) 0 1( ), vt k vsb SOI vt vsb vt k vsb BULK φ φ + ⎧⎪ = ⎨ + + − ⎪⎩ (3.15) where 1 , 0 , 1 v fb k SOI vt v k BULK fb φ φ φ + + ⎧⎪ = ⎨ + + ⎪⎩ (3.16) At the drain end, qd coxvgdt = − and (3.17) d q c d v dt d ox dt gdt = − where (3.18) (1 2) ( ), ( ) ( ), vgb vt vsb k vdb vsb SOI vgdt x vgb vt vsb Abulk vdb vsb BULK − − − + − ⎧⎪ = ⎨ − − − − ⎪⎩ (3.19) It is assumed that positive current flows into the drain and velocity saturation effects are neglected. The derivative of Abulk with vsb is assumed to be negligible. These assumptions are necessary for energy conservation [3.7] and simplified capacitance equations [3.8]. Even though the equations are simplified, accuracy is not significantly compromised [3.8]. The results are expected to be accurate for a substrate referenced system [3.9]. Drift current at a distance x along the channel can be written as ic (x,t) qc (x,t) d vcb (x) dx = μ (3.20) Charge conservation is assured using the continuity equation d ic (x,t) d qc (x,t) dx dt = − (3.21) ~24~ where qc qc0 qc1 = + In equation (3.21), qc0 is a function of terminal voltages and qc1 is a function of first order time derivatives of terminal voltages. Using (3.20) in (3.21) gives d [qc (x,t) d vcb (x)] d qc (x,t) dx dx dt μ = − (3.22) Taking the spatial derivatives of charge per unit length as a function of potential along the channel, equation (3.9) and (3.10) reduces to (1 2), ( , ) ( ); ; , d d k SOI qc x t Cc vcb x Cc coxK K dx dx Abulk BULK + ⎧⎪ = = =⎨⎪⎩ (3.23) Substituting d vcb (x) dx in (3.22) and rearranging terms gives [ ( , ) ( , )] ( , ) d d Cc d qc x t qc x t qc x t dx dx μ dt = − (3.24) Equation (3.24) can be solved iteratively to compute the current and the charge in the channel. In terms of the steady state (zero order) charge per unit length at any position x along the channel, equation (3.24) reduces to ( 0 0) 0 d q d q dx c dx c = (3.25) Performing integration from source(x=0) to drain (x=L), zero order charge along the channel becomes ( 2(1 / ) 2 / qc0 qs x L qd x L = − − + (3.26) and the steady state drift current component simplifies to 0 0 0 I q d q C c dx c c μ = (3.27) Equation (3.27) gives the usual equation for static current neglecting velocity saturation, which is shown in Table 1. The first order current and charge can be found by keeping terms of first order in time derivatives in equation (3.24) ~25~ ( 0 1 1 0 ) 0 d d d Cc d qc qc qc qc qc dx dx dx μ dt + =− (3.28) Rearranging the terms, equation for the first order channel charge simplifies to 1 ( ( [ ] ) ) 1 0 1 0 0 Cc d qc qc x dx dx c x c qc dt μ = − ∫ ∫ + + (3.29) and the first order channel current reduces to 1 ( 0 1 1 0) i q d q q d q c C c dx c c dx c c μ = + (3.30) Finally, equation (3.30) can be solved to compute the first order channel current at the source is1 = ic1 (x=0) and the drain id1 = is1 (x=L) ends in all regions of operation. We have assumed pinchoff saturation which occurs when qd 0 = . The drain voltage at saturation can now be estimated by setting vgdt (x) 0 = to get vgst vds K ≥ as a boundary between the linear and the saturation regions. In the cutoff, it is assumed that the channel current is zero, which is made possible by setting both the charge densities d q and s q to zero. Table 1 summarizes the charge and current in all regions of operations. These results obtained without partitioning the channel charge are in agreement with LimFossum [3.10] and the BSIM capacitive model [3.11, 3.12] which were obtained using Ward’s [3.2] partition. Therefore, we have verified that Ward’s partition is correct when the voltage dependence of Abulk is ignored. Table 3.1: NMOS Zero and First Order Charges and Currents Linear Saturation CutOff Conditions 0 0 0 qc vgdt vgst < > > 0 0 0 qc vgdt vgst < = > 0 0 0 qc vgdt vgst = = = qs coxvgst − c v ox gst − 0 qd coxvgdt − 0 0 ~26~ Ic0 2 2 2 ( ) 2 (1 ) gst gdt cox v v L k μ − + 2 2 2 (1 ) gst cox v L k μ + 0 is1 2 2 3 2 2 2 [2 ( )( 3 ) 15( ) ( )(8 9 3 )] ox gdt gdt gdt gdt gst gst gdt gst gst gst gdt gdt gst gst c L d v v v v v v v v dt v d v v v v v dt + + + + + + 2 5 c L d v ox dt gst 0 id1 2 2 3 2 2 2 [ ( )(3 9 8 ) 15( ) 2 ( )( 3 )] ox gdt gdt gdt gdt gst gst gdt gst gst gst gdt gdt gst gst c L v d v v v v v v v dt v d v v v v v dt + + + + + + 4 15 c L d v ox dt gst 0 ~27~ CHAPTER IV IV. MOSFET POWER This chapter discusses the origin of MOS transistor leakage and describes the power computation techniques for conserved and dissipative components without the channel charge partition. The existence of an energy function is also validated. The conserved and dissipative power components then become the basis of conserved and dissipative current components in chapter 5. The fast scaling of operation frequency for semiconductor integrated circuits that was seen in the last few decades cannot continue. One of the reasons is the increase in power dissipation. Power limits the scaling. The high power dissipation due to small device geometry has thrown off course the roadmap of future development of semiconductor technologies as predicted in the International Technology Roadmap for Semiconductors [4.1]. When the devices are switching rapidly, the power dissipation per unit area goes up causing excessive heating. Unless a sophisticated and expensive cooling system is implemented, the device may no longer be operational. The reality is: we have reached a power limited scaling regime. Scaling now is no longer determined by the device size, but by how much power the chip can dissipate at a particular working frequency. However, the lack of suitable device models to measure this power dissipation has provided a plethora of research avenues. The conventional MOSFET models have some inherent issues and are not consistent for power and energy prediction as they: • Fail to include the first order power dissipation due to channel charge redistribution, ~28~ • Give a net nonzero power in the channel that has no physical basis from the terms that should be conserved. This makes the MOSFET modeling very important going forward into the nanometer regime for low power design techniques and poweraware architectures [4.3]. Given that the accuracy of the simulation depends on the physical representation of the device, it is very important that we have a reliable mathematical model that is able to represent the device behavior. Designers need these accurate models for circuit development. 4.1 SOURCES OF POWER DISSIPATION There are three sources of power dissipation in the MOS transistor [4.34.6]. The first source of power dissipation is due to the transistor switching that is related to the charging and discharging of the external load capacitors. The second source is from the shortcircuit power due to the current flow from the supply to the ground. These two dissipations are related to the transitions at the gate [4.7]. The third source is the leakage power. Transistor scaling has reduced the threshold voltage and increased the gate leakage resulting in higher static power. Fig. 4.1 shows all these leakage sources that are taking up the power budget. Some of these sources have dominant effects on the transistor performance in the nanometer regime [4.7, 4.8]. Figure 4.1: Leakage Current Components [4.5] ~29~ I1 PN junctions reverse bias current I2 Subthreshold leakage I3 Drain Induced barrier lowering I4 GateInduced drain leakage I5 Punchthrough I6 Narrow width effect I7 Gate oxide tunneling I8 Hot carrier injection 4.2 POWER AND ENERGY MODELING ISSUES Meyer [4.9] was the first to present a capacitive model. Ward and Dutton [4.10] pointed out the assumed charge non conservation problems in Meyer’s model. To solve these problems in transient simulation, they proposed a charge partitioning scheme with a charge conservation constraint. Sheu et al. [4.11] and Chung [4.12] made many improvements later to better derive IV and CV characteristics. One of the industry standards, the BSIM capacitive model includes many of these models to estimate the behavior of MOS transistors. The BSIM model assumes that the MOSFET capacitance is an energy storage device and uses the conserved charges (to first order) to predict the currents and voltages at different nodes. The same charge (to zero order) is also used to predict the channel power. This makes the BSIM capacitive a zero order, quasistatic power dissipation model. The model Assumes that the first order terms only contribute to energy storage Uses channel charge partition scheme and the bulk charge parameter has a nonlinear dependence on the source potential. Both these ideas leave a lot to be desired. First, the dissipative power has some higher order terms due to the charge redistribution. These higher order dissipative components become significant at higher frequencies and modify the total power dissipated in the channel [4.13]. This is explained later in section 4.5. Second, the nonlinear dependence of Abulk on vsb does not ~30~ allow the derivation of energy function from all of the conserved components [Appendix A7.2]. These effects causes the BSIM capacitive model to predict a different number for instantaneous power measured from the supply than the power dissipated in the device, clearly a violation of energy conservation principles. If an analytical closed form solution for the stored energy function is desired using nonreciprocal capacitors, the FET charge equation has to be solved for a linear source dependence of the bulk without the channel charge partition. These inconsistencies make the current BSIM capacitive model nonideal for energy estimation. 4.3 POWER MEASUREMENT TECHNIQUES Many models have been suggested for the estimation of power, like using supply current measurements [4.14], input slew dependency [4.15], propagation delay [4.16], short circuit power [4.17] and nonconventional capacitorbased methods [4.18] CMOS VDD CL t Vin Ip In Vout Figure 4.2: Dynamic Power Fig 4.2 shows one of simplest techniques used to calculate the transistor power consumption. Power is consumed when the gate drives the output out V to a new value. Assuming that the input in V changes very fast, only one transistor turns on at a time. When the output goes high, the ~31~ current flows through the PFET and goes only to the capacitor. The current component that goes down the NFET has been neglected. Similarly when the output settles to a low value, it is assumed that the current goes through the NFET. Though the PFET is not quite turned off yet, the current that is coming through the PFET is neglected. vin vout Ip In t t t t 0 T/2 T Figure 4.3: Transient Waveforms Fig 4.3 shows the transient waveforms. The output looks more like a RC time constant due to the presence of the capacitance, charging up the output from 0 to T/2 and then discharging from T/2 to T. If we look at the corresponding current plots for falling input transient, it is only the PFET that is providing the capacitor current p I . For the rising input transient, capacitor current n I is through the NFET. It should be noted that the currents mentioned above are the magnitudes of the drain current. The instantaneous power dissipation is then calculated by solving for I and V and multiplying them together. It is also assumed that the capacitors are purely energy storage devices and does not contribute to net power dissipation. Hence, during the falling input transition, power dissipation is only in the PFET. Similarly during the rising input transition, power dissipation is only in the NFET. Using these assumptions, the average power Pc0 for a complete cycle is computed using 1 / 20 [ ] 0 /2 T T Pc I pVDSpdt InVDSndt T T = ∫ + ∫ (4.1) ~32~ where VDSp and VDSn are the outputs at the PFET and NFET respectively. During the falling transition as PFET charges the capacitor, actual positive current flows from the device to the capacitor. This makes the PFET drain current p I negative. ( out ) p L I C dV dt = − (4.2) where L C is the output load. The corresponding output voltage at the PFET, DSp V becomes ( ) DSp out DD DD out V =V −V = − V −V (4.3) where DD V is the supply voltage. From (4.2) and (4.3), power dissipated in the PFET, PFET P is computed using / 2 0 T PFET p DSp P = ∫ I V dt (4.4) Similarly, the current through the NFET, n I is negative of the capacitive current. ( out ) n L I C dV dt = − (4.5) and the corresponding output voltage, DSn V is DSn out V =V (4.6) From (4.5) and (4.6), power dissipated in the NFET, NFET P is given by / 2 T NFET n DSn T P = ∫ I V dt (4.7) The average power, c0 P for a complete cycle is estimated using equations (4.4) and (4.7) as 1 [ ] Pc0 T PPFET PNFET = + (4.8) Substituting , , n p DSn I I V and DSp V in equation (4.8), the average power equation reduces to 1 / 2 0 [ ( ) ( ) ] 0 /2 T dVout T dVout Pc CL VDD Vout dt CL Voutdt T dt T dt = ∫ − + ∫ − (4.9) ~33~ Because of the fact that the transistor currents are related to the charging and discharging of the currents of the capacitor, the power integrals can be replaced from integrals over dt to an integral over dv . This gives a closed form expression for the dynamic power independent of i(t) and v(t) . 2 Pc0 f CL V DD = (4.10) There are, however, some issues in regards to the dynamic power equation (4.10). These issues are: • The MOS channel is not purely an energy storage device and has no energy function. For an energy function to exist, second order partials have to be equal. This is shown in the Appendix [A4.5A4.7]. • The MOS capacitors dissipate power and the transcapacitive terms used in the charge model includes both dissipative and conserved components. Therefore, it is not appropriate to look at the change in the energy of the external load capacitor L C in the channel as a true measure of power. Dynamic power predicted using equation (4.10) is in fact an easy way of computing the zero order power by looking at the change in energy during charging and discharging of external capacitors. Fig. 4.4 shows another capacitor based technique used for power measurement. In this type of power measurement, switch S is closed and the load capacitor CL is allowed to attain the supply voltageVDD . The switch is then opened and the CMOS gate is allowed to undergo a transition. This causes some energy consumption in the circuit, which is captured by the measuring device as a decrease in supply voltage ( Δv ). Energy dissipated in the circuit can now be estimated using 1 2 1 ( )2 2 2 Energy CLV DD CL VDD v = − − Δ (4.11) where 1 2 2 CL v Δ is the energy consumed by the circuit. This method of energy prediction is very accurate [4.18]. However, this energy prediction is not possible during the design phase. Hence, ~34~ there is a need for a verification tool that can simulate the real world behavior of the transistor during the design phase. VDD Switch S CL Measuring Device CMOS Figure 4.4: Capacitor based Power Measurement Technique This makes the next and subsequent sections of power derivation one of the most important findings of our research, where the energy function is derived from a symmetrical charge conserving FET models. Before going through the derivation, it however, becomes important to discuss the extra source of transistor power dissipation that was not included in section 4.1. It also becomes important to check the validity of the quasistatic approximation in the model derivation. Figure 4.5: Power Dissipation in MOS Transistor When the gate undergoes a transition, from vss to vdd or vdd to vss, the resistive drop (IR) and the charge redistribution cause the power dissipation in the channel. Usually, the zero order steady state current is used to determine the power dissipation. The additional power dissipation from ~35~ the channel charge redistribution is ignored. This is because, in the quasistatic model, charge redistribution is assumed to happen instantaneously with no propagation delays. However, the channel charge density still changes as an indirect function of time through the dependence on time varying terminal voltages. This allows the use of the quasistatic model to predict the charge redistribution and the associate power dissipation as long it satisfies tR > 20 T0 [4.19] where R t is the waveform rise time and 0 T is the time taken by electrons to reach the drain from the source terminal (transit time). Moreover, the conventional charge model is based on the assumption that the MOSFET capacitors do not contribute any net power dissipation in the channel. But, as shown in Appendix [A4], it is not the case. The channel capacitances are not energy conserving. They do have some power dissipative terms due to the charge redistribution in the channel. These higher order dissipative terms become significant at higher frequencies, which make it necessary to include their effects on total power for efficient power dissipation prediction. 4.4 POWER EQUATIONS Fig: 4.6: MOSFET Channel Power Calculation Fig 4.6 shows a MOS device. Considering a slice of thickness Δx , MOS channel can be thought of having two power components, due to: • Fig. 4.6 a: The current i(x) flowing through the slice of thickness Δx having a potential Δv , which looks like a series resistance and results in the power dissipation of iΔv . ~36~ • Fig. 4.6b: The rate of change of charge that is building in the slice due to the difference in current Δi . This power change vΔi is the energy stored in the charge at the potential v(x) . The instantaneous power going into the transistor channel c P can then be estimated using ( ( ) ( )) ( ( )) ( )] ( )( ( ))] 0 0 0 L d L d L d Pc ic x vcb x dx ic x vcb x dx ic x vcb x dx dx dx dx = ∫ = ∫ + ∫ (4.12) where the first integral represents change in stored energy and second term represents power dissipation. Keeping nonzero terms to first order in time derivatives, equation (4.13) can be expanded as: Pc Pc0 Pc1,diss Pc1,cons = + + where 0 ( 0( )) 0 L d Pc Ico vcb x dx dx = ∫ [Appendix 4.1] (4.13) 1, 1( 0( )) 0 L d Pc diss ic vcb x dx dx = ∫ [Appendix 4.2] (4.14) 1, 0( 1) 0 L d Pc cons vcb ic dx dx = ∫ [Appendix 4.3] (4.15) The total instantaneous power P into the transistor is the sum of channel power Pc and gate power Pg1,cons . P Pc Pg1, cons = + (4.16) where the gate power is Pg1,cons ig1vgb = (4.17) where ig1 (Appendix: A3.3) is the first order gate current component. ~37~ Equation (4.13) represents the usual zero order power dissipation. Equation (4.14) represents the first order power dissipation due to the transcapacitive transient current components and equation (4.15) represents the first order conserved power in the channel. Since the gate power estimated in equation (4.17) is assumed to be purely reactive and leakage free, it becomes necessary to add its contribution together with the conserved components from the channel to obtain a closed form solution for the stored energy function. Table 2 summarizes the power components and Appendix (A4) shows the derivation of these equations. We have used vgbt0 vgb vt0 = − . Table 4.1: Power Equations Power Linear Region Saturation Region Cutoff Region Pc0 ( 2 2 ) 2 cox v v v LK ds gst gdt μ − 2 2 cox v v LK ds gst μ 0 Pc1, diss ( )[3 2 30( )3 3 2 7 ( ) ] coxL d vds vgst vgdt vgdt vgdt v v dt gdt gst v d v v d v d v v gst dt gst gdt dt gdt dt gst gst − + + + + 10 coxL d vds vgst dt 0 Pc1, cons [ 3( ) 6 4( ( 2 ) (2 ))( 0)] ( )2 coxL d d vgdt vgdt vgst vgst K dt dt v d v v v v d v v v v gdt dt gdt gdt gst gst dt gst gdt gst gbt vgdt vgst − − + + + + + + 6 ( 3 ) coxL d vgst dt vdb vsb − + 0 4.5 ENERGY FUNCTION CALCULATION Energy is defined as the capacity to do work. In a MOSFET, work is done to transfer the charge from the source to the drain terminal. However, energy prediction is very tricky for MOS devices ~38~ as it is difficult to separate the charging (effective work) and the dissipative components of the electrons. This makes it difficult to predict how much energy is lost in the channel and how much energy is used as the effective work. To make the matter worse, the bias at the gate terminal forces these charge movements. For the model derivation, the gate is assumed to be leakage free. It is also assumed that there is no net charge transfer from the gate to the channel. However, energy is still supplied from the gate to drive the channel charges. It then becomes necessary to add the contribution from the gate together with the channel charges. As these charges are conserved over a complete cycle, it is possible to derive a closed form analytical solution for an energy function from these conserved charges. The separation of conserved components make it possible to estimate total power dissipation by leaving out energy storage terms that do not contribute to power dissipation, making the solution simple, straightforward and computationally efficient. The conserved component of channel power was given by equation (4.15). It can also be written as: 1, P dE E dV c cons dt V V dt ∂ = =Σ ∂ (4.18) Equation (4.18) can be expanded to represent channel power in the form of energy as 1, E dvgb E dv E dv P c c db c sb c cons v dt v dt v dt gb db sb ∂ ∂ ∂ = + + ∂ ∂ ∂ (4.19) where Ec is some function of voltages vgb, vsb, vdb . Since the channel receives energy from the gate during switching transient, it can be shown [APPENDIX A4.5] that the energy from the channel alone is not conserved. Hence an energy function is not possible in equation (4.19). Taking similar approach, gate power is represented using ~39~ 1, Eg dvgb Eg dv Eg dv P db sb g cons v dt v dt v dt gb db sb ∂ ∂ ∂ = + + ∂ ∂ ∂ (4.20) where Eg is also some function of vgb, vsb, vdb . Since gate is supplying the energy to the channel, it can also be shown that the gate alone has no energy function [APPENDIX A4.6]. An Energy function is possible only when the conserved components are combined [APPENDIX A4.7]. Pcons Pg1, cons Pc1, cons = + (4.21) Using equations (4.19), (4.20) and (4.21) ( , , ) ; , , E E Eg v v v c j g s d v gb sb db v v jb jb jb ∂ ∂ ∂ = + = ∂ ∂ ∂ (4.22) It can be shown that equation (4.22) can be solved [APPENDIX A4.7] to compute the energy function. Table 4.2 summarizes the energy function. Table 4.2 ENERGY FUNCTION Linear Saturation CutOff Qg ( 2 ( )2 12( ( ) / 2) vdb vsb coxL vgb v fb vsb K vdb vsb vgst K vdb vsb φ − − − − − − + − − ( ) 3 ) coxL vgb vfb vgst vsb K φ − − − − ( 0 ) coxL vgb v fb vgbt K φ − − − E f 1 2 2 {( 1)( ) 4 ( )2 ( )2} 0 coxL K vdb vsb vgbt vdb vgbt vsb Qgvt − + + − + − + 2 1 {( 1)( 0 4 2 ) ( )2} 0 0 vgbt cox L K K vsb vgbt vsb Qg vt − + + − + 2 2 0 ( 1) 0 coxL vgbt K K Qgvt − + ~40~ CHAPTER V V. FIRST ORDER CURRENT COMPONENTS AND CAPACITANCE CALCULATION In this chapter, total capacitance equations are derived from the first order drain (id1) and source (is1) current components. These total capacitances are then separated into conserved and dissipative components. Finally, an equivalent circuit is developed by following the method used by LimFossum [5.1] and results are verified for currents and charges. 5.1 FIRST ORDER CURRENT COMPONENTS As seen in Table 3.1, first order currents are functions of voltages and their time derivatives (dv/dt). However, the coefficient of dv/dt instead of being purely storage capacitance is also responsible for some of the power dissipation in the channel. This suggests that the first order drain (id1) and the source (is1) currents consist of two separate components; one that contributes to power dissipation in the channel, and another that is responsible for the energy storage. Taking this approach, the first order drain and source currents obtained in chapter 3 can be expanded as id1 id1,cons id1,diss = + (5.1) is1 is1,cons is1,diss = + (5.2) where id1,diss and is1,diss are the dissipating, while id1,cons and is1,cons are the energy storing components of first order drain and source currents. Fig. 5.1 shows this concept where first order currents id1 and is1 are separated into two components. Since the gate and the substrate currents are nondissipative in the absence of leakage, there is no need to separate them. ~41~ id1,diss id1,cons is1,cons is1,diss Figure 5.1: First order dissipative and conserved current components The dissipative current components in equations (5.1) and (5.2) are due to the first order power dissipation in the channel from the charge redistribution. It is estimated by dividing the dissipative power obtained using equation (3.1) with the total channel potential as: 1, 1, 1, , P i c diss i i d diss v s diss tt diss ds = =− = (5.3) where itt,diss is the transient transport current that is responsible for the first order power dissipation in the channel, and is defined as positive going into the drain. The energy storage components are now easily computed by subtracting the dissipated component from the first order drain and source current components. id1,cons id1 id1,diss = − (5.4) is1,cons is1 is1,diss = + (5.5) Equations (5.4) and (5.5) can also be verified by solving conserved channel power equation (4.16) obtained in chapter 4 as: Pc1,cons id1,consvdb is1,consvsb = + (5.6) Table 5.1 summarizes these first order, energy conserving and dissipative drain and source ~42~ current components in three regions of transistor operation. Table 5.1: Storage and Dissipative Current Components Linear Saturation CutOff id1, diss ( ) [3( 2 2 ) 30( )3 7 ( )] coxL vgst vgdt d d vgdt vgdt vgst vgst v v dt dt gdt gst v v d v d v gdt gst dt gdt dt gst − + + + + 10 coxL d vgst dt 0 is1, diss id1, diss − id1, diss − 0 id1,cons [ (3 5 ) 6( )2 (3 )] cox L d vgdt vgdt vgdt vgst v v dt gdt gst v d v v v gst dt gst gdt gst + + + + 6 coxL d vgst dt 0 is1,cons [ ( 3 ) 6( )2 (5 3 )] coxL d vgdt vgdt vgdt vgst v v dt gdt gst v d v v v gst dt gst gdt gst + + + + 2 coxL d vgst dt 0 5.2 CAPACITANCE DERIVATION In the following section, capacitance equations are derived that are continuous and valid in all regions of transistor operation. Conventional MOS transistor model assume the MOS channel is an energy storage device and ignores the dissipative components due to the channel charge redistribution and convection effects. It is shown [5.3] that the dissipative components have significant contributions at high ~43~ frequencies and energy conserving capacitance representation of MOSFET is misleading. However, MOS transistors can still be represented as an energy storage device if the dissipative components are separated from the total capacitances. Ours is a first step towards such a complete model, which is able to separate the total capacitance into the dissipative and conserved components. Representing the first order current ii1 in terms of capacitance: 1 ( ) ; , , , . , ii Cii tvib Cij tv jb i j g d s j ib = ∂ − Σ ∂ = ≠ (5.9) where Cii , Cij’s are total capacitances and vib , vjb are the terminal voltages with respect to the body voltage. Table 5.3 summarizes these total capacitances, which are calculated by representing id1 and is1 in the above mentioned form. Table 5.4 and 5.5, on the other hand shows the independent energy storage and dissipative capacitances. This is one of the most important findings of our research, as all other capacitive models have mixed conserved and dissipative terms. However, in our model, the energy conserving capacitances are estimated simply from the conserved current components that were calculated using equations (5.4) and (5.5). 1, ( ) ; , , , . , ii cons Ccii tvib Ccij tv jb i j g d s j ib = ∂ − Σ ∂ = ≠ (5.10) where Ccii,Ccij are the conserved components of the capacitor. In equation (5.9) and all the subsequent equations, the subscript notation ‘c’ or ‘d’ stands for conserved or dissipative components. Fig. 5.2 shows the normalized capacitance plots against different values of channel potential in 180 nm process parameters. The capacitance plot consists of total, conserved and dissipative capacitances that are calculated using respective currents. ~44~ 0.25 0.5 0.75 1 1.25 1.5 1.75 0.2 0.2 0.4 0.6 Cgs Ccsg Csg Cdg Ccdg Cddg Cdsg Cdds Ccds Cds Cgd Csd Cdsd Ccsd Figure 5.2 Total, Conserved and Dissipative Capacitances vs vds Table 5.3: Total Capacitances TOTAL CAPACITANCES Linear Saturation CutOff Cgb ( )2 2 3(1 ) ( )2 2 k vgdt vgst coxL k v v gdt gst − + + 2 2 3(1 ) k c L + k ox 2 2 (1 ) k coxL + k Cgd 2 ( 2 ) 3 ( )2 vgdt vgst coxLvgdt vgdt vgst + + 0 0 Cgs 2 (2 ) 3 ( )2 vgdt vgst coxLvgst vgdt vgst + + 2 3 coxL 0 Csg 2 8 3 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 2 coxL 0 Csb 2 k Ccsg 2 k Ccsg 0 ~45~ Csd 2 (1 ) ( 3 ) 6 ( )2 k vgdt vgdt vgst coxL vgdt vgst + + + 0 0 Cdg 3 2 8 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 6 coxL 0 Cdb 2 k Ccdg 2 k Ccdg 0 Cds 2 (1 ) (3 ) 6 ( )2 k vgst vgdt vgst coxL vgdt vgst + + − + 2 1 6 k c L ox + − 0 Table 5.4: Conserved Capacitances CONSERVED CAPACITANCES Linear Saturation CutOff Cgb 2 2 ( )2 3(1 ) ( )2 k vgdt vgst coxL k v v gdt gst − + + 2 2 3(1 ) k c L + k ox 2 2 (1 ) k coxL + k Cgd 2 ( 2 ) 3 ( )2 vgdt vgst coxLvgdt vgdt vgst + + 0 0 Cgs 2 (2 ) 3 ( )2 vgdt vgst coxLvgst vgdt vgst + + 2 3 coxL 0 Ccsg 2 8 3 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 2 coxL 0 Ccsb 2 k Ccsg 2 k Ccsg 0 Ccsd 2 (1 ) ( 3 ) 6 ( )2 k vgdt vgdt vgst coxL vgdt vgst + + − + 0 0 ~46~ Ccdg 3 2 8 2 6 ( )2 c L vgdt vgstvgdt vgst ox vgdt vgst + + + 1 6 coxL 0 Ccdb 2 k Ccdg 2 k Ccdg 0 Ccds 2 (1 ) (3 ) 6 ( )2 k vgst vgdt vgst coxL vgdt vgst + + − + 2 1 6 k c L ox + − 0 Table 5.5: Dissipative Capacitances DISSIPATIVE CAPACITANCES Linear Saturation CutOff Cddg ( )(3 2 14 3 2 ) 3 30 coxL vgst vgdt vgdt vgdtvgst vgst vgdt vgst − + + ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 1 10 coxL 0 Cdds 2 (1 ) ( ) (7 3 ) 3 30 k coxL vgst vgdt vgst vgdt vgst vgdt vgst + − + − ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 2 1 10 k c L ox + − 0 Cddb 2 ( )(3 2 14 3 2 ) 3 30 coxk L vgst vgdt vgdt vgdtvgst vgst vgdt vgst − + + − ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 2 10 k c L ox − 0 Cdsg Cddg − Cddg − 0 Cdsd 2 (1 ) ( ) (3 7 ) 3 30 k coxL vgdt vgst vgdt vgdt vgst vgdt vgst + − + ⎛ + ⎞ ⎜ ⎟ ⎝ ⎠ 0 0 Cdsb Cddb − Cddb − 0 ~47~ 5.3 EQUIVALENT CIRCUIT Cgs Cbs Cbd Cgd itt,cons itt,diss Ic0 Source Drain Gate Substrate is ig id ib Cgb MOSFET ig is ib id Figure 5.3: Equivalent Circuit We have developed an equivalent circuit in this section by following the method used by Lim Fossum [5.1]. Tables [5.35.5] showed that the capacitances are not reciprocal, which makes the capacitance representation using two terminal reciprocal capacitances impossible if these capacitances are made to represent the total first order drain current. However, equation (5.4) can be rewritten with reciprocal capacitors [Appendix A5.13] as id1, cons Cgd tvdg Cbd tvdb itt, cons = ∂ + ∂ + (5.11) where itt, cons (Cgd Ccdg ) tvgb (Ccsd Ccds ) tvsb Ccsd tvds = − ∂ + − ∂ + ∂ (5.12) The dissipative component of current from equation (5.3) can also be written in terms of dissipative capacitances as id1, diss Cddd tvdb Cddg tvgb Cdds tvsb itt,diss is1, diss = ∂ − ∂ − ∂ = =− (5.13) Fig.5.3 shows an equivalent circuit of a four terminal MOSFET. The circuit is equivalent to Lim Fossum’s, but we have broken the transcapacitive transport current itt into conserved and ~48~ dissipative components. There are three current components flowing from the drain to the source terminal. The current component responsible for the first order power dissipation in the channel is represented by itt,diss. The conserved current component is represented by itt,cons. Ic0 represents the steady state zero order current. Two terminal reciprocal capacitances Cgd, Cgs, Cbd, Cbs and Cgb represents the conserved gate to drain, gate to source, substrate to source, substrate to drain and gate to substrate capacitances respectively. These reciprocal capacitances do not conserve energy by themselves; the conserved component of itt must be included. Cddd, Cddg, Cdds in equation (5.13) represents the dissipative drain to drain, drain to gate and drain to source capacitances respectively. ~49~ CHAPTER VI VI. COMPARISON AND DISCUSSION In this section we compare our results with LimFossum’s SOI model [6.16.3] and the BSIM Capacitive Model [6.46.5]. We also discuss the mechanism of net transfer of energy from the gate to the channel and show that the higher order dissipative terms modify the total power equation and have significant effects at higher frequencies. 6.1 MODEL VERIFICATION AND ADVANTAGES Our model verifies that Ward’s [6.6] method of channel charge partitioning works correctly when the bulk charge has a linear dependence on the channel potential (vsb). Our model also verifies LimFossum’s equations for a fully depleted SOI MOSFET that uses Ward’s partition scheme. It predicts the same source and drain currents, and hence the same terminal capacitances ( ij C ) as shown in Fig. 6.1. However, we are able to partition these total terminal capacitances into conserved ( Ccij ) and dissipated ( Cdij ) components. The partitioning approach to capacitances offers several advantages over conventional transcapacitances: • The energy stored in the conserved capacitances can be predicted. • They can be made to agree with Meyer’s [6.7] capacitances if the body effect and body bias are ignored. Fig 6.1 and Fig 6.2 shows the capacitances. The total capacitance shown in Fig 6.1 is separated into conserved and dissipative capacitances in Fig 6.2 and is written as Cij Ccij Cdijwhere i, j g, s,d = + = ~50~ 0.25 0.5 0.75 1 1.25 1.5 1.75 0.2 0.2 0.4 0.6 ox cap c L vds 0.25 0.5 0.75 1 1.25 1.5 1.75 0.2 0.2 0.4 0.6 ox cap c L vds Figure 6.1: Terminal capacitances vs vds Figure 6.2: Capacitance vs vds Our other significant contribution has been in the power estimation. Our models have improved the device power estimation by implementing two important concepts: • First order terms have to be included for power dissipation estimation as they become significant at higher frequencies. • Stored components can be ignored for computationally efficient power dissipation estimation. The average device power computation is then possible by taking dissipative current times voltage and integrating them over time. 6.2 ENERGY PUMPING It is important to understand the pumping action of the gate to understand the power components from different sources. When the gate undergoes a rising (falling) transition, electrons (holes) are sucked out of the source terminal and stored in the channel. During the falling transition, these electrons (holes) are pushed out of the channel into the drain terminal. Even though the gate charge integrates out and there is no net charge transfer, there is transfer of energy from the gate to the channel. The gate acts as a energy source which allows the electrons (holes) to move in the channel, while the channel acts as a recipient of this energy. Moreover, if power calculations are done using only the channel current components, it may appear that the MOS transistors are generating extra energy in the channel. In reality, power is pumped from the gate to the channel and when the gate contributions are added, the conserved ~51~ terms cancel out. However, if the gate contributions are neglected, the channel ends up looking like an energy generator. Therefore it is not appropriate to integrate the channel currents alone for the power computation. Contributions from the gates need to be included. Fig. 6.3 shows the pumping action of the gate. Figure 6.3: Gate pumping action 1×1010 2×1010 3×1010 4×1010 5×1010 0.00003 0.00002 0.00001 0.00001 0.00002 0.00003 Pg1,cons Pc1,cons Figure 6.4: Average conserved gate and channel power vs. frequency Fig. 6.4 shows the average conserved gate ( Pg1,cons ) and channel ( Pc1,cons ) power plots against frequency for 180 nm process parameters. The positive power from the gate shows that energy is flowing from the gate to the channel, while the negative channel power shows the energy generation at the channel. Since these average powers are equal and opposite, they cancel out over a complete cycle and contribute no net energy in the channel. This is all possible due to the existence of an energy function for the conserved components. The existence of ~52~ energy function validates the notion that the conserved terms do not contribute any net power dissipation in the channel. It also makes it possible to leave out power terms that do not contribute to net power dissipation in the total power equation, making the simulation simple and computationally efficient. This is explained in detail in the following section. 6.3 TOTAL FIRST ORDER POWER It is possible to derive the total first order MOS power by using the equation P ig1vgb id1vdb is1vsb = + + (6.1) The problem here is the complexity in the first order current terms. Other than the first order gate current, first order drain and source currents have both the conserved and dissipative terms, which are not separated. As mentioned in previous chapters, the gate and the conserved components of drain and source currents contribute no net power dissipation in the channel. Its presence just adds the extra complexity and slows down the simulation process. The separation of the first order terms into energy conserving and power dissipating terms on the other hand, simplifies the equation as energy conserving terms are taken out from the simulation. The total first order power then reduces to P id1,dissvdb is1, dissvsb = + (6.2) It should also be pointed out that leaving the gate component altogether and using the equation P id1vdb is1vsb = + (6.3) is not a very good option. In that case, as mentioned in section (6.1), the conserved channel power component acts as an independent source of energy. Equations using such models are inconsistent and should be avoided. 6.4 SIMULATION EXAMPLE A simple simulation is used to show the importance of first order power using only the dissipative components. Fig. 6.5 shows the idealized voltage waveforms for the drain and the gate terminals used to turn a transistor on then off. ~53~ Figure 6.5: Idealized voltage waveforms The average dissipative power from the first transition (vds=vdd) when vgb goes from low at t0 to high at t1 is computed by 1 1 1 ( 1, 1, ) ( 0 1) ( 1 0) 0 t Pc t id dissvdb is dissvsb dt t t t t = ∫ + → − (6.4) If we assume the source and the substrate are at the same potential (vsb=0), equation (6.4) can be rewritten as 1 1 ( ) 1( ) ( ) 0 1, 0 1 1 0 t Pc t id dissvdb dt t t t t = ∫ → − (6.5) In the second power dissipating transition, when the gate terminal is high, the drain swings from high at t1 to low at t2. The dissipative power equation (6.4) reduces to 1 2 1( ) ( ) 1, 1 2 2 2 1 t Pc id dissvdbdt t t t t t = ∫ → − (6.6) During the interval t2 to t4, there is no power dissipation in the channel (vdb=0). Even though energy flows from the gate to the channel as vgb changes, the energy is transferred to the channel carriers and is not dissipated. The final power transition occurs when the drain waveform swings from low at t4 to high at t5. As the gate voltage has already reached a steady low value, the power equation becomes ~54~ 1 5 1( ) ( ) 1, 4 5 5 4 4 t Pc id dissvdb dt t t t t t = ∫ → − (6.7) The total dissipative power for a complete cycle is computed taking the sum of all these powers 1 ( 0 1) ( 1 2) ( 4 5) Pc P t t P t t P t t = → + → + → (6.8) For a complete cycle, energy is conserved. This allows us to leave out the conserved component from the power equation for computationally efficient power dissipation prediction. Nonetheless, the total dissipative powers predicted by equation (6.8) have first order terms. These first order dissipative components become significant at higher frequencies and modify the total power dissipated in the channel as shown in Fig 6.6. The total power is no longer constant, and at high frequencies becomes dependent on the switching frequencies. 1×1010 2×1010 3×1010 4×1010 5×1010 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 P Pc0 Pc1,diss Fig 6.6: Total power vs. frequency The result also shows that we need to be extra careful while doing the power measurements. It is not appropriate to look only at the channel dissipation; the first order power dissipation does have contributions from the gate. If the power dissipation is estimated by just considering the total channel power, there would be an extra negative component from the conserved energy. In that case, the channel would seem to act as an energy generator. Fig 6.7 and Fig 6.8 shows the current and the corresponding power plots. ~55~ Figure 6.7: Current Plots Figure 6.8: Power Plots 0.0031 0.0021 0.0011 0.0001 0.0009 0.0019 0 1E12 2E12 3E12 4E12 5E12 6E12 7E12 8E12 id0 id1D is1D id1C is1C ig1 T(sec) I(A) 0.008 0.006 0.004 0.002 0 0.002 0.004 0.006 0 1E12 2E12 3E12 4E12 5E12 6E12 7E12 8E12 p0 p1 D p1 C T(sec) P(W) ~56~ CHAPTER VII VII. DEPENDENCE OF THE BSIM ABULK PARAMETER ON THE SOURCE POTENTIAL In this chapter, the capacitive model is extended to include the source potential (vsb) dependence of the bulk charge coefficient Abulk. Until this chapter, the BSIM bulk parameter, Abulk [Appendix A7.1], was assumed to be constant with respect to the source potential, which made the derivation of the energy function possible. It also made the evaluation of the terminal capacitances straightforward, sacrificing very little accuracy. However for circuits where vsb is not constant and bulk parameter dependence is included, unlike the Lim and Fossum model, the BSIM capacitive model fails to give an energy function for the conserved power components [Appendix A7.2]. The energy supplied from the gate does not balance with the energy generated in the channel and an extra power component shows up in the channel that has no physical basis. The term that gives energy storage in our model (equation (4.21)) does not give energy storage in BSIM, which makes the BSIM model inconsistent for power and energy prediction. In general, when the conserved power components are integrated over a complete switching cycle and the transistor is returned to the original state, there is a non nonzero power contribution. This is where the inconsistency of the BSIM model is evident. The BSIM bulk charge coefficient has vsb dependence and when this is included, the BSIM model: • Generates extra current that has no physical basis • Gives a net nonzero power that shows up in the channel from the terms that are supposed to be conserved, • Fails to give an energy function from all of the conserved components ~57~ It should also be pointed out that we are not finding the energy function for the total transistor power, as not all the power components are conserving. It is also not true that the BSIM model has no energy function. It has a quasienergy function; the same term that shows up in our model (Chapter 4) also show up in the BSIM model. Obviously for those terms there is an energy function. But, the BSIM model also has some extra terms due to the vsb dependence that do not show up in our model, which makes it impossible to find an energy function for all of the conserved components. In other words, the quasiconserving BSIM model is inconsistent. It generates extra power in the channel that has no physical basis. Though the extra term has no physical rationale, it is thought to be from the incomplete mathematical representation of the square root dependence of the bulk charge on the channel potential vcb, which the BSIM model tries to linearise using the first two terms of a Taylor’s expansion. It can then be assumed that if the higher order terms are included that were left out in the Taylor’s expansion, the BSIM model should provide the correct energy function. Nonetheless, the good news is that we can still apply our model to BSIM by comparing the energy differences between the models. By doing so, we should be able to separate out the energy function from all the terms except for those that have vsb dependence and also evaluate the physically inconsistent extra dissipating components. 7.1 EVALUATION OF EXTRA CURRENT COMPONENTS Our conserved components of the gate ( ig1, cons ), source ( is1, cons ) and the drain ( id1, cons ) currents are given in Appendix (A3.3.5), and the respective BSIM components ( ig1cons, B , is1cons, B and id1cons, B ) can be evaluated including the source potential dependence on the bulk charge parameter using the equations given in Appendix (7.3). ~58~ The difference in the first order gate current due to the source dependence of the BSIM bulk charge parameter is then given by ig1, cons Extra ig1cons, B ig1, cons = − (7.1) Similarly, the difference in the conserved first order drain current is given by id1, cons Extra id1cons, B id1cons = − (7.2) and the difference in the first order source current is given by is1, cons Extra is1, cons, B is1, cons = − (7.3) These extra conserved first order gate, drain and the source currents predicted by equations (7.1 7.3) causes extra power in the channel that has no physical basis, and can be estimated using Pg1,cons Extra Pg1,cons,B Pg1,cons = − (7.5) Pc1,cons Extra Pc1,cons,B Pc1,cons = − (7.6) P1,cons Extra Pg1,cons Extra Pc1,cons Extra = + (7.7) where Pg1, cons, B ig1, cons, B vgb = and Pc1, cons, B id1, cons, B vdb is1, cons, B vsb = + 7.2 SIMULATION EXAMPLE In this section, a simple simulation example is presented using a pass transistor logic. Though it is not straightforward to separate the conserved and the dissipative power components in the BSIM model (due to the channel charge partition), the example does show the existence of extra power due to vsb dependence of Abulk. A pass transistor is chosen because they have a high vsb swing which makes the BSIM models’ unphysical effect (generation of extra power) more ~59~ pronounced. For the BSIM model to be consistent, it is assumed that the difference from the first order dissipative power should give the correction term. This correction term should then balance out the extra power component generated in the channel. vdd vdd vddvt vdb vgb vsb t0 t1 t2 t3 t4 t5 Time Voltage G D S Figure 7.1: Pass transistor simulation Voltage Waveforms (180nm process parameters) Fig. 7.1 shows the idealized voltage waveforms for the drain, gate and the source terminals. The drain terminal is assumed to be high ( vdd ) during the entire simulation, while the gate and the source potentials are varied to calculate the extra power component. In the first transition (t0 to t1), the gate terminal goes from low (0) at t0 to high ( vdd ) at t1, while the source potential remains low (0). The transistor enters the saturation as soon as the gate to source potential vgb vsb − becomes greater than the threshold voltage vt . The extra energy Et1 , calculated from the extra power (eq. (7.7)) is then given by 1 1 1, 0 t Et P cons dt t Extra = ∫ (7.8) During the second transition (t1 to t2), the gate terminal stays high ( vdd ) and the pass transistor remains in the saturation. The source terminal on the other hand, goes from low (0) to high ( vdd vt − ) and the extra energy Et2 becomes ~60~ 2 2 1, 1 t Et P cons dt t Extra = ∫ (7.9) The transistor now enters cutoff (at t2) and remains there even though the gate and source terminals come back to their original states at t4 and t5. The extra energies during these transitions are given by 3 3 1, 2 t Et P cons dt t Extra = ∫ 4 4 1, 3 t Et P cons dt t Extra = ∫ (7.10) 5 5 1, 4 t Et P cons dt t Extra = ∫ Combining all, total energy difference ( Et ) can be written as Et Eti where i 1 to 5 i = Σ = (7.11) For a complete cycle, energy should have been conserved and there should have been no contribution. But as shown by equation (7.11) and Fig 7.2, this is not the case. There is some extra power in the channel P1, cons Extra , which is more than the first order dissipative power Pc1,diss . The correction term from the difference in first order dissipative power Pc1, diss Extra that we thought would negate the extra channel power was nonexistent. 1×109 2×109 3×109 4×109 5×109 5×107 1×106 1.5 ×106 2×106 2.5 ×106 3×106 3.5 ×106 Figure 7.2: Extra power dissipation ~61~ Fig. 7.2 also shows that the frequency dependence of power components becomes significant at higher frequencies and also raises the first order power dissipation to a new value P1, which includes the first order dissipative power ( Pc1,diss ) and all other extra unphysical components ( P1,cons Extra and Pc1,diss Extra ). It also proves that the energy pumped from the gate does not balance out in the channel as was the case when Abulk was assumed to be a constant. In this particular case, the channel acts as an independent energy generator. This error, together with the noninclusion of first order dissipative power makes the BSIM model inconsistent for energy and power prediction. Fig. 7.3 compares the differences in the bulk charge parameters (Abulk vs. 1+k2) and the threshold voltages (Vt,B and Vt) between BSIM and our models, while Fig. 7.4 shows the zero order current plot for the simulation example mentioned above. From the plots 7.3 and 7.4, it is evident that our parameters match very well with the BSIM parameters when the zero order current is dominant. Figure 7.3: Abulk vs. (1+k2) and Vt’s (Top) Figure 7.4: Zero order current plots (Bottom) ~62~ Fig 7.5 shows the instantaneous first order gate, drain and source current components. Here also, the plots matches very well and the difference is evident only in the first order source current, which as mentioned above, is due to the dependence of source potential and other extra components on the BSIM bulk charge parameter Abulk [Appendix 7]. Figure 7.5: First order currents ~63~ 7.3 CONCLUSION Conventional MOS models for circuit simulation assume that the channel capacitances do not contribute to net power dissipation. Numerical integration of channel currents and instantaneous terminal voltages however shows the existence of first order dissipating terms. Given that the accuracy of the simulation depends on the physical representation of the device, it is very important that we have a reliable mathematical model that is able to represent the device behavior. Designers need these accurate models for circuit development. To overcome the limitation of conventional charge based models, a selfconsistent, first order, quasistatic, power dissipation model has been developed that is able to • Predict the exact solution to first order 1D channel equations for MOSFETs without a channel charge partition approximation provided that the charge has a linear dependence on the channel potential. • Validate the terminal currents as being the same as Ward’s channel charge partition approximation. • Validate that Ward’s partition scheme is correct as long as the charge has a linear dependence on the channel potential. • Derive the first order channel charge (qc1 ) and current (ic1) as a function of position (x) inside the channel. • Derive the first order power dissipation and conserved components. • Estimate energy function. • Separate the terminal current into conserved and dissipative components. • Identify the inconsistencies in the BSIM power model. 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Meyer, “MOS models and circuit simulation,” RCA Rev., vol. 32, pp. 4263, 1971. ~72~ APPENDICES APPENDIX 1: 180 NMOS SPICE model parameters A1.1 180nm NMOS SPICE Parameters .model NMOS NMOS +Level = 49 +Lint = 4.e08 Tox = 4.e09 Clc= 0.0000001 Cle= 0.6 +Vth0 = 0.3999 Rdsw = 250 Dwc= 0 Vfbcv= 1 +lmin=1.8e7 lmax=1.8e7 wmin=1.8e7 wmax=1.0e4 +Tref=27.0 version =3.1 Cf= 1.069e10 Dlc= 4E08 +Xj= 6.0000000E08 Nch= 5.9500000E+17 +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 +wwn= 0.00 ll= 0.00 +lw= 0.00 lwl= 0.00 wint= 0.00 +wl= 0.00 ww= 0.00 wwl= 0.00 +Mobmod= 1 binunit= 2 xl= 0 +xw= 0 binflag= 0 +Dwg= 0.00 Dwb= 0.00 +K1= 0.5613000 K2= 1.0000000E02 +K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000 +Dvt2= 8.0000000E03 Dvt0w= 0.00 Dvt1w= 0.00 +Dvt2w= 0.00 Nlx= 1.6500000E07 W0= 0.00 +K3b= 0.00 Ngate= 5.0000000E+20 +Vsat= 1.3800000E+05 Ua= 7.0000000E10 Ub= 3.5000000E18 +Uc= 5.2500000E11 Prwb= 0.00 +Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E02 +A0= 1.1000000 Keta= 4.0000000E02 A1= 0.00 +A2= 1.0000000 Ags= 1.0000000E02 B0= 0.00 +B1= 0.00 +Voff= 0.12350000 NFactor= 0.9000000 Cit= 0.00 +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 +Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000 +Pclm= 5.0000000E02 Pdiblc1= 1.2000000E02 Pdiblc2= 7.50000E03 +Pdiblcb= 1.3500E02 Drout= 1.7999999E02 Pscbe1= 8.66000E+08 +Pscbe2= 1.00000E20 Pvag= 0.2800000 Delta= 1.0000000E02 +Alpha0= 0.00 Beta0= 30.0000000 +kt1= 0.3700000 kt2= 4.0000000E02 At= 5.5000000E+04 +Ute= 1.4800000 Ua1= 9.5829000E10 Ub1= 3.3473000E19 +Uc1= 0.00 Kt1l= 4.0000000E09 Prt= 0.00 +Cj= 0.00365 Mj= 0.54 Pb= 0.982 +Cjsw= 7.9E10 Mjsw= 0.31 Php= 0.841 +Cta= 0 Ctp= 0 Pta= 0 +Ptp= 0 JS=1.50E08 JSW=2.50E13 +N=1.0 Xti=3.0 Cgdo=2.786E10 +Cgso=2.786E10 Cgbo=0.0E+00 Capmod= 2 +NQSMOD= 0 Elm= 5 Xpart= 1 +Cgsl= 1.6E10 Cgdl= 1.6E10 Ckappa= 2.886 ~73~ APPENDIX 2: 180 PMOS SPICE model parameters A2.1 180nm PMOS SPICE Parameters .model PMOS PMOS +Level = 49 +Lint = 3.e08 Tox = 4.2e09 +Vth0 = 0.42 Rdsw = 450 +lmin=1.8e7 lmax=1.8e7 wmin=1.8e7 +wmax=1.0e4 Tref=27.0 version =3.1 +Xj= 7.0000000E08 Nch= 5.9200000E+17 +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 +wwn= 0.00 ll= 0.00 +lw= 0.00 lwl= 0.00 wint= 0.00 +wl= 0.00 ww= 0.00 wwl= 0.00 +Mobmod= 1 binunit= 2 xl= 0.00 +xw= 0.00 +binflag= 0 Dwg= 0.00 Dwb= 0.00 +ACM= 0 ldif=0.00 hdif=0.00 +rsh= 0 rd= 0 rs= 0 +rsc= 0 rdc= 0 +K1= 0.5560000 K2= 0.00 +K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000 +Dvt2= 1.0000000E02 Dvt0w= 0.00 Dvt1w= 0.00 +Dvt2w= 0.00 Nlx= 9.5000000E08 W0= 0.00 +K3b= 0.00 Ngate= 5.0000000E+20 +Vsat= 1.0500000E+05 Ua= 1.2000000E10 Ub= 1.0000000E18 +Uc= 2.9999999E11 Prwb= 0.00 +Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E03 +A0= 2.1199999 Keta= 2.9999999E02 A1= 0.00 +A2= 0.4000000 Ags= 0.1000000 B0= 0.00 +B1= 0.00 +Voff= 6.40000000E02 NFactor= 1.4000000 Cit= 0.00 +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 +Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000 +Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2= 8.0000000E05 +Pdiblcb= 0.1450000 Drout= 5.0000000E02 Pscbe1= 1.0000000E20 +Pscbe2= 1.0000000E20 Pvag= 6.0000000E02 Delta= 1.0000000E02 +Alpha0= 0.00 Beta0= 30.0000000 +kt1= 0.3700000 kt2= 4.0000000E02 At= 5.5000000E+04 +Ute= 1.4800000 Ua1= 9.5829000E10 Ub1= 3.3473000E19 +Uc1= 0.00 Kt1l= 4.0000000E09 Prt= 0.00 +Cj= 0.00138 Mj= 1.05 Pb= 1.24 +Cjsw= 1.44E09 Mjsw= 0.43 Php= 0.841 +Cta= 0.00093 Ctp= 0 Pta= 0.00153 +Ptp= 0 JS=1.50E08 JSW=2.50E13 +N=1.0 Xti=3.0 Cgdo=2.786E10 +Cgso=2.786E10 Cgbo=0.0E+00 Capmod= 2 +NQSMOD= 0 Elm= 5 Xpart= 1 +Cgsl= 1.6E10 Cgdl= 1.6E10 Ckappa= 2.886 +Cf= 1.058e10 Clc= 0.0000001 Cle= 0.6 +Dlc= 3E08 Dwc= 0 Vfbcv= 1 ~74~ APPENDIX 3: MOSFET CURRENT EQUATIONS The zero and first order channel charges as well as currents were used in chapter 3. However, the derivations were not shown, which is given in this appendix. It should also be pointed out that these derivations are very tedious and results would not have been possible without the help of sophisticated tools like Mathematica. A3.1 Zero Order Current Component In equation (3.27), the zero order charge qc0 at a distance x along the channel is given by ( 2(1 / ) 2 / qc0 qs x L qd x L = − − + where L is the length of the channel. qs and qd are the source and the drain charges per unit length as given in (3.14) and (3.18). These charges can be substituted into the steady state current equation (3.28) to represent Ic0 in terms of voltages. ( 2 2) ( 2 2) 02 2 Ic qd qs vgst vgdt LcoxK LCc μ μ = − = − (A3.1) In pinchoff saturation, the drain charge density ( qd ) is zero. This reduces the zero order current (A3.1) to 2 0 2 cox Ic vgst LK μ = (A3.2) The corresponding drain to source potential in saturation ( vdssat ) can be estimated by setting vgdt vgb vt vsb K(vdb vsb ) 0 = − − − − = so that vgb vt vsb vdssat K − − = where 2 1 k SOI K Abulk BULK ⎧ + → = ⎨ → ⎩ as defined in (3.24). ~75~ In cutoff, it is assumed that there is no channel current, which is made possible by setting the source charge density qs to zero. Ic0 0 = (A3.2) (A3.1), (A3.2) and (A3.3) give the usual equations for the steady state current neglecting velocity saturation effects. A3.2 First Order Channel Charge and Channel Current The derivation of first order channel charge and current components are one of the most important findings of our research. The first order channel charge allows calculating the first order channel current without a charge partition, which can be used to calculate the first order drain and source currents. The first order channel current also makes it possible to derive the energy stored and dissipative power components. Since it is crucial component of our research, a detailed derivation is presented in this appendix. Taking charge density as a function of potential along the channel, and keeping terms of first order in time derivatives, the current continuity equation (3.25) can be written as ( 0 1 1 0 ) 0 d d d Cc d qc qc qc qc qc dx dx dx μ dt + =− (A3.2.1) Rearranging the terms, first order channel charge per unit length becomes 1 [ ] 1 0 1 0 0 Cc d qc qc x dxdx c x c qc dt μ = − ∫ ∫ + + (A3.2.2) where c1 and c0 are constants of integration, and can be calculated using the boundary condition qc1 0 = at x = 0 and x = L 0 0[ ] 0 (4 5 2 2 ) 4 2 4 15( 2 2)3 Cc d c qc x dxdx dt x q q d q q d q q d q Cc d s dt d d dt s s dt s L qs q q d s μ μ = ∫ ∫ → − + = − + (A3.2.3) ~76~ 1 0[ ] ( ( 5 5 3 2 4 5) (4 5 5 2 3 5) ) 4 15( 2 2)3 Cc d c qc x dxdx dt x L q d q q q q q q q q q q d q Cc d dt d d d s s s d d s s dt s L qd qs μ μ = ∫ ∫ → − − + − − + = − + (A3.2.4) Substituting the values of c0, c1 and qc0 in (A3.2.2), the first order charge at any point x along the channel becomes 4(4 5 2 2 ) 1 {4 ( 1 2 2 ( 2 2)3 ( ) 15 (( 5 5 4 3 2( ) 4 2 3( ) 4(4 ) 4 ( 4 )) ) /( )2( )3) L q q q d q q d q q d q q C L s d s dt d d dt s s dt s c c q q qs L x qd x d s L q d q q d q q q d q d q q q d q d q d dt d s dt s d s dt d dt s d s dt d dt s q q d q d q q q d q d q x q q q q d s dt d dt s d s dt d dt s d s d s μ − + = − + − + − + − + − + + − + − + + + − + 2 2 3/ 2 1 ( ) 2 2 ( (4 5 ) ( 2 2)3 ( )( )( ) ))) qs L x qd x d d d Lqs qd qs qd qd qs qs qs q q L dt dt dt d s q q q q q d q q d q x d s d s d dt d s dt s − ⎛ − + ⎞ ⎜ ⎟ − + − ⎜⎜ ⎟⎟ − ⎝ ⎠ − + − (A3.2.5) The first order channel current at any position x along the channel can now be estimated using 1 ( 0 1 1 0) i q d q q d q c C c dx c c dx c c μ = + (A3.2.6) Taking derivatives of qc0 and qc1, and substituting the corresponding values, (A3.2.6) expands to {4( ( 4 3 4 2 2 4 3 4 4) 1 15( )2( )3 (4 4 4 3 4 2 2 3 4)} 10( )( 2(1 ) 2 { (2 (3 2 2) ) ( 2 2)( ) } i L q d q q q q q q q q q c q q q q d dt d d d s d s d s s d s d s q d q q q q q q q q q d dt s d d s d s d s s q q q x q x d s s L d L q q d q q q q d q q q q d q q d q x S d dt d s d s dt s d s d dt d s dt s = + − − − + − + + + − − − + − + − − − − − (A3.2.7) As mentioned above, this is one of the most important findings of our research and can be solved to find the first order drain ( ic1 id1, x L) − = → and source (ic1 is1, x 0) = → current components, which are shown in Table 3.1. These results obtained without partitioning the channel charge are ~77~ in agreement with previous results (LimFossum and BSIM) which were obtained using Ward’s partition. Therefore we have verified that Ward’s partition is correct when the voltage dependence of Abulk is ignored and the channel charge is linearly dependent on vcb. A3.3 First Order Gate Current We present here the derivation of the gate current. These derivations are not different than what have been done already and can be found in the literature. The total gate charge (Qg ) can be estimated by integrating the gate charge density from the source (x=0) to the drain terminals (x=L) as 0 L Qg qgdx = ∫ (A3.3.1) where channel current equation ( , ) ( , ) ( ) 0 L vdb ic x t dx qc x t dvcb x vsb ∫ = μ ∫ can be solved to get ( , ) ( ) 0 ( , ) L vdb q x t dx c dv x v i x t cb sb c ∫ = μ ∫ (A3.3.2) Replacing 0 L ∫ dx in (A3.3.1), it can be rewritten as ( , ) ( , ) ( ) 0 vdb Qg qg x t qc x t dvcb x ic vsb μ = ∫ (A3.3.3) which can be solved to get the total gate charge. ( )2 2 ( ) 12( ) 2 vdb vsb K vdb vsb Qg coxL vgb v fb vsb K vdb vsb vgst φ ⎛ ⎞ ⎜ − − ⎟ = ⎜ − − − − + ⎟ ⎜ − ⎟ ⎜ − ⎟ ⎝ ⎠ (A3.3.4) The first order drift current flowing in the gate terminal can now be calculated from ~78~ 1 d dvgb dQg dv dQg dv dQg i Q db sb g dt g dt dv dt dv dt dv gb db sb = = + + (A3.3.5) Taking the derivatives, the first order gate current in the linear region becomes (3( 1) ( )2 2 ( 2 ) 2 (2 ) ) 1 3 ( )2 K d v v v v d v v v v v v d v i c L dt gb gdt gst gdt dt gdt gdt gst gst gdt gst dt gst g ox K v v gdt gst − + + + + + = + (A3.3.6) In pinchoff saturation, when qd 0 = , ig1 reduces to 1 (3( 1) 2 ) 3 coxL d d ig K vgb vgst K dt dt = − + (A3.3.7) In cutoff, though the drift components of the drain and the source currents are zero, the gate still has some current, which can be estimated by setting qs 0 = in equation (A3.3.5) 1 ( 1) coxL d ig K vgb K dt = − (A3.3.8) ~79~ APPENDIX 4: MOSFET POWER EQUATIONS This appendix describes the detailed derivations of MOS power components that were used in chapter 4. To avoid confusion with the general definition of the static and dynamic power terms, channel power components are defined as the zero and the first order powers in the dissertation. It should be pointed out that the zero order power defined in equation (4.14) is different than the static power. In general, static power is defined as being independent of time (time invariant). However, the zero order power that has been used in this research is time variant. Although there is no explicit time dependence, it depends on the terminal voltages that change in time. The first order power on the other hand, depends on the time derivatives of the terminal voltages, while the dynamic power that has been used in the literature depends on energy stored in external capacitances which is dissipated by both zero order and first order power in the transistor. A4.1 Zero order power The zero order power is given in equation (4.14) as 0 [ 0( 0( ))] 0 L d Pc Ic vcb x dx dx = ∫ (A4.1.2) since Ic0 is independent of the position along the channel x, equation (A4.1.1) reduces to Ic0vds where Ic0 is given in equation (A4.1) as ( 2 2) 0 2 Ic cox vgst vgdt KL μ = − (A4.1.2) From (A4.1.2) and (A4.1.1) ( 2 2) 0 2 Pc coxvds vgst vgdt LK μ = − (A4.13) In pinch off saturation, the change density at the drain is assumed to be zero, which reduces (A4.1.3) to 2 0 2 Pc coxvdsvgst LK μ = (A4.1.4) In cutoff region, when the source charge density becomes zero, equation (A4.1.4) further reduces to 0. ~80~ A4.2 First order dissipated power In equation (4.15), the first order channel dissipated power is given by 1, [ 1( 0( ))] 0 L d Pc diss ic vcb x dx dx = ∫ (A4.2.1) where ic1 is the first order channel current given by (A3.2.7). Solving the integral, (A4.2.1) reduces to ( )2(3 2 3 2 1, 30 ( )3 7 ( ) ) P L q q q d q q d q c diss C q q d s d dt d s dt s c d s q d q d q q d dt d dt s s = − + + + + (A4.2.2) where , , , q q d q d q d s dt d dt s are defined in the List of Symbols. Substituting the values of qd ,qs , d qd , d qs dt dt in terms of ' ' v s and d v s dt as given in (3.14), (3.15), (3.18) and (3.19) into (A4.2.2) gives ( )(3 2 3 2 1, 30( )3 7 ( ) ) coxL d d Pc diss vds vgst vgdt v gdt vgdt v gst vgst v v dt dt gdt gst v d v d v v gdt dt gdt dt gst gst = − + + + + (A4.2.3) In pinchoff saturation region, as qd 0 = equation (A4.2.3) reduces to 1, 10 coxL d Pc diss vds vgst dt = (A4.2.4) and in cutoff, the first order dissipative power becomes Pc1,diss 0 = A4.3 FIRST ORDER CONSERVED POWER The first order channel conserved power is given in (4.16) by ~81~ 1, [ 0( 1)] 0 L d Pc cons vcb ic dx dx = ∫ (A4.3.1) where ic1is the first order channel current and vcb0 is the zero order channel potential. Integrating, equation (A4.3.1) expands to 1, [ 3( ) 6 4( ( 2 ) (2 ))( ) ] ( )2 coxL d d Pc cons vgdt vgdt vgst vgst K dt dt v d v v v v d v v v v gdt dt gdt gdt gst gst dt gst gdt gst gbt vgdt vgst = − − + + + + + + (A4.3.2) In pinchoff saturation, with qd 0 = , equation (A4.3.3) reduces to 1, ( 3 ) 6 coxL d Pc cons vgst vdb vsb dt = − + (A4.3.3) and in cutoff, it becomes Pc1,cons 0 = A4.4 Energy function validation for the gate Clairaut’s theorem states that, “If two second order partials are continuous, their derivatives will be equal”. The same theorem can be used to check the equality of second order partial and verify the existence of an energy function for the conserved power. Using equation (4.18), the conserved first order gate power is given by (3( 1) ( )2 1, 1 3 ( )2 2 ( 2 ) 2 (2 ) ) coxL d Pg cons ig vgb vgb K vgb vgdt vgst K v v dt gdt gst v d v v v v v v d v gdt dt gdt gdt gst gst gdt gst dt gst = = − + + + + + + (A4.4.1) In terms of energy, the conserved power can be written as ~82~ 1, E dv Eg dvgb Eg dv Eg dv P db sb g cons v dt v dt v dt v dt gb db sb ∂ ∂ ∂ ∂ = = + + ∂ ∂ ∂ ∂ (A4.4.2) Comparing (A4.4.1) and (A4.4.2), the derivatives of the gate energy with respect to voltages give 2 (2 ) 3( )2 Eg coxLvgbtvgst vgdt vgst vsb v v gdt gst ∂ − + = ∂ + (A4.4.3) 2 ( 2 ) 3( )2 Eg coxLvgbtvgdt vgdt vgst vdb v v gdt gst ∂ − + = ∂ + (A4.4.2) 2( )2 1 (6 ) 6 ( )2 Eg vgdt vgst coxLvgbt vgb K v v gdt gst ∂ − = − ∂ + (A4.4.3) As mentioned earlier, an energy function exists if and only if the second order partials of (A4.4.3) (A4.4.5) are equal. Comparing (A4.4.3)(A4.4.5) ( ) ( ) Eg Eg vsb vgb vgb vsb ∂ ∂ ∂ ∂ ≠ ∂ ∂ ∂ ∂ ( ) ( ) Eg Eg vdb vgb vgb vdb ∂ ∂ ∂ ∂ ≠ ∂ ∂ ∂ ∂ It is found that the pa 



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