Transcript 
QUARTZ PRESSURE TRANSDUCER
SYSTEM IMPLEMENTED
USING SOl
By
IRA SHANKAR
Bachelor of Engineering
Dr. B.A.M University
Maharashtra
India
2000
Submitted to the Faculty of the
Graduate College of the
Oklahoma State University
in partial fulfillment of
the requirements for
the Degree of
MASTER OF SCIENCE
December, 2003
QUARTZ PRESSURE TRANSDUCER
SYSTEM IMPLEMENTED
US~NG SOl·
Thesis Approved:
// , Thesis Adviser
ean of the Graduate College
11
ACKNOWLEDGMENTS
I wish to express my sincere appreciation to my research advisor, Dr.
Chriswell G. Hutchens and Mr. Steven A. Morris for their intelligent supervision,
constructive guidance, inspiration and friiendship. Their inspiring insight guided
me through my study and provided me with a valuable experience and
knowl,edge. My sincere apprec:iation extends to my committee members Dr. L.G.
Johnson and Dr. G. Scheets.
I am thankful to all my colleagues in the Mixed Signal Very Large Scale
Integration (MSVLSI) Design Laboratory for assisting and helping me on
numerous occasions. I would like to thank all my close friends for their love,
encouragement and support during the period of my studies. I sincerely thank
Dr. H. Schultz and Halliburton Inc., for providing financial support to this project
and excellent work experience.
I would like to give my special thanks to my family for their patience and
support. I like to thank my parents who have provided me with support and
encouragement through their prayers and love.
Finally, I would like to thank the Department of Electrical and Computer
Engineering for providing me this opportunity to conduct valuable research.
m
TABLE OF CONTENTS
CHAPTEH
1. INTRODUCTION
2. QUARTZ PRESSURE TRANSDUCER SYSTEM
2.1 Review of Previous Architecture
2.2 OPT Architecture
2.3 OPT Architectu re Function
2.4 Limiter Error
2.4.1 Limiter induced phase jitter
2.4.2 Relationship between timing jitter and phase noise
3. CHARACTERIZING THE DIGITAL MIXER
3.1 MSD as a phase detector
3.2 Metastability
3.3 Latch and Mixer implementation example
3.4 Input Phase Jitter Model
3.5 Error in OPT measurement system
3.6 Previously discussed phase detector architectures
3.6.1 Hogge Phase Detector
3.6.2 Alexander Phase Detector
4. aUARTZ PRESSURE TRANSDUCER SYSTEM
4.. 1 OPT measurement system
4.2 Digital Mixer
lV
PAGE
1
8
9
13
18
24
24
27
30
31
34
40
46
50
51
52
54
56
57
63
4.3 aPT control system 64
4.4 FREF control circuit 66
5. CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK 69
References 72
LIST OF TABLES
TABLE
I. Operational Parameter
II. Latch Dev!ice Sizes
v
PAGE
17
42
LIST OF FIGURES
FIGURES
1.1 Block Diagram of Proposed Architecture
1.2 Overvi'ew of thesis
2.1 Block Diagram of existing OPT Measurement System
2.2 Block Diagram of the OPT architecture
2.3 Count Uncertainty
2.4 Floor Plan of OPT architecture
2.5 System Timing Diagram
2.6 Equivalent Noise model
3.1 (a) D latch as a phase frequency detector
3.1 (b) Response to unequal input frequencies
3.2 Input/output characteristic of Mixer
3.3 Misclock generated due to input phase jitter
3.4(a) DLatch
3A(b) Equilibrium points in crosscoupled inverters
3.5 Input triggering that might cause Metastability
3.6 Typical shape of tr versus S Metastability Window
3.7 Probability of miscount g~ven a metastable event
3.8 Latch Implementation
3.9 Di'gital Mixer Implementation
3.10 Finitestate diagram of Mixer operation
3.11 Bench Study setup for phase jitter analysi's
VI
PAGE
4
7
10
14
15
16
18
28
31
31
32
33
34
34
35
37
39
41
42
43
48
3.12 FDIFF versus misclock rate (M) using HCMOS components 49
3.13 Hogge Phase Detector 52
3.14 Alexander Phase Detector 54
4.1 aPT building blocks
4.2 aPT measurement system schematic
4.3 aPT simulation results
4.4 aPT test results
4.5 Digital Mixer schematic
4.6 Mixer test results at 180°C
4.7 Schematic of aPT Control circuit
4.8 Test Results of OPT Control Circuit
4.9 Schematic figure of the FREF counter control circuit
4.10 FREF counter control circuit results
Vll
57
59
60
62
63
64
65
66
67
67
sal
TSM
OPT
PFD
CDR
FP
FREF
FDIFF
UTSi
MSD
MER
(t)
<.00
MTBF
SOC
Cdlb
Cgs
gm
NOMENCLATLJRE
Silicon on Insulator
Thickness Shear Mode
. Quartz Pressure Transducer
Phase Frequency Detector
Clock and Data Recovery
Pressure Frequency
Reference Frequency
Difference Frequency
UltraThin Silicon on Insulator
Master Slave D Flip flop
Metastability Error Rate
Timing Jitter
Resolution time constant
Phase noise
Nominal Frequency
Mean Time Between Failures
System on Chip
Drain to Body Capacitance of the Transistor
Gate to Source Capacitance of the Transistor
Transistor tranconductance
viii
CHAPTER 1
INTRODUCTION
Sauerbrey's observations about the mass sensitivity of AT cut quartz
crystals in 1959' L11 led to the quartzcrystal microbalance's applicati~m as sensor for a wide array of applications ranging from vacuum deposition monitors
and gas phase sensors to applications lin the fiel'd of electrochemistry. Sensor
applications today include temperature, pressure, force, acceleration, fluid
density, and thin film thickness monitors. Quartz pressure resonators that are
routinely used for hydrocarbon reservoir modeling (a.k.a. downhole sensors) are
the commercially most successful family of quartz resonator sensors and form
the core of this thesis.
Two kinds of high precision pressure and temperature sensors are
currently being used by the petroleum industry: a thicknessshear resonator or vibrating quartz beam. The industry mostly uses SCcut quartz crystals vibrating
in thickness shear model [2], [3].. A thickness shear mode resonator consists of plate (often circUilar) of crystalline quartz wlith thinfilm metal electrodes deposited
on the faces. The thiclknessshear mode (TSM) quartz sensor is based upon the
wellknown forcefrequency effect of precision qualrtz resonators: if force exerte,d upon the circumference of a quartz resonator, ilts frequency will shift proportion to the applied force. A thicknessshear resonator frequency changes
1
as a function of biasing stresses and temperature gradients in the vibrating
element.
High accuracy, resolution and fast response of this sensor enabl:e reliable estimate of formabon stability and oi Iwater :interfaces in reservoirs that
help reduce the overall cost of oil and gas production. The need is to extend the
commercially available quartz resonator systems to operate for extended periods
of time (lifetimes of 1020 years) at temperatures of around 200 degrees Celsius.
Further the quartz sensor and the associated electronics that process,es the
output from the crystal oscilllator sensor suffer from problems outlined below:
1. Dependence on ancillary physical property [3]: The sensor can be sensitive
not only to the primary or desired characteristic, but also to some other ancillary
characteristic that coexists with the primary characteristic. For instance, pressure sensor such as the one currently in use by the petroleum industry may
have a response, which is affected not only by pressure but also by temperature variation.
2. Aging [7], [8]: The frequency changes with time systematically due to internal
changes in the oscillator even when factors external to the oscillator
(environment, power supply, etc.) are kept constant. The effect of this aging observed as a drift in the frequency in the application that inturn degrades the
longt,erm accuracy and pe:rformance characteristics of the resonator system,
thereby setting an upper limit on the life of the sensor.
3. Noise: Stochastic (random) processes establish the performance limitations
of both OCMs and Crystal osc:illators. Except for vibration, the shortterm
2
instabilities almost always result from noise. NoiiSe limits the ability to determine
the current state and the predictabUity of precision resonators [4], [7],. [8]. Noise the postsensor processing: electronics has been shown to degrade the accuracy
of the resonator system by three orders of magnitude [4]; [7[, [8].
4. Thermal Hysteresis: An ideal crystal resonator frequency versus temperature
characteristic is a single value function and frequency can then be uniquely
known by knowing the temperature [7], [8]. But actuailly the frequencies versus
temperature characteristics of quartz resonators do not repeat exactly upon
thermal cycling. The mechanisms that cause hysteresis linclude: changes stresses on the resonator plate which may be caused due to temperature cycling;
changes in the quartz; contamination redistribution; oscillator circuitry hysteresis
etc. [4], [7], [8].
5. Modeling: Since quartz ils piezoelectric, a voltage appHed to the electrodes
causes the quartz plate to deform slilghtly. The amount of deformation due to an
alternating voltage depends on how close the frequency of the applied voltage to a natural mechanical r,esonance of the c1rystal [7]., [8]. To describe the
behavior of a resonator, the differential equations for Newton's laws of motion for
a continuum, and for Maxwell's equations, must be sOilved with the proper
electrical and mechanical boundary conditions at the plate surfaces [7), [8].
Nearly alltheoretical works have used approximabons. These approximations,
although small, are the source of some of the important instabilities of crystal
resonators; such as the acceleration sensitivity, the thermaltransient effect, and
the amplitudlefrequencyeffect [7]., [8]. Also the post processing electronics
3
comprises of bulky analog mixers that are difficult to model accurately at elevated
temperatu res.
This thesis proposes alternate system architecture (Fig. 1.1) that greatly
reduces the size of e~ectronics, allows greater temperature range and eliminates
some of the sources of errors outlined above. This thesis work discusses only
the portion that is outlined in Fig. 1.1 below.
FREF La,tch1
Reference
oscillator
• u ·•.•••"'.· U' u' ,•• u ... : :
~ ~ ..." ! Mixer FDIFF NA"F
Measurement : NAVG counter .!: •
oscillator Latch
NRE~
~
Unknown Frequency
j •
FREF counter I:::: Reference Frequency
................................................................................................................................................
Fig. 1.1 Block Diagram of Proposed Architecture (outlined portion is covered
in thils thesis)
4
This novel alldigital lowpower fully integrable Quartz Pressure Transducer
(OPT) is to be implemented using Peregrine's 0.5 micron SiliconanInsulator
(SOl) (UTSi®) process. The key design goals in developing the OPT system are:
• Low Phase Noise (accuracy of 0.06 ppm at 200 degree Celsius)
• Low Power Consumption « 1mW)
• Reduced Size «2 mm square in area)
• Manufacturability and Consistency
• Low cost
• 510 year life at 200 degree Celsius
• 24 Bits of accuracy
The QPT uses a temperature sensor to sense the temperature and with the
help of a calibration polynomial, corrects for the effect of change in pressure due
to temperature. The low phase noise of the QPT electronics insures high
accuracy as weill decreases the shortterm instabilities in the system. The
system is implemented using Sal, hence extending the operational temperature
range and the life of the system at elevated temperatures [15]. This alldigital
circuit eliminates the need of an analog mixer and bulky, temperature sensitive
low pass filter components, thereby making the circuit much more robust to
environmental effects of temperature and aging. In addition modeling of the
device behavior much simpler.
Figure 1.2, outlines the organization of the thesis. This chapter outlines some
of the errors associated with current stateoftheart downhole sensor systems
thus explaining the need for a high temperature, low power robust downhole OPT
5
system. In chapter 2, the proposed OPT system architecture is presented and
compared to the existing architectures. The basic measurement equation of the
system is derived and two of the errors in the measurement system are modeled.
In chapter 3,. a di9'ital mixer circuit that forms the core of the OPT system is
presented. This chapter will focus on modeling and analysis of the metastable
behavior and measurement inaccuracy caused by input phase jitter of the digital
mixer. This chapter will present a composite error mode for the OPT system.
This circuit may also be used as a phase frequency detector (PFD) in clock and
data recovery (CDR) circuits. Finally., some previously published techniques
such as HOglge detector and Alexander detector are discussed briefly and
compared with the digital mixer architecture.
Chapter 4 describes the performance of the OPT system. Finally, chapter discusses the accomplishments of this work and makes suggestions for future
research.
6
1. Current stateoftheart pressure sensor systems and
what ails them.
1
2.2 OPT System Architecture
1
2.3 QPT Architecture Function
and sources of error
1
2.4 Limiter
induced error
!
1
3.0 Digital Mixer
1
3.3 Metastability
3.4 Phase jitter
!

3.5 Error in the OPT system
1
4.0 Implementation and Results of OPT
1
5.0 Conclusions and Suggestions for future work
Fig. 1.2 Overview of thesis
7

CHAPTER 2
QUARTZ PRESSURE TRANSDUCER SYSTEM
This chapter describes the architecture, operation and performance of a
high accuracy monolithic quartz pressure transducer (OPT) system. The OPT
architecture is based on the wellknown period measurement method [16] for
highresolution frequency measurement. However, this design represents significant advancement over the current stateofart desigrl" "In terms of power
dissipation, size, operational temperature, stability and accuracy. The current
stateoftheart sensors allow for an accuracy of +/ 0.1 ppm and are deployable
at temperatures up to 175 degree Celsius. Accuracies of 0.06 ppm (224
) at 200
degrees Celsius willi be demonstrated using the proposed OPT system in
Chapter 4.. The system is implemented using Peregrine Semiconductor's 0.5
micron UltraThin SilicononInsulator process, UTSi® [30], which potentially
allows the extension of the operational temperature range of the OPT up to 250
degrees Celsius [15].
A unique feature of this design is that it is an aUdigital solution eliminating
the need for bulky temperaturesensitive analog mixer and filter components.
Monolithic VLSI impl,ementation greatly reduces size and ensures higher
accuracy.
8

2.1 Review of Previous Architecture
The existing quartz resonator based pressure transducer system in use by
the petro1leum industry is based on a system originally developed by HewletlPackard
191, (101, [11]. In this system a thickness shear mode quartz resonator is
secured in a hollow cylindrical housing. Pressures exerted on the cylinder cause
shifts in the resonant frequency ot the resonator. The difference between the
resonator frequency and a reference frequency is proportional to pressure and
can be converted to a pressure measurement.
The welllogging industry typically applies their version of this sensor to
shut in testing of oil wells. This type of test measur,es the pressure buildup in an
oil reservoir after the well is dosed off. The measured data is a time varying
pressure transient and dictates the use of a pressure sensor with faster response
time and greater accuracy at high temperatures than is possible with the original
Hewlett Package design.
The current industrial sensor design improves upon the original HewlettPackard
design by the incorporation of a temperature sensitive resonator and a
reference resonator in the sensor cylinder. The sensor itself is smaller than the
HewlettPackage design, giving a faster thermal response time. A block diagram
of this system is shown in Figure 2.1. A calibration polynomial, derived from
measurements of known pressures as a function of temperature, is used to
correct the measurement as a function of temperature. The temperature and
reference resonators are designed to have temperature transient response times
that mimic the temperature response time of the pressure sensitive resonator.
9
This allows temperature corr·ections to be made during thennal transients, thus
speeding the response time of the system.
The difference between the pressure dependent :resonator frequency (FP)
and a referenoe frequency (FREF) is proportional to pressure and is converted to
a pressure measurement.
O,scillator .:::::::I Pressure
~ CrySIa!
Mixer
t.i+
OscilJalOr
t=ll Reference
~ Crystal
Oscillator f ~~
1::::1 Temperature Mlxer
~ CryslOJ
Gale To 
Fig. 2.1. Block Diagram of existing Quartz Resonator based Pressure
Measurement System.
The electronics associated with the measurement system consists of
oscillator circuits, mixers and digital counting circuitry. Using the reference
resonator, the reference oscillator generates a signal at about 7 MHz and is used
as the frequency standard for the device. Referring to Figure 2.1, signals from
the pressure resonator oscillator are mixed with the reference oscillator to obtain
a baseband frequency of 6 to 30 kHz. This corresponds to a pressure range
10

from 0 to 20,000 psi. The oscillator signal from the temperature resonator is
mixed with the reference frequency to obtain a baseband from 6 to 30 kHz.
Digital logic is used to count the baseband temperature and pressure
frequencies. These counts are offloaded by a downhole microcomputer. The
data is processed, by transforming it with a calibration polynomial. The
resolution of the system can be changed, by increasing the gate time of the
counter circuit at the cost of increasing the measurement acquisition time.
Resoi1ution specifications of the current system have not been disclosed but are
believed to be similar to a system by Ouartzdyne with claims of a resolution of
.01% of fullscale [13]. The fundamental accuracy and resolution of the HP
based system are limited by the following error sources:
• Thermal noise of the pressure·sensor (a function of the sensor mass)
• Thermal noise in the oscillator transistors
• Limits to counter gate time imposed by the required time response of the
system.
• Uncorrectable sensor nonlinearities
The temperature rating of the current industrial quartz resonator based
pressure sensor is 175 degrees Celsius. The aim of this design was primarily to
extend the operational temperature range of the current stateofart to 200
degree Celsius while maintaining the system's measurement accuracy. The
OPT design presented in this thesis is unique in its genre by virtue of it being an
aliidigital solution implemented as a monolithic VILSI SystemonChip (SOC).
This design improves and builds upon previous designs through a combination of
11

optimum choice of architecture for the circuit while incorporating good design
techniques.
The drift of bulk device parameters with temperature significantly affects
the correct operation of both digital and anal!og integrated circuits in terms of
standby power dissipation, speed, precision and eventually results in complete
loss of functionality or even destruction of the circuit by thermally induced fatchup
[15]. The OPT presented here is to be implemented using a SilicononInsulator
(SOl) process because SOl offers several potential advantages for
implementation of high temperature circuits, some of which are enumerated
below ["17]:
• Full dielectric isolation allows for easy isolation of devices at low frequencies
implying a total suppression of latchup, and also higher integration density.
• Reduced Parasitic Capacitances  implies unsurpassed low power
periormance. Virtual elimination of Cdb (draintobody capacitance) results in
reduced power (CV 2 f) and tdelay (faster).
• Lower leakage currents  resulting in lower standby power.
• High temperatur,e operation up to 250°C.
Lower leakage currents and reduced parasitics lead to a higher yield
enabling us to improve upon the reliability and lifetime of the device at elevated
temperatures [15]
12

2.2 aPT Architecture
The architecture of our frequency measurement method is based on the
period measurement method [16] for highresolution frequency measurement.
The c'rcuit topography is similar to the quartz crystal microbalance circuit of
Bruckenstein and Shay [18]. Their method uses a D flipflop mixer to convert the
unknown frequency to low frequency, followed by direct counting of the low
frequency signal. We improve upon the architecture of Bruckenstein and Shay
[18] by using cascaded MasterSlave D flipflops in order to reduce the effect of
misclocking due to phase noise and metastability, as described in Chapter 3. In
a later rendition of the same circuit, Bruckenstein et al. replace the D flipflop
based mixer with an analog mixer stating functionality and improved accuracy as
r,easons for the change [19'].
However, the flip flop based architecture has the following advanta9'es over its
analog mixer counterpart:
• Elimination of bulky filter circuitry.
• Elimination of mixer and additional limiter circuits.
• Fully digital design, allowing implementation in customized SOl circuitry.
• Implementation in SOl potentially allows the extending of operational
temperature range of the aPT to temperatures in excess of 250 degrees
Celsius [15], [17].
• Reduced power consumption and volume.
The architecture of the frequency measurement system, Fig. 2.2, consists of
five major components: (1) a crystal oscillator circuit which generates a
13
temperature compensated reference frequency, FREF; (2) limiter circuits that
convert oscil~lator sinusoids into logic Jevel clock signals; (3) a digital mixer that
produces a difference signal, FDIFF, from the reference frequency, FREF and
the unknown (measured) frequency, FP; (4) the period averaging circuit, NAVG
counter latch and (5) the measurement interval counter and latch, Latch1 and
FREF counter. This thesis covers all the circuits shown in Fig,. 2.2 barring the
oscillators.
Fig. 2.2 Block Diagram of the QPT architecture.
Beginning at the leading edge of a period of the FREF signal, NAVG
FREF Latch1
Reference
oscillator
t., •.·, .•• ' " ..OI " , .. U." ~.·,.~,· ~ , .. f1<~, ,••• , , (o ~ ~ ~ " ••• ,'~~ ~
~ £ ; ~ ... ! Mixer NAVG !
~ ~
Measurement i FDIFF NAVG counter • !
oscillator , Latch!
~ i
'"""""'T' I I"~"~
!
Unknown Frequency .1
! I NREF !
1+. !
i!!~
~ FREF counter i
Reference Frequenj I
. ,
; , ; " " , _ ", " , i
counter latch counts NAVG; the number of difference frequency periods, that
occur during the time it takes to accumulate 2N counts of FREF in the FREF
counter. Latch1 holds the remainder in FREF counts from 2N that occur between
14
L

the time of the final fallingedge of the FDIFF period and FREF counter ove.rflow,
referred to as NREF.
The circui1 measures the unknown frequency (FP) by measuring the time
period and taking the inverse. However, by virtue of the chosen architecture, a
plus or minus one count inaccuracy is inherent to the OPT (Fig. 2.3). Hence, we
average over a large number of periods to measure the unknown frequency with
24 bits of accuracy.
FDIFF
COUNT
Fig. 2.3 Count Uncertainty
Whenever there is a phase transition there will be a change in the output
of the mixer. Now, because of the uncertainty or jitter in the edges of the input
signals, as a result of noisy oscillators, false clocks will be generated.
A false clock may also be generated as a result of the jitter induced by the
thermal noise of the limiters and the mixer also contributes to the fundamental
intrinsic error of the OPT. We modeled the occurrence of a false clock to predict
the error introduced by it and explain how it affects the measurement accuracy of
15
the OPT. An inhibit circuit that prevents a misclock for the clock cycle
immediately following a phase crossing was added. Circuitry has been added to
the flipflop circuit to eliminate undefined metastable clocking and eliminate false
clocking from clock jlitter. The mixer is discussed in more detail in Chapter 3.
Fi'g. 2.4 shows the fIIoor plan of the SOl design.
16 Bit NAVG
Counter
/
24 Bit NREF
counter
Mixer and control
circuitry
Pad
drivers
Fig 2.4 Floor Plan of OPT architecture
The 350micrometer square OPT implemented in SOl has the following operating
parameters:
16
TABLE I. OPERATIONAL PARAMETERS
REFERENCE SIGNAL (FREF) 7 MHz
INPUT SIGNAL FREQ. (FP) 7.006MHz7.030MHz
RANGE
DIFFERENCE FREQUENCY 6KHz30KHz
{FDIFF) RANGE
PROCESS USED PEREGRINE'S 0.5/1
UTSi® PROCESS
UPPER OPERATIONAL 180°C
TEMPERATURE LIMIT
DIE SIZE 350ltm2
NUMBER OF LOGIC GATES 2172
In order to precisely predict the accuracy of the OPT system it is essential
to model the inaccuracies of the system introduced by the various components of
the OPT architecture. There ar,e three basic sources of error in the OPT system,
namely:
1. Architecture error
2. Input limiter induced phase jitter
3. Misclock generated due to
a. Metastability in OPT mixer
b. Thermal noise in OPT mixer
The next section models the fundamental measurement error inherent to
the OPT by virtue of its design and count,er architecture (architecture error). The
jitter induced by the limiters further affects the measurement accuracy and will be
modeled in Section 2.4. The OPT mixer is susceptible to miscount errors as we,u
as misclocks due to metastability and thermal noise induced phase jitter. This
17
error is modeled in Section 3.3. Section 3.5 summarizes all the errors (1 through
3, above) inherent to the OPT system and presents the actual error in the QPT
measurement system.
2.3 OPT ARCHITECTURE FUNCTION
The QPT circuit measures frequency by measuring the time period and
taking the inverse. In order to maintain approximately N (24) bits of accuracy in
the measured frequency we accumulate 2N counts (where N is the depth of the
counter) of the measured frequency. However, there is a plus/minus onecount
uncertainty (COUNT) in these 2N counts accumulated as shown in Fig. 2.3. In
general the measurement period can be expressed as
2N +COUNT
accurate measured_ frequency (1 )
•

This COUNT error is not accumulated or corrected for by the QPT measurement
system and is the basic architectural error of the system.
Fig. 2.5. System Timing Diagram
In Fig. 2.5 above, FDIFF is defined as the baseband frequency to be measured.
NAVG is the number of FDIFF periods that occur in the time it takes to
18
accumulate approximatelly 2N counts in the FREF counter. The time taken by the
FREF counter to accumulate 2N counts is the measurement period of the system,
henceforth referred to as Tmeas. Tmeas is an integral number of periods of FHEF,
and can be calculated from:
2N
~,eas =
FREF (2)
Equation (2) represents the actual measurement time period of the OPT
system while (1) is the accurate measurement time period including the
FDIFF referred to as NAVG. The measured frequency can now be written as:
plus/minus one count uncertainty in the measurement. Latch1 holds the
The measurement interval extends over an integral number of periods of
(3)
(4)
NREF  Latch 1
T,npoJ =
FREF
NA.VG
Jmeils = T
meas
edge of the FDIFF period and FREF counter (NREF) overflow. Thus, (NRIEFLatch1
)",,2N is the largest number of integral periods of FREF in the period Tmeas.
remainder in FREF counts from 2N that occur between the time of the final falling
Expressing, Tmeas in terms of NREF, Latch1 and FREF, we get:
Substituting (3) into (4) gives:
NAVG·FREF
f."eas = NREF  LatchI (5)
Equation 5 is the measurement equation of the OPT system. COUNT is not
included in the above equation since it is not measured by the system but is the
19
inaccuracy .in the frequency measured (fmeas). It is important at this point to make
the distinction between FDIFF, the frequency being measured and fmeas, the
measured frequency. Revisiting Fig. 1.1, FDIFF is the output of the mixer,
whereas fmeas is the output of the measurement system, computed from the
counts downloaded from the NAVG, NREF and Latch1 counters/latch, using
equation (5).
Now, TmeaS_ClJccurate may also be defined in terms of NAVG and is expressed as:
number of bits in the FREF counter. Thus, from equations (1), (2), (3) and (6),
The system is designed so that NAVG counter is larger the largest number
of integral cycles of FDIFF that will fit into 2N cycles of FREF, where N is the
Rearranging, equation (8) we get:
(9)
(8)
(6)
(7)
NAVG
FDIFF
2N  Latch! ± COUNT
FREF
NAVG
FDIFF
accurate
rneas _ accurate
FDIFF = NA VG . FREF
(2 N _ Latchl). [I± COUNT ]
2N Latchl
FDIFF = NAVG . FREF
2N
 Latchl ±COUNT
T
Now, using (7), FDIFF can be expressed as:
Noting the approximation,
1
:::::la
l+a
(10)

20
Equation (9) can be rewritten as:
FDIFF = NAVG· FREF [1 ± COUNT ]'
(211'  Latch!) 2'"  Latchl
Using (5), rewriting (11) in terms of fmeas, we 9'et:
[
COUNT ]
FDIFF =fmeas' 1±
2N Latch)
(11)
{12)
The relative measurement error (ERROR) is defined as the error in the
measumd frequency relative to the true value of the frequency being measured
[20]. Thus, the measurement error is:
FDIFF f
ERROR = meas
FDIFF
Substituting (12) into (13), and applying: the approximation (10), gives:
ERROR=± COUNT
2N  Latchl
(13)
(14)
We have yet to show proof of our claim of 24 bits of accuracy. This subsection
demonstrates proof of 0.06ppm accuracy in the measured frequency. Also, the
method for selecting the number of bits accumulated in the NREF counter, the
NAVG counter and Latch1 is presented.
By way of introduction, a counter running at a 10 MHz frequency counts 10
million pulses in a second, giving an accuracy of 0.1 ppm. If we were to count for
10 seconds, the accuracy achlieved woul1d be 0.01 ppm. Hence by increasing the
measurement time period we can theoretically get infinite accuracy.
21
The desired accuracy in our case is 224 (0.06 ppm) at a center frequency of 7
MHz. The measurement time interval, given by (2) was chosen to get the
desired accuracy. Rearranging (2), we g,et the equation for calculating the
number of bits to be stored lin the NREF counter,
2N ~ FREF
Tmeas (15)
From (15), it can be shown that for a measurement time interval (Tmeas) of
2.40 second, the accuracy of 24 bits (0.06 ppm) is readily achieved. Now,
revisiting the measurement system architecture, it calls for a 16bit counter for
the NAVG counter and that only 10 lSB of the 24 bits of the NREF counter are
stored in Latch1. The difference frequency being measured, FDIFF ranges from
6 KHz to 30 KHz (FDIFFmin to FDIFFmax). The worst condition occurs during the
FREF, where N is the number of bits in the FREF counter. Thus, from equations
measurement of FDIFFmax. As a reminder, the system is designed so that NAVG
is the largest number of integral cyclles of FDI FF that will fit into 2N cycles of
(2) and (7), NAVG can be expressed as:
NAve = INT((2
N
 Latch1)FDIFF J"'" INT(2
N
)FDIFFmax J
FREF FREF
(16)
Latch1 holds the remainder in FIREF counts (or residual) from 224 that occur
between the time of the final fallingedge of the FDIFF period and NREF counter
overflow. The remainder hetwe,en the two frequencies, FREF and FP, will be
worst case or largest when the two frequencies are closest to each other, i.e., at
22
FDIFFmin. Thus the maximum number of bits required by Latch1 to avoid loss of
information can be written as:
(
FREF J Latch1 . = 10
max_bus g2 FDIFF.
.. nun
{17)
More specifically, for FDllFFmin equal to 6 KHz, 10 LSB of NREF counter must be
saved in Latch1. Equati,on (17) glives the maximum residual number of bits
Thus from (18), it is obvious that the residual between the counts generated by
comparison to the count stored in NREF. The number of counts generated in
stored in Latch1. Practically, the residual would be extremely small in
Counts = [NT (Tmeas * f) (18)
Tmeas by an N bit counter clocked at a frequency, f, is given by:
th,e NREF counter and NAVG counter would be a very small number as
compared to NREF counts (four orders of magnitude lesser).
As a verification example, substituting, 30 KHz for FDIFFmax, 7 MHz for FREF,
N=24, ignoring contents of Latch1, and taking the log2 of both sides of equation
(17), gives the desired number of bits for NAVG as 16. Substituting FDIFFmin in
(17) calls for the NAVG counter length of 14 bits. A 16bit counter was chosen
for the NAVG counter.
Revisiting the error equation given by (14):
ERROR =± COUNT
2N  Latchl (14)
Substituting, COUNT=1, N=24 and ignoring the contents of Latch1, for reasons
given above, the measurement error in the OPT system is given by:
23
1
ERROR=+N2
(19)
The bits downloaded from the NAVG counter and Latch1 are combined
together to calculate the measured frequency to 24 bits of accuracy, which is
preserved by the measurement time interval, fixed by the 24bit FREF counter.
This completes our design of the OPT architecture, the measurement
equation derivation and the basic architectural inaccuracy of the system. As
mentioned earlier, in addition to the fundamental measurement error,. the thermal
noise in the limiters and mixer can further reduce the accuracy of the OPT.
In the next section, we enhance the measurement error equation by
accounting for the contribution of the thermal noise of the limiters. We discuss
our choice of the limiter based on thermal noise in Section 2.4
2.4 LIMITER ERROR
2.4.1 Limiter Induced Jitter
The limiter takes the incoming analog signal that varied from Vdd to
+Vdd and maps it into the two discrete values +Vdd and Vdd. The device can
be thought of as a single bit analogtodigital converter with an extremely fast
sampling rate. Hence, it is essentially a slope amplifier. The purpose of the
IIimiter is to greatly increase the slope of a signal as it approaches a threshold.
Slope amplification adds noise to the signal. The source of this noise is the
intrinsic thermal noise of the amplifier [21]. This noise is added to the si·gnal,
during the process of ampllification and causes random Uuctuations in the half
24
level crossing of the slope amplifier's output. These fluctuations are called jitter.
Timing jitter (Tjitter) or jitter will be defined to be the difference between the
output's half level crossing time and its mean value. Jitter is typically a function
of the gain and bandwidth at the amplifier (21].
In the QPT system (Fig. 2.2), there is jitter induced in the edges of the
signals FP and FREF and it is introduced by the finite gain and bandwi,dth of the
limiter circuits that convert oscillator sinusoids into logic level dock signals.
If jitter is measured at the zero crossings, then a noise source superimposed on
the input signal will cause a change in the timing equal to the noise vol1tage
multiplied by the slope of the waveform at that point Le.,
Hence the timing jitter {Tjitter} component is given by:
(20)
(21 )
where V"oise is the thermal noise of the system [22] and d%r is the slew rate of
the edge transition. This jitter is random (Le., unpredictable) as it is caused by
thermal noise and thus is expressed by a gaussian probability density function.
Since the jitter induced by the input limiters may cause the mixer to
misclock (Section 3.2), we chose the limiters to be four times wider (reduce the
thermal noise by a factor of two) than the transistors in the mixer. A detailed
analysis of the effect of limiterinduoed jitter is done in Chapter 3.
25
We will now account for the effect of Tjitter on the measurement accuracy of
the OPT system.
Now, accounting for the thermal noise in the input limiters, we can solve error due to Tjitter. We modify (4) to show the uncertainty of Tmeas caused by T jitter (f meas  r NAVG ]
 T ±.J2*T.
meas J (22)
The random jitter from the two limiters are added in (22) as root mean squares. (2) into (22) gives:
f meas
2N
T =meas
FREF
I FDIFF * T meas J tT + ~2*T
meas  V L J (23)
(2)
•
Substituting (23) into (19) and again using approximation (10) gives
+Tj ERROR(Tjitter) = T
l1Ieas
Using (2) we can express (24) as
+Tj *FREF
ERROR(Tjirter) ::::: 2N
(24)
(25)
This is the error caused as a result of the thermal noise in the input limiters. We
have now covered the two sources of error, architecture error, given by (19} and
timing jitter error that takes effect due to thermal noise in the limiters (25).
26
The third and final source of error is the inherent to the dilgital mixermetastability
and phase jitter due to thermal noise in the mixer. In order to get a
composite error model of the OPT measurement system, we need to establish
the relationship between phase noise and timing jitter. The next section deals
with just that.
2.4.2 Relationship between timing jitter (Tjitter) and phase noise:
Jitter is defined as shortterm noncumulative variations of the significant
instants of a digital signal from their ideal positions in time. Timing jitter (Tjitter) is
a measure of the deviation of each signal edge timing from its ideal position in
time domain and phase noise defines the same deviation in frequency domain
[12]. Thus, depending on the jitter problem one of the following two methods
maybe used to model jitter:
1. Equivalent noise voltage model: considers a pure signal with an added
noise voltage.
2. Phase noise model: considers a pure signal that has its phase
modulated by a noise source.
27
noise voltage
distribution
, dv ~v
SlewRate =  :::: hining
jitter dt At
di stributiOll
+ill ..  }liter
I
As can be seen from Fig. 2.6, a Iiloise voltage imposed on an ideal clock
Phase noise is how far the phase of a signal at a given time varies from what it is
edge causes the time shift of the clock edge via the slew rate of the edge
supposed to be. Consider an ideal sinusoid with its phase modulated by a phase
(26)
Fig. 2.6 Equivalent noise Voltage Model [32]
x(t) =A(t)cos(av + cp(t»
noise «p(t)).
transition [32]. The timing jitter thus modeled is given by (21).
•
where
Fig. 3.2 Input/output characteristic
The MSD latch is called a "bangbang" phase detector to emphasize the
fact that the average value of the output (FDIFF) jumps from railtorail as L1$
varies from below zero to slightly greater than zero degrees. [22]
In the unlikely event of noisefree signals, the single masterslave 0 latch
(as shown in Fig. 3.1 (a)) would be sufficient to find the difference between two
unequal frequencies applied to its inputs. However, as shown in Fig. 3.3, input
phase jitter in the signals causes a misclock.
32
FDIFF ,' I I
PHASE CROSSING MISCLOCK
Fig. 3.3 Misclock g'enerated due to input phase jitter
The digital mixer is implemented with a MSD latch and it is possible that
the MSD latch becomes metastable due to setup and hold time violations thus
causing a misclock. Hence, the simple phase detector circuit shown in Fig.
3.1 (a) is susceptible to misclocking due to phase jitter of the input limiters (as
shown in Sectton 2.6), phase noise of the phase detector or metastable events or
any combination of the three.
The issues that affect the design of a digital mixer are latch design, latch
settling, metastabil.ity, and phase jitter. Most importantly for this application the
mixer circuit must be designed such that the miscount errors due to input phase
jitter are below a desired design criteria.
The discussion of the issues of metastability in section 3.2 and, latch design
in section 3.3 lead to a detailed analysis of the input phase jitter in the mixer in
section 3.5. The effect of a misclock on the measurement accuracy of the
system is also modeled in section 3.5. Section 3.6 summarizes the sources of
errors of the OPT measurement system, and concludes with the equation for the
33
basic measurement error thus summing up the OPT measurement system
design.
3.2 METASTABILITY
The fundamental constraints necessary for correct clockin91 of the input
signals by the MSO latch in the digital mixer are the setup and hold time, the
maximum clock rate, the minimum p,ulse width and at times the slopes of input
signals. Violation of any of the above constraints may cause a condition of
metastability where the latch enters an undefined state thus causing misclock(s).
Fig. 3.4 shows the schematic of a CMOS VLSI OIatch.
\I") ~ A
2
~LK \... M
.IL/
[}
~LK_BAR 1.11
• (a) (b)[25]
Fig. 3.4(a) DLatch (b) Equilibrium points in crosscoupled inverters
With CLK=1, Q takes the value of input 0, while with CLK=O it acts like a
memory element storing the value previously introduced. In this situation, the
latch may become metastable when the input triggering has led it to point M in
Fig. 3.4(b). The various permutations of input triggering that may cause the latch
to become metastable are illustrated by Filg. 3.5.
34
,1
r,T .K
i '~"
1/
n I ~
i .......; I I a ; Q ~ ; b : j/
tr ""I
(a)
eLK ~" .
D
._~
,'''p.. : 
~
Q
...L.g ,~ .'.,, tr (b)
eLK or.' /. ; ~ D ~T_~ Q ) v: "] : : h ~I ! (c) • GLK ).""~ :..: D :T~.: ~,.~ ~
Q
.....~ ... 'tr
(d)
Fig. 3.5 Input triggering that might cause Metastability. (g=time interval
between change of 0 and fall of Q, Tw=time interval between rising and falling
edge of elK, tr=resolution time) [23]
35
(a) Q=O, D=O AND CUK=1, SIMULTANEOUS CHANGE OF D: 0~1
AND C1lK: 1~O
(b) Q=11, 0=1 AND ClK=1, SIMULTANEOUS CHANGE OF D: 1~O
AND ClK: 1~0
(c) Q=o, 0=1 AND ClK=O, ClK PULSE: O~1~0
(d} Q=1, D=O AND ClK=O, elK PULSE : 0~1~O
In Fig. 3.5, cases (a) and (b) arise from skew in the clock signal (setup
time violation), and (c) and (d) show the effect of runt ClK pulses on the static 0
latch (ho,ld time violation).
The latch once mistriQlgered as in cases (a)(d), would theoretically stay in
this undefined (metastable) state for an indefinite time period. These conditions
(a)(d) define the region in which the latch would become metastable. This
region is known as the metastability window. Resolution time (tr) is used to
quantify the time needed by the latch to reach a stable state, after a metastable
event occurs.
The most common way of determining the metastability window is by the
representation of tr versus metastable event (<>=T or g). (Fig. 3.6)[23]
36
•
I T _~I w
i
I
I!!
IT
iWmaX
i
Ocrit
Fig. 3.6. Typical shape of trversuso. Metastabi:lity Window (tre=normal
resolution time, o=metastable event)
The width of the metastability window (Tw) is used to characterize how
good a latch is with respect to metastability.
(30)
Also, Mean Time Between Failures (MTBF), Le. the mean time between
metastable events, is defined as [23]:
eli 1
MTBF= =
fDfclkTO fDfclkT,,,
37
(31 )
where
fD =data frequency (corresponding to FP)
felk=clock frequency (corresponding to FREF)
1r= resolution time
Tw= metastability window
To = asymptotic width of Tw
't= Regenerative (resolution) time constant, and is given by, r = gm
CL
To deal with this unstable or "'in between" state designers typically attempt
to reduce the metastability error rate (MER) to some acceptable value. The
methods employed include using faster and specifically designed (metastable
hardened) devices with extended settling times, Schmitttriggered inputs,
pipelined flipflops, and a pausable clock and metastable detectors [24], [25].
In order to reduce the probability of the occurrence of a metastable event,
the MSD latch (presented in Section 3.4) has been selected for its zero hold time,
i.e., the only constraint on the input signals is the setup time of the latch.
Theoretically, once the latch enters the state of metastability (point M in Fig.
3A(b)),. it would stay there for an infinite time period (Fig. 3.6), however, the
thermal noise in the latch causes the latch to recover from this state of
equilibrium to settle to either point A or B of Fig. 3.4(b) depending on the thermal
noise and the input voltage. For discussion purposes, a flowchart that explains
the calculation of the total probability of a miscount given a metastable event is
presented (Fig. 3.7).
38
Assume: vN << vE
Noiseless clock signals
N
Not
Metastable
Noiseless Mixer
Metastable
V < vE
Yes
6a
es
Compute
P(false decision)
Asynchronous Data
& clock
Jitter/noise in signal
Can we make a decision a non decision?
Can we make a non decision a decision?
Total Probability of a miscount
given a metastable event
Considering only at metastable boundary
Fig. 3.7. Probability of miscount given a metastable event
Fig. 3.7 starts with the latch being at the metastable precipice, i.e., an input
voltage transition has caused a setup time violation making the latch metastable,
also there is not enough noise in the signals or the latch to push the latch out of
this state of equilibrium (i.e., ktsetup and Vthermal noise < VE, where VE represents an
infinitesimally small voltage). The two paths in the flow chart are representative
of the fact that the noise lin the mixer or the noise in the signals (probabilistically
independent events) would cause the latch to resolve to a logic level (points A
39
and B in Fig. 3.4 (b». Mathematically, the probability of a miscount given a
metastable event is given as:
P(miscount I metastable)=P(metastable latch) + P(noisy signals)
The inputs to the mixer come from the limiters (Fig. 1.1) so considering the
case when there is no noise in the signals (thermal noise of Iimiters=O); the
probability of a miscount is given by the probability of the latch being metastable.
In order to calculate the probability of the latch being metastable, we need to
know the thermal noise of the latch. The next section introduces the latch design
and a calculation of the probability of the latch being metastable given the
thermal noise of the latch is presented.
The other case to be considered is the case of zero thermal noise in the
mixer, i.e., noisy limiters. The thermal noise in the limiters effectively defines the
probability of noisy signals causing a metastable event. The next section shows
the calculation of the phase noise of the input limiters. The effect of input limiter
induced phase jlitter, i.e., the probability of miscount due to noisy input signals is
modeled in Section 3.4.
3..3 Latch and Mixer implementation example
Metastability errors in latches with asynchronous inputs are
probabilistically unavoidable and it is possible that the metastable state will exist
for an indefinite time period should a metastable event occur. When the latch is
in the metastable state the thermal noise of the transistors becomes the
dominant factor in resolvling metastability [24], [25]. For discussion purposes Fig.
40
3.8 shows a device leve! diagram of a latch used in the mixer. Increasing the
gain bandw:idth product of the regenerative latch circuit, M1, M4, M5, M6,
produces a shorter resolving time [24], [25], which will reduce MER. Increasing
the static noise margin of the devices in the regenerative latch circuit reduces the
time to recover from metastabi:lity. Full symmetry in the latch has been described
as a good design strategy for a metastablehardened latch [24], [25].
Latches for our mixer were designed using the architecture of Fig. 3.8,
with full symmetry as weill as with zero hold time. The thermal noise in the mixer
helps the mixer resolve to a logic level and hence, the transistors ,in the latch
have oversized geometri,es for metastable hardened operation. See Table 3.1
Q
~P:LEAR
DATABAR
Figure 3.8 Latch Implementation
41
TABLE 11 DEVICE GEOMETRIES
MOSFET M@W {J.lm)/L (Jlrn)
M1, M5, M9, M10 4@9/2
M2, M3 2@9/2
M4, M6, M7, M8, M11, M12 8@9'/2
In Fig. 3.9, FP is the frequency being counted with reference to frequency
FREF. FDIFF represents the difference between the two frequencies (FP and
phase difference of zero or 180 degrees between FP and FREF.
(FF2) and NAND gates U1AU1 D (shown in Fig. 3.9) have been added. The
to detect and correct misclocks due to input phase jitter an additional flip flop
output of mixer, Le., FDIFF, changes only when both FF1 and FF2 detect a
v V d V d V
FREF) and CLEAR is used to asynchronously clear the flipflops. Now, in order
0"_0 FF1
11
Fig. 3.9 Di:gital Mixer Implementation
42
To inspect the behavior of this mixer (Figure 3.9) more closely, we have
shown the finj'testate diagram of the mixer with its four possible state included
(Fligure 3.10). In the diagram, each state transition is accompanied by its
corresponding transition condition, which is basically the positive transition of
FREF (elK) and FP (unknown frequency), denoted by FREF1' and FPI
respectively. Two simultaneously occurring positive transitions are simply
denoted by (FREF1' FPI).
FP=l FREFi
FP=lFREFi
Fig. 3.10 Finitestate diagram of
~FREFi
FREF
43
Mixer operation.
A simple technique for achieving an arbitrarily small metastable error is to
sample the output of the flipnap after delay by using cascaded flipflops [24].
Increasing the number of stages reduces exponentially the probability of a
metastable event but at the cost of increased latency. Consi:der the simple case
of two cascaded flipflops (Fig. 3.'9). In order for FF2 to go metastable, FF1 must
present a metastability that lasts longer than the clock delay time or resolves in
the critical window, i.e., the sum of setup and hold times, of FF2.
Probability of a failure is a Poisson process and is given by
the cross coupled latch.
Using process parameters, we get the following parameters,
where T=c1ock frequency, 't=regenerative latch resolution time, A=self gain of
:x P(failure) == e A .
A 2 30
A:.~V
r == CL == 2. 5L
2 == O.4ns
gm 3 Kp·f).V
assuming a 3X load and a AV of (Vdd/2 Vt)=1.1 V.
(32)
(33)
Thus from the numbers above, the probability of failure can be calculated
to be approximately equal to 7.88E66. Now, if we send a sample every 143
nanoseconds we get a failure every 18.15E+57 seconds which implies a failure
44
approximately every 5.755E+50 years. Hence, the chance of metastable events
for this circuit ils inconsequential.
Now, as shown in Fig.3.7, the input limiter induced jitter may also cause
the latch to become metastable. In order to avoid this, limiter jitter must be
significantly less than the latch metastable settling time (given by (34» [26].
[ . ] Ll VLog ic
TLATCH = r LATCH In Ll V0 (34)
Thermal noise causes jitter or uncertainty in the limiters that increases the
uncertainty in the phase of the measured signal, thus increasing the probability of
a misclock to occurring in the mixer.
Thermal noise of a MOSFET is given by [26]:
(35)
Using analog noise analysis techniques the composite thermal noise of
the mixer is an aggregate sum of the thermal noise in transistors of latches FF1
and FF2, and the limiter transistors of gates U2A and U2B. This result may be
calculated using (35). By selection of proper transistor geometry the 1/f term in
(35) has been made small enough to be ignored. In addition the selfgain of the
limiters (M=16, W=9Itm, L = 211m) r,educes the significance of the latch jitter.
Composite noise was evaluated using geometries in Table 3.1. The jitter
contribution of the limiters is given by:
T. ~ ~ 4kT 1 < 2 S
Jitter 3C 2V '"" P gs pi':} P
45
(36)
where Cgs = 993.6 fF, Vp = 1.65V,. FP = 7 MHz.
This value corresponds to a phase jitter of 5E3 degrees at the
measurement frequency of 7 MHz. Also, this value, when substituted into (25)
and assuming N=24 causes much less error (3 orders of magnitude) than the
fundamental error giv,en in equation (19). Therefore it is not anticipated that
limiter jitter or the thermal noise in the latch will induce measurement erl"Ors.
Hence we have verified that the error caused by metastability and limiter induced
jitter is not significant. In Section 3.4 we present an input phase jitter model thus
modeling the final inaccuracy in the measurement system.
3.4 Input Phase jitter model
Starting with the basic measurement equation (5) it is easy to show that
the measured frequency is given by:
f meas
NAVG*FREF
224 Latchl (37) The error of this count is ±224 plus the error in the reference frequency (yielding
a basic system inaccuracy of .06 ppm).
The mi:xer (see Figure 3.1) as implemented using a MSD latch with the
unknown frequency applied to the D input and the reference frequency applied to
the clock is susceptible to misclocking dlUe to input phase jitter which may cause
a miscount. In order to corr,ect for the inaccuracy in the measurement, the
46
measured frequency is averaged over 224 cycles of FREF. Additional latch (FF2}
and NAND gates (U1AU1 D) detect and correct misclocks due to phase jitter
(Fig. 3.9').
The circuit is based on the assumption of a noiseless advance in the
phase difference of the input signals. Whenever the phase difference of FREF
and FP glOes through zero or 180 degre,es the output phase will go from lowtohigh
or hightoIow respectively. When the input phase difference goes through 0
degree or 180 degrees and an output phase crossing is produced, if noise
causes the input phase difference to be reversed at subsequent clock pulses, a
false reversal of output phase will be produced. After each phase crossing there
is a chance of a misclock being produced by jitter induced phase reversal at
subsequent clocking edges. Modeling the jitter in the input phase difference as
Gaussian with zero mean and variance if, the conditional probability of a
misclock on the kth clock edge, following the occurrence of the first output phase
crossing can be derived as:
] M.e _ x2
p(misclock I, k) =.J2i f e 20
2 dx
2ila 00
(38)
In order to model! the misclock rate, in misclocks per second, we need to
sum all the probabilities over the entire FDIFF cycle and then divide it by one
period of FDIFF. Hence the misclock rate is modeled by:
M = IFREF FPII[ 1 7e :~, l k=1 J2ila 00
47
(39)
where
1 NX
M = Lp(misclock Ik)
TFDIFF k=l
(40)
where M is the misclock rate and NX is FREF cycles per FDIFF cycle.
A bench study was conducted using HCMOS components to assess the
" effect of phase jitter on the measurement accuracy. Fig. 3.11 shows the setup
tor the bench study.
7
HCMOS
ONE SHOT
74123
2
C
3
4 5
6
3 h'l
HCMOSD
FLIPFLOP
7454
f~2
[MHz
crystal
osci.llalor
Reference
Frequency
Frequency 10 be
measured
7400
Ll NAND
OUTPUT
'Dl TO
COUNTER
Fig. 3.11 Bench study setup for input limiter induced phase jitter analysis
48
The OFF generates an output frequency whenever there i:s a phase difference
between the measured frequency and the reference frequency. The output of
the flipflop goes to the input of a dual edge triggered monostable multivibrator.
The oneshot generates an output pulse whenever it sees an output from the flipflop.
The Rand C components are used to adjust the duty cycle of the output
pulse from the oneshot. The counter thus counts the number of misclocks
generated by a single flip nap based mixer.
4000 5000 6000 7000 8000
fdtrr
1000 2000 3000
I
Misclock rates measured I :
over 30 second period. ' ' _
; fREF= I MHz ::
I I • I
I I I I • I
    1     1     ,    l'      r      r     1    
I riO L I I I
I I I I I I I
I 'I I I I
_____ 1 1  I   ....J. _    ....     _ ~  _  __1_  _
I I I. I I
I I I' I I
I I I I I
    :  Trial and error match of ,    :     :  
: model to data give:; (J = : : :
_____ : _ _ 0.35 degrees ~ _ _ _ _ I : _
I I
: I Model predicts l error : :
;: ~v~l1daYSatf'DIFF= : ~:
I , ,
I r I I I I I
lI~~~~I 
ljjl~lj
I I ~ I , I
I I I I I I
I I r I I I
. '0
10
.,
t ,0. M
Mi
10..
'0.
10."
'0.I~
10
Artifact from '.r,..,.r,..., measurement'O
method
..
FDIFF
Figure 3.12 FDI FF versus misclock rate (M) using HCMOS components
49
Fig. 3.12 shows the results of the mixer clocked at 1 MHz and the
misclock rates were measured over a 3,0 second time peri'od. The data verified
the model (42) for inaccuracy in the system and predicted a misclock every 11
days if we were to use a mixer as in Fig. 3.1 with the two frequencies being 6KHz
apart.
Extending the inaccuracy model, in order to predict the misclock rates in
case of the cascaded Dflipflops (Le., with inhibit circuit, Fig. 3.9) implies a
decrease in the misclock rate by 4 orders of magnitude. Results in Fig. 3.12 [27]'
demonstrate that with a cascaded implementation (inhibit circuit) phase jitter is
insignificant if the difference between the two frequencies is greater than 2 KHz.
At a difference frequency of 6 KHz, the circuit would have an error of 0.06 ppm,
.I.e., one part'In 224.
3.5 Error in the OPT measurement system
The four main sources of error of the OPT measurement system have
been mentioned and dealt with separately. This section sums up the errors of
the measurement system and present an estimate for the measurement
inaccuracy when measuring a frequency of FP=7.006 MHz7.030 MHZ with
respect to a reference frequency of FIREF=7 MHz.
Starting with equation (19) the basic OPT error equation,
ERROR =+ IN
2
(19)
•
we had modified it to account for the input limiter induced phase jitter as given by
equation (23): .
50
f meas ~_F=D_IF_'_F _*_T~'::':::;lle=as~J
T meas + 2*T·J (23)
Now, substituting for jitter due to thermal noise in the limiters as given by
equation (36) we had established, in Section 3.4, that the limiters by selection of
correct geometries do not affect the measurement error. The other sources of
error include misclocks due to phase noise in mixe~, and the possibility of the
mixer being metastable. In Section 3.4 we have established that misclocks due
to mixer being metastable are inconsequential due to proper design. Phase
noise analysis of section 3.4 explains how we had selected the mixer architecture
as well as proven that phase noise induced misclocks are not an issue for the
frequencies we are dealing with. Hence equation (21) entirely describes the
error in measurement of the aPT measurement system.
3..6 Review of previously published phase detector architectures and a
comparabve overview of them as opposed to the digital mixer architecture.
Phase locked loops (PLLs) with phase frequency detector (PFD) are often
used in I/O interfaces of digital VLSI circuits to avoid clock distribution
delay/skew, jitter and to improve overall system timing. A number of
architectures for phase detectors have been proposed in the literature, this
section reviews and compares PFD architectures similar to our MSD latch based
phase detector. A MSD latch acts as a PFD, Le., can detect data transition as
well as phase difference as shown in Fig. 3.1. The MSD latch phase detector is
called a "bangbang" phase detector because the output swings from railtorail
as a function of the phase difference between the two signals present at its
51
inputs. Two features that are critica,! when choosing a PFD are: the monotonic
detection range and the frequency detection capability. This section will go over
features of two different PFDs, and focus on pros and cons of the designs when
compared to the PFD presented in thils thesis.
3.6.1 Hogge Detector [28J:
Fig. 3.13 shows the linear PFD architecture proposed by C. R. Hogge
[28]. The output of the circuit shown in Fig. 3.1 (a) is sensitive to data
transition density, i.e., failing to uniquely represent the phase difference when
the data transition density falls to onehalf and the phase difference becomes twice as much. In the Hogge Phase detector (HPD) both the DFFs act as
decision circuits eliminating the ambiguity due to transition density.
1 \1
2
I.
A U2A
1 \1
H dH dH_l
0 in 0 o out P"'"    0_ _D Q ... ~CLK r • eLK
~I K
U3A ux
Fig. 3.13 Hogge Phase Detector
let us consider the HPD in the presence of finite delays of the flipflops. A
change in the output A is delayed by the c1ocktoQ delay of the DFF yielding a
pulse that is wider than the phase difference between D_in and elK, while the
52
output D_out is simply a delayed version of A, shifted by the clocktoQ delay of
the OFF. Ideally, when the input phase difference is zero the pulses X and Yare
identical, however due to finite delays in the DFFs the pul:se at X would be wider
than pulse Y. Thus the output would be a spectrally impure control signal going
to the VCO. This circuit uses the over~ap of pulses X and Y to control the VCO.
Hence if the waveforms of the input signals are not symmetrical, the detection
range may be significantly reduced, thus the HPO is not frequency sensitive.
Now, consider the digital mixer (Fig. 3.9) as a PFD. As can be seen from Fig.
3.1 (b), the mixer generates an output proportional to the phase difference
between the two input frequencies. The misclock analysis (Fig. 3.12) shows the
robustness of our mixer in the presence of finite delays, thus the mixer presented
here is more reliable than the HPD for PLL and COR applications. Up to, the
tested range of 10MHz the PFO presented here is linear as well as frequency
sensitive. However, our mixer was not tested at frequencies greater than 10
MHz, and for fast clock speeds (greater than or equal to 10 MHz) the mixer
needs to be analyzed more closely.
53
3.6.2 Alexander Detector [28]
ct!t
""..J.ll.o
FFI ,... CLK
dtel
0 .....0
FF2 elK
0.......,~~out1
d11.2
)O"_CLK
L......__ o
FF3 o__=
Fig 3.14 Alexander Phase Detector
We have established that a single DFF is not sufficient for reliable phase
detection. The Alexander phase detector (APD) is shown in Fig. 3.14.
The APD is based on the principle of multiple sampling of data in the vicinity of
expected data transitions, and using the resulting samples to provide the control
signal to the VCO. In Fig. 3.14, FF2 and FF4 act as delay elements, and FF1
samples D_in on the rising edge of the clock while FF3 samples the input on the
falling clock cycle. The APD can determine whether a data transition is present
as well as whether the clock lags or leads the data. [8] In the absence of data
transition, i.e., zero input phase difference, the APD gives a zero output thus
leaving the VCO undisturbed. The APD configuration provides inherent data
retiming. The more robust architecture such as the APD comes with higher
power dissipation. The APD is a more robust architecture in comparison to our
54
digital mixer of Fig. 3.9 because of the added redundancy of FF2 and FF4 in the
APD. This circuit is more robust to metastable conditions {24] but this comes at
the cost of increased latency that would decide the maximum clocking frequency
of the APD, and the PLL. The APD however has no feedback while the phase
detector presented in this thesis does which limits the maximum clocking
frequency of our digital mixer in comparison to the APD. The digital miixer
presented in this thesis is intended for low speed (10 MHz), low power (2.0 V)
appl,jcations. However, for faster speeds and lower power applications other
techniques such as dynamic logic, domino logic and simulation based
optimization of the mixer architecture are suggest,ed. We recommend the use of
this mixer/ PFD for low power, low speed area constrained applications for its
simple design and inherent robustness.
55
CHAPTER 4
QPT SIMULATION AND RESULTS
This chapter presents the simulation and results of the QPT implemented
using Peregrine's 05 micron SiliconanInsulator (Sal) (UTSi®) process. The
design presented is heavily simulation aided and SPICE simulations are
presented wherever possible to project the performance of the actual OPT. A
functional verification of the fabricated QPT measurement system was done at temperature of 180 degree Celsius and at a frequency of 1 MHz, the results of
which are presented in Section 4.1.
The OPT as implemented does not have oscillators integrated on~chip.
During the entire design we assumed that the noise floor of the OPT is eventually
set by noiseiln the oscillators. For s,imulation purposes ideal pulse sources were
used as the oscillators and for testing the inputs were provided using Data
Generator DG2020A. The various building blocks of the OPT were separately
tested for verification of functioning and their circuit schematics and testing
results are also presented here. In chapter 3, we had proven theoretically and by
means of experiments on the mixer that the OPT measurement system
measures an unknown frequency with an accuracy of 0.01 ppm. Results in this
chapter are provided to substantiate our claim.
56
4.1 The QPT Measurement System
As shown in Fig. 2.2, the architecture of the OPT system, consists of five
major components: (1) two crystal oscillator circuits which generate temperature compensated reference frequency, FREF and the frequency to be
measured, FP; (2) limiter circuits that convert oscillator sinusoids into logic level
clock signals; {3) a digital mixer thai produces a difference signal, FDIFF, from
the reference frequency, FREF and the unknown (measured) frequency, FP; (4)
the period averaging circuit, NAVG counter and (5) the measurement interval
counter and latch, Latch1 and FREF counter. The OPT measurement system
presented in this thesis does not include the oscillators.
Fig. 4.1 shows the building blocks of the OPT.
Fig. 4.1 Building blocks of the QPT measurement System
57
As one can see, the OPT measurement system is a fai;rly simple, alldigital
desi,gn comprising mostly of standard cell library type components.. These
building blocks were optimized for high temperature application. All the building
blocks of the OPT were tested separately and the schematics, simulations and
results are presented in the sub sections that follow.
A block schematic of the OPT measurement system is given in Fig. 4.2.
This schematic was simulated in OReAD PSpice and using transistor models
provided by Peregrine Semiconductor. The results of the simulation are shown
in Fig. 4.3.
Beginning at the leading edge of a period of the FREF signal, NAVG
counter latch counts NAVG; the number of difference frequency periods, that
occur during the time it takes to accumulate 2N counts of FREF in the FREF
counter. Latch1 is used to hold NREF; the total counts of FREF that occur in
NAVG counts of the FDIFF ,period.
The circuit measures the unknown frequency (FP) by measuring the time period
and taking the inverse. The OPT measurement equation is provided, as a
reminder:
NAVG·FREF
fmeas = NREF  Latch!
58
(5)
59
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fI)
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Q....)
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~
l n.
0
Q)
.c
l
N .:i
0> i.i: I ~ ~.J I1
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Fig. 4.3 Simulation results of the QPT Measurement System
.. .
Fig. 4.3, above, shows the simulation results of the OPT measurement system
simulated at FREF=7 MHz and FDIFF=6KHz. At the beginning of measurement cycle, along with the reference frequency (FREF) and the
frequency to be measured (FP) a START signal is given to the OPT
measurement system. This START signal triggers the OPT control circuit into
action and it g,enerates the clocks (GATED_FO and GAIED_FREF) used to load
both the NAVG and FREF counters. An END signal, signifying the end of measurement time interval, is generated when the 24bit counter (FREF
counter/latch) overflows. Upon receiving this END signal, the OPT control circuit
disables the counters by removing the clock. Figure 4.3 also shows signal's "dOd23";
these are outputs of the 24bit FREF counter. Signals "nOn3" are the first
four outputs from the 16bit NAVG counter. Both the 24 bit FREF counter as well
as the 16bit NAVG counter are made using a 2bit counterlatch building block.
In order to make sure that the counterlatch is functioning as desired, some of the
outputs from the 2bit counter latch were also observed (signals 2bitcntrx.tffx.Q).
Signal "Counten" generated by the OPT control circuit is an intermediate test
signal, to verify functioning of the OPT control circuit which generates the clock
(GATED_FREF and GATED_FO) for the two counter latch circuitries.
Fig. 4.4 shows the testing results of the OPT fabricated in Peregrine's 0.5 micron
SiliconanInsulator (SOl) (UTSi®) process.
61
Tek Run: 100kSls Sample
~.{....__..::r._..._...._.__._._._: ]
'~·F~~··;····.'~~m' •.··'···'~••_ffiEF
,j. \
..' ~ ... ;. :.... ": .... :...... :..... 'Ti' ' LI<;~,~1.:~~~_:.,~._:'':'';''': ..~~,~..~~''''~ I"lD OF cau
, ,. R~FLOAD: : : :~ ': : : : .
. . . . . .. .. . : : ,.. : . : . J : : : : ~ REFLOAD 7..... ,. 1.....
6.......1IIIl"9'..........,.~1I'lIiloPI!...,""nIl.;..~................
1 ,\" '. ' .. , .... , . , • '... t ... , . , , .. , ...... , •.. , . , . :;,..
.... .: I Of:~.... If' :', ,,,' •••I... ~ ~ ....~... ...:N"'"
••.'~~ j ..... ' .• "~''"'_+.... ,; _~. ; .... l .....''
Fig. 4.4 OPT Test Results at 180 0 Celsius.
The data was taken at 59 KHz at a temperature of 180°C. Fig. 4.7 shows . .
the FREF signal (waveform 1) and the measured FP signal (waveform 2).
Control signal CLEAR (waveform 3) clears the previously stored values in NAVG
Counter, NREF counter and Latch1. REFLOAD, a I'oad signal that latches NREF
into Latch1, is waveform 6. An END OF COUNT (waveform 4) signal is
generated at the N+1th count, Le., when NREF counter/latch overflows.
6'2
4.2 Digital Mixer
The digital mixer forms the heart of the OPT circuit. The digital mixer
shown in Fig. 4..5 was simulated to find the difference between two Gloseily
varying silgnals (6 KHz to 30 KHz apart) when clocked at a frequency of 7 MHz.
A schematic of the digital mixer is shown below.
Fig. 4.5 Digital Mixer
Fig. 4.6 shows the signals from the mixer in operation at 3.3 V,180°C at
FREF equal to 1 MHz, and FDIFF of 6 KHz. The inputs FP and FREF were
given to the milxer using a Data Generator DG2020A and a Tektronics TLS216
logic scope was used to save and view the results shown below.
63
. ..
Ii +. ..
~~.Jifj.H+::::jt++++.·H..·r.~lLHHc>+H+HH+H'"·,lrt: ++.., '...1'.:r."r"I.. ·
,
·
,
..+t
3 ..,.J;o<~~. ~"',",,,.~r_,,<.....,....,..; J ~.. +
CLEAR
REFLOAD
,. FREF
.. .~ ..
""'""I1'<+'~r'"'.,~L r......,.v'lo"or'.f'''."i''>J·.JI,·"<~·~i' ..~o//~~II/If",~·,J,\,I:.:·..J<{~~)rwM"'~I";
8.....
ge 6o
Fig. 4.10 FREF Counter Control Circuit Results
67
The FREF counter controll circuit was laidout as a test cell on a 2X12 pad
test frame and was tested using a data generator DG2020A and a power supply
of 3.3 V. The circuit was probed at a frequency (FREF) of 57 KHz, and the
results are shown in Fig. 4.10 above.
The aPT measurement system has been tested and iits functioning
verified at 3.3V and temperature of 180 degree Celsius. The building blocks of
the OPT measurement system were also tested at separately at an elevated
temperature of 180 degree Celsius. Thus, we have shown theoretically and by
means of simulations, results and measurements that the OPT measurement
represents a significant advancement over the current stateofart design in
terms of size, operational temperature and accuracy. The current stateoftheart
sensors allow for an accuracy of +/ 0.1 ppm and are deployable at
temperatures up to 175 degree Celsius. Accuracies of 0.06 ppm (224
) at 200
degrees Celsius have been demonstrated using the aPT system. The system is
implemented using Peregrine Semiconductor's 0.5 micron UltraThin SilicononInsulator
process, UTSi® [30], which potentially allows the extension of the
operational temperature range of the OPT up to 250 degrees Celsius [15].
A unlique feature of this design is that it is an alldigital solution eliminating
the need for bulky temperaturesensitive analog mixer and filter components.
Monolithic VLSI implementation greatly reduces size and ensures higher
accuracy.
68
CHAPTERS
CONCLUSION AND SUGGESTIONS FOR FUTUIRE WORK
This thesis presents an alternative digitalonly architecture for a quartz
resonator based pressure transducer (OPT) systems. The system was
implemented as a monolithic VLSI SOC using SOl CMOS technology.
Accuracies of 0.06 ppm (Z24) at 200 degrees Celsius have been demonstrated
using the OPT system presented in this thesis, which is an improvement over the
current stateoftheart sensors, which allow for an accuracy of +/ 0.1 ppm and
are deployable at temperatures up to 175 degree Celsius [13]. The primary aim
of this project was to extend the operational temperature range of the current
stateofart from its current 175 degree Celsius by researching different
technologies and different design techniques.
This work builds and improves upon the previous OPT architectures by
using a similar topology but redesigning the components that cause inaccuracies
in the previous OPT designs. A unique feature of this design is that it is an alldigital
solution eliminating the need for bulky temperaturesensitive analog mixer
and filter components. Monolithic VLSI implementation greatly reduces size and
ensures higher accuracy.. Implementation using sal CMOS allows the extension
of the reliable operational temperature range of the QPT as well as has the
potential to increase the expected lifetime of the system at elevated
69
temperatures. Based on a period measur,ement method [16], the aPT
architecture is described and the basic measurement equation for the aPT
system derived (Chapter 2). A +/ onecount uncertainty is inherent to the aPT
system by vlirtue of its architecture and is included in the basic measurement
error model of the aPT. A novel DFF based digital mixer is presented along with
its design and functioning details. limiter noise induced phase jitter,
metastability issues in digital mixer that cause false clocking of the QPT are
modeled. The effect of a false dock on the measurement accuracy of the aPT
system is modeled and presented in Chapter 3 with regard to preselVing 24 bits
of accuracy while measuring a baseband signal varying from 6 KHz to 30 KHz
using a reference dock of 7 MHz.
The aPT system was fabricated using Peregrine Semiconductor's 0.5
micron UltraThin SiliconanInsulator process, UTSi® [30]. Chapter 4 presents
the simulation and results of high temperature testing of the fabricated aPT
system and its building blocks.
Suggestions for other works in the Held:
The aPT architecture presented here does not have oscillators integrated
with the system. Therefore, the most obvious direction is to go from here and
implement th,e aPT with onchip oscillators..
Further works on the subject of this thesis can be pursued in analyzing
the effect of longterm hi,gh temperatures on the system. Accelerated life
testinQl at elevated temperatures should be done to estimate the life span of
the OPT. An important application of the mixer circuit is in the field of
70
communications as a Phase Frequency Detector (PFD) for use in phase
locked loops that the authors have not fully explored. The authors have
recently discovered I!iterature that discusse,s the design of PFDs ior various
applications and optimization techni,ques [31], but Hazavi [25] is the only one
who specifically points out the difference between the two topologies. The
digital mixer presented in this thesis goes a step further in combining many
advantages of the various phase detector techniques elaborated in section
3.5 that have been developed so far with some novel contributions from the
authors. With this in mind the mixer has achieved respectable performance
figures as far as thermal noise and consequently misclock rate is concerned.
Simulations and results indicate this performance but the actual circuit was
not tested at a frequency greater than 11 MHz.
71
BIBUOGRAPHY
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75
Thesis:
VITA
IRA SHANKAR
Candidate for the Degree of
Masters of Science
QUARTZ PRESSURE TRANSDUCER SYSTEM IMPLEMENTED
USING SOl
Major Field: Electrical Engineering
Biographical:
Personal Data: Born in Lucknow, India, on August 12,1977, the daughter of
Indu and RaJeshwar Yadav.
Education: Graduated from Delhi Public School, R K Puram, New Delhi,
India in May 1995; received Bachelor of Engineering degree in Electronics
and Telecommunications from Or. B.A.M. University, Maharashtra, India in
July 2000. Complleted the requirements of Master of Science degree with a
major in Electrical Engineering at Oklahoma State University in May 2003.
Experience: Summer trainee engineer at Bharat E'ectronics Limited,
Ghaziabad,. India, May 1998 to August 1999; Research Assistant, Mixed
Signal VLSI Desilgn Laboratory, Oklahoma State University, Department of
Electrical and Computer Science Engineering, August 2000 to January
2003; Design Engineer Intern at Microsystems Engineering Inc., Houston,
TX, February 2003 to Present 