HARDWARE IMPLEMENTATION OF
A FULLY TUNABLE HETERODYNE
NOTCH FILTER IN FPGA
By
DHINESH SASIDARAN
Bachelor of Science
Oklahoma State University
Stillwater, Oklahoma
1999
Submitted to the Faculty of the
Graduate College of the
Oklahoma State University
in partial fulfillment of
the requirements for
the Degree of
MASTER OF SCIENCE
May, 2002.
HARDWARE IMPLEMENTATION OF
A FULLY TUNABLE HETERODYNE
NOTCH FILTER IN FPGA
Thesis Approved:
Thesis Adviser
11
Preface
Wireless and satellite communication systems often use spread spectrum techniques
to modulate the narrowband informationbearing signal before transmission. This
technique masks the transmitted signal as noise by spreading the narrowband signal, therby
preventing the effective use ofjamming and interception techniques in interefering with the
transmission. However, during such a transmission, a narrowband interference signal from
nearby transmitters could find its way onto the channel of the desired signal. The existence
of this interference signal on the channel ofthe desired signal could ultimately cause detection
errors and anomalies at the receiver end. These detection errors and anomalies appear
when the receiver latches onto the undesired signal instead of the desired signal.
In this thesis, a novel approach is taken to remove the unwanted interference frequency
from the channel. A tunable filter system is used to remove the undesired signal at the
receiver end of the transmission before the desired signal is extracted and used for any
given application.
The entire tunable system actually employs the use offixed filters in its lowerlevel
structure to remove the narrowband interference signal, but the system itself is completely
tunable. This continuously tunable property allows any frequency from 0 to DC to be attenuated
by tuning a single parameter, which is the heterodyning frequency.
III
Since the underlying basis for this tunable filter is the use of the heterodyning concept, it
can be shown also that all images created by the heterodyne (mixing) process are eventually
cancelled without the use of any additional filters.
This thesis concentrates on the digital hardware implementation of the proposed
filter structure. Since a digital version of the proposed filter has never been implemented,
this thesis will put forth the idea of achieving a workingstructure with minimal hardware
of the filter to remove narrowband interferences from a channel. The platform for this
implementation of the proposed structure is Field Programmable Gate Arrays (FPGAs)
which provides a suitable hardware structure for rapid prototyping.
Although the tunable filter system presented in this thesis is implemented as a manually
tunable structure, an adaptive version could easily be built by employing standard
adaptive algorithms at the cost of incurring some additional hardware.
IV
Dedication
To My Parents, Dr Michael Soderstrand, Dr Louis Johnson
and Regina Henry for all their support, encouragement and
friendship.
v
ACKNOWLEDGMENTS
I wish to express my sincere appreciation to my research advisor, Dr. Michael A.
Soderstrand for his intelligent supervision, constructive guidance, insight and friendship.
His incomparable patience and confidence has guided me through my graduate study and
provided me with a valuable experience and knowledge. I also wish to extend my most
sincere appreciation and gratititude to my committee member Dr. Louis G. Johnson whose
guidance, assistance, encouragement, and friendship are also invaluable. I would also like
to thank committee member Dr. Keith Teague for carefully reviewing my thesis and giving
me his precious advice.
I am thankful to all my research colleague in the Digital Signal Processing and
Communication (DSP&C) Lab for their friendship and time and not to mention assisting
and helping me on numerous occasions.
I cannot help but extend my eternal gratitude to Ms. Regina Henry at the International Students
and Scholars office for being an invaluable friend, mother and advisor. I would like
to thank all my close friends for providing me with love, encouragement and support during
the period of my studies.
As a final note, I would like to acknowledge my family for all their patience and
support. I would like to thank my parents who have provided me with constant support,
love and encouragement through their prayers and love.
VI
Table of Contents
CHAPTER 1 Introduction 1
1.1 Broadband communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1
1.2 Problem Statement. 2
1.2.1 Narrowband Interferences (NBI) 2
1.3 Scope of Thesis 4
1.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CHAPTER 2 Background 7
2.1 Spread Spectrum 7
2.1.1 Interference Suppression in spread Spectrum communications 7
2.1.1.1 Direct Sequence 8
2.1.1.2 Frequency Hopping 10
2.1.1.3 Signal Recovery , " 10
CHAPTER 3 The Heterodyne Process 11
3.1 Frequency translation II
2.1.1 The heterodyne concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11
3.1.2 Superheterodyne receiver. 13
CHAPTER 4 Previous Work 15
4.1 Tunable Bandpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IS
4.1.1 Theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16
4.2 Final Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
4.2.1 Advantages 19
4.2.2 Disadvantages............................................................. 19
CHAPTER 5 FTHN Filter System 22
5.1 Splitter 22
5.2 Fixedcoefficient prototype filter. 24
5.2.1 Why implement a notch filter? 24
5.2.2 Filter selection 25
5.3 Combiner 28
5.4 The Complete FTHN Filter System 29
5.4.1 Theory of Operation 30
CHAPTER 6 MatLab Simulations 37
6.1 Filter translation 47
CHAPTER 7 Hardware Choice 53
7.1 Field Programmable Gate Arrays (FPGA) 53
VB
7.2 Xilinx XCV800 FPGA Structure 54
7.3 Configurable Logic Blocks (CLBs) 55
7.3.1 Function Generator/LookUp table (LUT) 55
7.3.2 The Arithmetic Logic 55
7.3.3 Storage Elements 56
7.4 Input/Output Blocks 57
7.5 Block SelectRAM 57
7.6 CLB Configuration 58
CHAPTER 8 Hardware Implementation 59
8.1 Sine/Cosine Genrator 60
8.2 8bit 2's Complement Multiplier 62
8.3 Splitter 64
8.4 Fixedcoefficient Prototype Filter 66
8.5 Combiner 69
8.6 Final Structure 70
8.7 Resource Usage 71
CHAPTER 9 Final Results 72
9.1 Experimental Results 72
9.1.1 Experimental Setup 72
CHAPTER 10 Future Work 91
10.1 Adaptive Heterodyne Notch Filter. 91
10.2 Cordic Algorithm 93
10.3 Multiplesource Interferences 94
Bibliography 95
Appendix A 98
Vlll
List of Figures
CHAPTER 1 Introduction 1
CHAPTER 2 Background 7
CHAPTER 3 The Heterodyne Process 11
Figure 31. Mixer block diagram 12
Figure 32. Superheterodyne receiver block diagram 13
CHAPTER 4 Previous Work 15
Figure 41. Tunable Heterodyne Bandpass Filter Unit. 15
Figure 41. Tunable Bandpass Filter operation 16
CHAPTER 5 FTHNF Filter System 23
Figure 51. Splitter circuit 24
Figure 52. Virtual translation in frequency of a highpass filter. 26
Figure 53. Direct Form II implementation of a firstorder highpass filter 27
Figure 54. Combiner circuit 28
Figure 55. Fully Tunable Heterodyne Notch Filter 29
Figure 56. Fully Tunable Heterodyne Notch Filter operation (part I) 30
Figure 57. Fully Tunable Heterodyne Notch Filter operation (part II) 31
Figure 58. Fully Tunable Heterodyne Notch Filter operation (part III) 32
CHAPTER 6 MatLab Simulations 37
Figure 61. Stages of the FTHN Filter structure 37
Figure 62. Block diagram of Splitter stage I 38
Figure 63. Time and frequency domain representation of the input signal 38
Figure 64. Normalized Power spectrum piot of cosoutl and sinoutl.. 39
Figure 65. Block diagram of Filter Stage I 40
Figure 66. Magnitude response of IIR highpass filter with 3dB cutoff frequency of 500Hz .40
Figure 67. Normalized power spectrum plot of signals cosout2 and sinout2 .41
Figure 68. Block diagram of Splitter Stage 2 41
Figure 69. Normalized power spectrum plot of signals cossin I and coscosl .42
Figure 610. Normalized power spectrum plot of signals sinsinl and sincos I .42
Figure 611. Block diagram oflntermediate Stage .43
Figure 612. Normalized power spectrum plot of signals sum1(=sum4) and sum2 (=sum3) 44
Figure 613. Block diagram of Combiner stage 1 44
Figure 614. Normalized Power spectrum plot of signals sumreal and sumimaj .45
Figure 615. Block diagram of Filter stage 2 45
Figure 616. Normalized power spectrum plot of signals in I and in2 46
Figure 617. Block diagram of Combiner stage 2 46
Figure 618. Normalized power spectrum plot of the output signal .47
Figure 619. Frequency response of 1st order highpass filter with 3dB cutoff at 500Hz 48
Figure 620. Polezero plot of original IIR highpass filter prior to translation .48
Figure 621. Filter uptranslated by 3kHz 49
lX
Figure 622. Polezero plot of highpass filter uptranslated in frequency 49
Figure 623. Frequency response of highpass filter downtranslated by 3kHz 50
Figure 624. Polezero plot of filter downtranslated by 3kHz 50
Figure 625. Final position of translated filter 51
Figure 626. Final pole and zero positions of translated filter 51
CHAPTER 7 Hardware Choice 53
Figure 71. Slice CLB 56
Figure 72. Detailed Virtex Slice 56
Figure 73. Virtex Input/Output (VO) Block 57
CHAPTER 8 Hardware Implementation 59
Figure 81. Sine/Cosine generator 61
Figure 82. Synthesized sine/cosine generator circuit using Synplify Pro 62
Figure 83. 8bit 2's complement multiplier block diagram 63
Figure 84. 8bit, 2' s complement multiplier implementation using Synplify Pro 64
Figure 85. Block diagram of the Splitter circuit.. 65
Figure 86. Synthesized Splitter circuit using Synplify Pro 66
Figure 87. Block diagram of Istorder highpass filter 68
Figure 88. Synthesized Ist order highpass filter using Synplify Pro 69
Figure 89. Block diagram of Combiner 69
Figure 810. Synthesized structure of Combiner using Synplify Pro 70
Figure 811. Final synthesized structure of FTHN filter using Synplify Pro 70
CHAPTER 9 Final Results 72
Figure 91. Interface between codec and FPGA on the XSV800 Vl.1 board 73
Figure 92.512 point, normalized Power spectrum plot of the input signa!.. 74
Figure 93.512 point, normalized Power spectrum plot of the heterodyning signaL 75
Figure 94.512 point, normalized Power spectrum plot of signal sinoutl : 76
Figure 95. 512 point, normalized Power spectrum plot of signal cosoutl 77
Figure 96. 512 point, nonnalized Power spectrum plot of signal sinout2 78
Figure 97. 512 point, normalized Power spectrum plot of signal cosout2 79
Figure 98.512 point, nonnaized Power spectrum plot of signal cossin1 80
Figure 99.512 point, normaized Power spectrum plot of signal coscosl 81
Figure 910. 512 point, normaized Power spectrum plot of signal sincosl 82
Figure 911. 512 point, nonnaized Power spectrum plot of signal sinsin1 83
Figure 912. 512 point, normaized Power spectrum plot of signal sum1 84
Figure 913. 512 point, normaized Power spectrum plot of signal sum2 85
Figure 914.512 point, normaized Power spectrum plot of signal sumreal 86
Figure 915.512 point, nonnaized Power spectrum plot of signal sumimaj 87
Figure 916. 512 point, normaized Power spectrum plot of signal in1 88
Figure 917. 512 point, nonnaized Power spectrum plot of signal in2 89
Figure 918. 512 point, nonnaized Power spectrum plot of signal output.. 90
CHAPTER 10 Future Work 91
Figure 101. Basic block diagram of secondorder adaptive notch filter.. 92
Figure 102. Complete Adaptive Heterodyne Notch Filter 93
x
List of Tables
CHAPTER 8 Hardware Implementation 61
Table 81. Resource usage comparison for sine/cosine generator and multiplier 73
Table 82. Resource usage comparison for FTHN filter components 73
Table 83. Resource usage comparisonfor entire structure 73
IX
1Introduction
1.1 Broadband communications
The importance of Digital Signal Processing (DSP) has been greatly exhibited over the
years. The existence ofDSP techniques and algorithms have opened up a plethora ofinventions
and advancements in the field ofcommunications and in almost every aspect of engineering.
In telecommunications, namely broadband communications, DSP algorithms have
enhanced the performance factor, reliability and reputation of the broadband communications
universe.
Broadband communications or sometimes known as wideband communications, can be
described as the transmission of narrow bandlimited information over a wide range of
available frequencies in an assigned bandwidth. This form oftelecommunication has a distinct
advantage of allowing several different types of information to be multiplexed and
sent to different frequencies within the wideband concurrently.
Previously, broadband communications were strictly confined in the analog domain where
analog signals were transmitted and received from one end to the other. The transmission
and reception of these signals were done using dicrete analog devices which were considered
primitive. However, modern developments in technology has allowed digital information
to be transmitted within the confines of the analog environment. With the properties of
data compression and manipulation available solely in the digital domain, the capability of
1
transmission has increased with the resultant increase in the number of channels available
in a given frequency band. This rise in efficiency has given digital data transmission a slight
edge over analog data transmission.
Even with these advancements, several issues still plague modern communication systems,
primarily the existence of narrowband interferences in broadband Binary Phase Shift
Keying (BPSK) and QuadriPhase Shift Keying (QPSK) signals. These interferences will
need to be addressed and eliminated from the desired signal.
1.2 The Problem Statement
One of the most common problems in controls and communications applications is the
detection ofa sinusoid. The sinusoid signals may contain important information to be transmitted
or may be of harmful nature whereby it is classified as a narrowband interference
(NBI) signal. Also, these sinusoids are not constant with respect to time and therefore
detection of these signals for extraction or attenuation can be a daunting task. In cases
where the sinusoid is harmful and lying adjacent to a desired signal, we will need to attenuate
these signals without affecting any nearby desired signals [1].
1.2.1 Narrowband Interferences (NBI)
Narrowband interferences (NBls) from external or internal noise sources are often strong
enough to 'drive' down and not to mention corrupt the critical information carried by
nearby adjacent signals. These interference signals, aptly called "adjacent channel" inteferences,
should be removed or greatly attenuated in order to preserve an intelligible amount
of information that is being transmitted from one end to the other [3]. Examples of well
2
known external noise sources or Intersystem Interferences (lSI) are radiofrequency transmitters
or certain weather conditions such as lightning; both of which produce radiofrequency
interference (RFI) while resonance in a sensor system used in a control systems is
a good example of an internal noise source [I ][3]. These high power signals adjacent to the
wanted signals can cause from slight to total masking of the desired signal [3]. With these
effects on signals around it and on the receiver, narrowband interferences has been causing
some major problems, especially in the mobile communications universe. These signals
can appear anywhere in the entire bandwidth of the channel and can appear from one, upto
any number of sources. It would seem impractical and not to mention impossible to guess
where these interference frequencies would appear and to build a fixed filter based on that
assumption. The only perceived logical method of removing these intruding signals is to
have a flexible filter structure that can be tuned to locate the interferences in the channel
and eliminate them where they appear.
The standard method of designing tunable filters would be to precalculate the filter coefficients
that would translate a given filter in frequency to the desired location. However, the
hardware implementation for this method seems like overkill when it comes to designing a
tunable filter. This is because in order to tune the filter over a range offrequencies, the coefficients
that makeup the filter will need to be changed for each distinct frequency to be
tuned to [2]. Imagine the hardware required to store all these coefficients that would enable
the filter to be tuned continuously over the entire band while maintaining the specified frequency
response. For example, assuming our filter is ofNth order with coefficients that are
of 8bit precision. In order to tune to M distinct frequencies from DC upto the Nyquist frequency,
M would therefore represent the number ofROM tables that is required to store the
3
N+1 filter coefficients. Tuning this filter to M distinct frequencies would therefore be limited
by the order of the filter, N, since an increase in order brings about an increase in the
number coefficients which directly translates to an increase of the size of ROM tables
required to store the filter coefficients, making the standard approach highly inefficient for
higherorder filters. It is obvious that a more suitable method is required.
1.3 Scope of Thesis
This thesis introduces a new filter scheme which allows a fixedfilter to be tuned contiously
from DC to the Nyquist frequency using a single tuning parameter. For the purpose of this
thesis, a highpass filter is chosen to provide an important part of this single parameter tunable
filter used for narrowband interference suppression.
This newly proposed tunable notch filter is the first known implementation of the heterodyne
concept and the frequency translation process for active filters suggested by Soderstrand
and Nelson [1][8]. This Fully Tunable Heterodyne Notch (FTHN) filter can be
adjusted or 'tuned' to the appropriate frequency in order to attenuate any NBls resulting
from a single interference source and can also be proven to cancel out all images unavoidably
created during the heterodyne process.
Although the proposed digital notch filter has been mathematically proven to perform as
intended [1], the purpose of this thesis is to verify the hardware implementation of the
FTHN filter using VHDL as the hardware description language along with the Xilinx
XCV800 Series FPGA. As such, this thesis also plays the role of a feasibility study, since
a digital version of this filter has yet to be implemented due to the complexity occurring
from a finite spectrum and not to mention the high sampling rate required for an efficient
4
system. The choice was made for an FPGA implementation owing to the fact that it provides
the flexibility as a test environment and also as a rapid prototyping solution. The successful
implementation could eventually lead to the design being hardwired into an ASIC
or VLSI process in the near future. Hardware description language was used to create a
technology independent design which could be used when targeting different FPGA families
or when converting to an ASIC process.
1.4 Thesis Outline
In Chapter 2 of this thesis, a background review is presented to explore the classic techniques
for interference suppression in spread spectrum communications. The two most
popular methods of interference suppression is discussed in somewhat shallow detail here.
In Chapter 3, modulation techniques are discussed and the heterodyne concept is explored
in some detail to present the basis ofthe tunable structure proposed in this thesis. This chapter
goes through the foundation behind the heterodyne process employed throughout the
entire filter structure.
In Chapter 4, a previous tunable heterodyne filter strucuture is discussed here. The previous
version, a tunable bandpass filter, is made up ofthe basic building block of the FTHN filter
presented in this thesis. Advantages and disadvantages of using the previous structure is
discussed here leading to the proposal of a new and improved system.
In Chapter 5, the FTHNF system is introduced. Three main components that make up the
entire filter are discussed. The chapter explains the workings of the three separate components
that makeup the tunable filter system.
5
In Chapter 6, Matlab simulation data are provided as peliminary results for the proposed
filter. The FTHN filter is divided into 7 stages and MatLab diagrams are provided at each
stage of the structure to simulate the functionality of the circuit and to prove the theoretical
equations [1] that brought forth the idea for the filter system.
In Chapter 7, the structure of the FPGA intended for this design is dissected and inspected
to provide a clear understanding of the platform of implementation chosen for this thesis.
In Chapter 8, Actual hardware implementation data is presented here from experimental
results. These are results provided from the 7 stages that the system was divided into.
Results here are to confirm the intial simulations obtained from MatLab provided in Chapter
6.
In Chapter 9, the final analysis of the proposed system is presented.
In Chapter 10, ideas for future work are presented.
6
2Background
Previous modulation techniques concentrated the power of an informationbearing signal
in a narrowband as compared to the bandwidth ofthe signal before being transmitted. It was
discovered later that this techpique made it easy for the signal to be suppressed or corrupted
by an adjacent NBI signal. A solution to the problem came in the form of spread spectrum
modulation and has been employed ever since [21].
2.1 Spread Spectrum
Spread spectrum is a form of wireless communication modulation technique in which the
frequency of the transmitted signal is deliberately varied, resulting in the bandwidth of the
modulated signal being spread beyond the bandwidth of the modulating signal [6]. This
enables the transmitted signal to occupy more than one possible spectrarIocation and therefore
make signalinterception or frequencyjamming techniques extremely difficult or
highly impractical. The primary use of Spread Spectrum Communications (SSC) is that of
interference suppression and is the lifeline of the mobile communications industry [6].
2.1.1 Interference suppression in spread spectrum communications
Generally, a conventional wireless signal has a frequency that is constant with a particular
bandwidth associated with it. This property allows the signal to be easily located by the
receiver to retrieve the information contained in it. Unfortunately, a signal that is constant
7
in frequency can be greatly disturbed when another signal is transmitted on to or close to
it. To recover the desired signal and its information, frequency modulation techniques will
have to be employed, such as the spread spectrum frequency modulation method. There are
several types of spread spectrum modulation techniques that can be used to remove
unwanted interference signals, but the two most popular techniques in practice are Direct
Sequence (DS) and Frequency Hopping (FH) [6].
2.1.1.1 Direct Sequence
Direct Sequence Spread Spectrum (DSSS) which is also known as Direct Sequence Code
Division Multiple Access (DSCDMA) is a common modulation technique in a coherent
communications system, the information that is to be transmitted is multiplied by a PseudoNoise
(PN) Sequence, which is essentially a pseudo number generator taking on a random
binary sequence (spreading code) [6]. Figure 21 shows the spreading/despreasing procedure
used in this method [15]. This multiplication effectively spreads the wanted signal
across its assigned bandwidth or channel, masking the signal as noise. However, a narrowband
interference signal could still find its way onto this frequency spectrum of the spread
signal. Hence, to eliminate the interference signal, the receiver 'despreads' the wanted
signal and acquires it using the replica ofthe spreading code while this function also effectively
spreads out the interference signal, as shown in Figure 22 [15]. This system however
can result in long acquisition time due to long PN codes used and it also suffers from the
wellknown 'neartofar' problem where transmitters which are closer to the receiving station
can overpower distant transmitters and in effect, destroy their signals [7]. Although this
method is somewhat effective, an NBI signal could still have a relatively highpower associated
with it when it is spreadout at the receiver.
8
At the front end of the receiver, such highpowered signals could drive the operational
amplifier into its saturation (nonlinear) region, preventing the desired signal to be effectively
extracted.
, r1 Channel ~ tV\Vf\~\I
Noisy
Data IDS 1MlJlr Data
PN
Sequence
Figure 21. Spreading/despreading method.
PN
Sequence
nJI (Iwb:tnt! i1;!cril:rcr
spread ~pcctnlln ~lgnul
'~
,PIl:3J spc..:tnllll signal
na>rowb311J intC'I1~'ra
Figure 22. Spectral effects of spreadingldespreading.
9
2.1.1.2 Frequency Hopping
In Frequency Hop Spread Spectrum (FHSS), the frequency of the transmitted signal is randomly
'hopped' around onto a given set offrequencies in an assigned bandwidth or channel
to avoid frequency jamming or interception [6]. The frequency hopping is generated by a
Hopping Code Generator (HCG) which essentially shifts the signal onto a different frequency
randomly. At the receiver end, the hopping code that was used to create the frequency
shifts is replicated and synchronized with the hopping pattern to retrieve the
original transmitted signal. This system requires a complex frequency synthesizer to generate
the frequency hops from m binary digits which are then mapped to one ofN=2m frequencies
in the channel [7].
2.1.1.3 Signal recovery
Any spread spectrum receiver can only suppress a given amount of interference and the
system will not function as desired if the power associated with the interference signal
becomes too great. With the above mentioned techniques, the wanted signal at the receiver
is separated from the unwanted signal with the use of digital signal processing techniques
and algorithms, before further processing is done on the wanted signal. The proposed
FTHN filter can be shown to provide the neccessary means to suppress any NBI signal
appearing at the receiver end before passing the wanted signal to the rest of the receiver,
thereby greatly increasing its effectiveness and not to mention the quality of the received
signal.
10
3The Heterodyne Process
Informationbearing signals have to be modulated before being transmitted through free
space or through a communications channel. The modulation process allows the information
to be transmitted over long distances and typically translates the informationbearing
signal to a new spectral location. It is a neccesary process in communications theory when
transmitting a message signal through freespace in order to have effective transmission
using a reasonablesized antenna. In a communications channel, the modulation process
allows different signals to be transmitted to different spectral locations when more than one
signal can occupy the channel [6]. There are several types of modulation techniques that
can be employed based upon the type of application and the factors that can influence the
transmission. For the purposes of this thesis, we will look at the method known as 'Frequency
Translation'.
3.1 Frequency translation
Any signal can be translated or moved to a new spectral location. This translation process
employs the most widely used modulation technique known as 'heterodyning'.
3.1.1 The heterodyne concept
Heterodyning or 'mixing' is the process oftranslating a signal to a new spectral location by
mixing two frequencies together to produce a different frequency output. In the continuous
11
time domain, this mixing process can be described as a multiplication of two signals with
different frequencies to produce a third signal.
x(t)
Figure 31. Mixer block diagram.
Figure 31 shows the block diagram ofthe heterodyne concept in continuous time. Looking
at the frequency domain, the results ofthis multiplication translates into a shift in frequency
of the original signal. Taking the Fourier Transform ofthe output ofthe multiplication process
produces the following result:
(3.1 )
As can be observed from the above equation, the multiplication in the time domain process
translated the incoming signal to two different spectral locations containing the sum and
difference frequency components of the two input signals. Notice also that the heterodyne
process effectively doubles the bandwidth of the signal with the creation of the two frequency
components, each with the original bandwidth. In the analog domain, bearing in
mind that the spectra is infinite, this effect is acceptable since one of the images can be
safely removed. The basis for the proposed implementation in this thesis has been derived
from this frequency translation concept which is widely applied in radio communications.
12
One ofthe most popular application for this concept appears in the use of superheterodyne
receivers.
3.1.2 Superheterodyne receiver
In the superheterodyne receiver, the incoming signal with frequency ifc) is 'mixed' with a
signal containing the heterodyne frequency ifLO =Ie lif)' This process serves to translate
the input signal which is centered on the carrier frequency,fc to the intermediate frequency,
/;f where the signal is extracted using an appropriate filter before being processed for a
given application. Employing the frequency translation theorem mentioned previously in
section 3.1.1, the local oscillator (LO) is tuned to the frequency at which the input frequency
ifc) is translated into the passband ofthe intermediate frequency filter located at/if
Essentially, we are simply reducing the frequency of the incoming signal which is either
Amplitude Modulated (AM) or Frequency Modulated (FM) by virtue of mixing the signal
with another signal. Figure 33 shows the block diagram of the superheterodyne filter [6].
Radio frequency
(RF) filter and
amplifer.
IF Filter Demodulator 7 Output
Local Oscillator
~   
Figure 32. Superheterodyne receiver block diagram.
13
4Previous Work
A previous implementation of a tunable heterodyne filter was explored and implemented
on a Virtex XCV800 FPGA in a Thesis work by Azam [2]. The Tunable Heterodyne Band
Pass Filter implementation by Azam makes use of a very narrow bandpass filter to isolate
the NBI signal. The range of tunability in this filter is from 0 to 7t/4 and 7tl4 to 7tl2.
4.1 Tunable Bandpass Filter
Various tunable heterodyne bandpass filters implementation using the basic building block
in Figure 41, was discussed by Azam in his thesis work [2]. These tunable bandpass structures
can be characterized by the following transfer function [1]:
(4.1)
x(n) ::~
sin (~n)
Figure 41. Tunable Heterodyne Bandpass Filter basic building block.
15
cos (ct1,u)
sin (~n)
(It~~ yen)
4.1.1 Theory of operation
~kHz
?fkHz
10 12
/\/\
5
(c)
(b)
The operation behind the tunable bandpass structure shown in Figure 41 can be explained
using Figure 42. We assume that the input signal, x(n) contains an undesired sinusoid at
3kHz and desired sinusoid at 5kHz and the fixed filter has a narrow passband centered at
10kHz. The heterodyning frequency, fh (%/21t) required in this case would be 7kHz
(lOkHz3kHz), which would translate the undesired signal into the filter's passband region.
Frequency components on the negative axis are ignored in the following demonstration for
sake of simplicity.
(a)
?[kHz
17 V (h)
(g)
(f)
10 fkHz
(_e_) t_P_SJ_·IV_2_(f)_I I0,7; V >fkHz (VZ A
'L::3,.....L~17::':>~fkHz
(vz
3
Figure 42. Tunable Bandpass Filter operation.
16
W· h h F' c. . . j21tf t j21tfht It t e ouner translonn propertIes of cosme (!e h +!e ) and sine
. f 2 2
j21tf t J21t ht . . . ..
( !je h +!je ), FIgure 42 follows the sIgnal through the block diagram of
2 2
Figure 41 showing the power spectrum plots of the inphase and quadrature components
ofthe input signal traversing the structure. Inphase components are plotted against the real
spectrum axis, while the quadrature components are plotted against the imaginary spectrum
aXIs.
In (a) ofFigure 42, the power spectrum ofthe input signal, x(n) containing frequency components
centered at 3kHz and 5kHz is shown. In (b), we plot VI fonned when we heterodyne
the input signal x(n) with a cosine wave of frequency fh Hz. The positive phasor
j21tfht
portion of the cosine signal ( !e ) will translate the spectral components of the input
2
signal to their new locations shown at 10kHz and 12kHz. In (c), we plot VI fonned when
we heterodyne the input signal with a sine wave of frequency fh Hz, the frequency components
ofthe input signal are translated to 10kHz and 12kHz, except that the translated spectra
lies below the frequency axis due to the negative sign of the positive frequency
j21tfht
(!j e ). In (d) and (e), we see that the spectrum ofV 2 and V2 after the filter Hf, hence
2
the spectral component at 10kHz remains after being filtered with the bandpass filter H(f).
Notice that the resulting spectra are out ofphase with each other. In (f), the heterodyne process
on V 2 translates the filtered signal V3 on the inphase branch to its new spectrallocations
at 3kHz and 17kHz due to the positive and negative phasor portions of the cosine
j21tf t j21tfht ., . .
signal (!e h +!e ). In (g), the sIgnal V2 IS translated to V3, WIth Its new spectral
2 2
locations at 3kHz and 17kHz. With the second multiplication in the time domain, the spectrum
is now plotted on the real axis. The negative amplitude portion of the spectrum at
10kHz will be translated upwards to 17kHz and downwards to 3kHz on the real axis. Due
17
to the positive sign of the negative frequency, and the fact that the spectrum in (e) already
contains the imaginary component,}, the translated signal at 3kHz lies above the frequency
axis, while the translated signal at 17kHz lies below the frequency axis. Finally in (h), U3
and V3 which are both plotted on the real axis are added forming the output yen). Since the
frequency components at 3kHz are inphase and the frequency components at 17kHz are
out ofphase, the summation of these two brances yields only the inphase spectra at 3kHz.
Therefore, the NBI signal was effectively isolated from the desired signal [2].
The circuit of Figure 41 allows a single parameter to be tuned to translate the incoming
interference signal into the center of the bandpass filter via the heterodyne process. The
bandpass filter isolates the unwanted signal before it is translated back to its baseband by
vitrue ofanother heterodyne process. As one might have already guessed, this system however
is not complete, it does not produce the desired signal at the output but serves to 'capture'
the intereference signal instead. The structure can further be used to actually remove
the interference frequency and produce the desired signal at the output at the cost of incurring
some additional hardware. However, the effectiveness of the digital heterodyne process
is clearly visible.
The final transfer function implies that the filters were translated up and translated down
and then added together to produce the end result. Since the filters used were fixed filters,
clearly the uptranslation and downtranslation discussion here is merely a virtual phenomena.
Realistically speaking, the translation process only applies to the incoming signal and
not the filters themselves.
The tunable bandpass filter of Figure 41 can be constructed using highpass filters, lowpass
filters and bandpass filters. The difference between these three filters comes in the
18
range of tunability across the frequency spectrum. Highpass and lowpass filters used in
the design allows the filter to be completely tuned from DC to Nyquist. The bandpass filter's
tuning capability however is divided into two regions: from DC to n/4 and from rrJ4
to Nyquist. The summation of the uptranslated and downtranslated poles and zeros of the
prototype bandpass filter virtually creates 2 bandpass filters in the regions mentioned
above. A similar situation presents itselfwhen using a notch filter as the prototype filter in
the structure.
4.2 Final Analysis
The previous filter structure has several advantages and disadvantages when implemented
as a tunable structure for narrowband interference rejection.
4.2.1 Advantages
From the proposed structure in Figure 41 it can be seen that several types of filters can be
used in the design to implement the NBI extraction from the transmitted signal. Lowpass,
highpass and bandpass filters can be interchanged depending on the type of application.
4.2.2 Disadvantages
Loworder filters proved to be unsuitable for the application as it failed to completely isolate
the interference signal from the desired signal. The solution to the problem of isolating
the interference frequency came in the form of implementing higherorder filters to replace
the ineffective lowerorder filters [2]. It is well documented that higherorder filters require
extensively more hardware and are more difficult to implement. This is because the number
ofcoefficients that makeup the filter increases linearly with the increase in order ofthe fil
19
ter. Since each of the coefficients are implemented as multipliers, considerable hardware
will need to be expended in order to achieve an acceptable frequency response at the output
of the system.
Having a bandpass filter with a center frequency other than 0 (lowpass) or fs/2 (highpass)
can prove to be problematic when dealing with zeros in some cases where the bandpass is
not one that is extremely narrow. Assuming that H(z) has both poles and zeros, H(Z) = B(z)/
A(z), then the problem can be explained using the following equations [1]:
(4.2)
As observed, in equation 4.2, the poles of the filter gets multiplied with each other in the
denominator and translates linearly with respect to the heterodyning frequency, fh, as
expected. However, we have lost control over the zeros ofthe final transfer function as they
are mixed with the poles and zeros in the numerator. With this difficulty ofpredicting and
controlling where the zeros ofthe transfer function will endup, the design of the filter will
20
need to take on a different approach. The transfer function of the separate filter will need
to be somewhat predistorted to end up with the desired overall response when the addition
of the separate tranfer functions take place [1 ][2].
21
5FTHN Filter System
The FTHN filter system is composed of three (3) main components:
1. Splitter
2. Fixedcoefficient prototype filter
3. Combiner
5.1 Splitter
The Splitter component is the first heterodyne unit in the system. The structure is divided
into 2 branches, called the "inphase" and "quadrature" branches respectively. The incoming
signal is split into these branches and multiplied with a cosine wave on the inphase
branch and a sine wave on the quadrature branch; both of which are carrier waves at the
heterodyning frequency. Using the trigonometric identities given by equations 5.1 and 5.2
below and the frequency translation theorem given by equation 5.3, it can be shown that
this multiplication process in the time domain effectively translates the incoming signal to
new spectral locations.
. 1 (+j(Olon) j(Olon))
sm(w n) =  e  e
o 2j
22
(5.1 )
(5.2)
(5.3)
Figure 51 shows the Splitter implementation. The frequency domain function of the Splitter
can be explained .using equations 5.4 and 5.5.
x(n)~
Figure 51. Splitter circuit
1x( zejcoon) + 1x( zejcoon)
2 2
(5.4)
(5.5)
As observed in equations 5.4 and 5.5, the input signal is translated to a pair of new spectral
locations after being passed through the splitter. The locations of these spectra are determined
by the heterodyning frequency, fo '
23
5.2 Fixedcoefficient prototype filter
For the initial implementation, a firstorder fixedcoefficient IIR filter will be used to study
the feasibility of using a loworder filter to provide the necessary filtering needed for the
system to function as required. The choice for an IIR filter instead of the more stable FIR
was made to take advantage ofthe sharp transition band property associated with IIR filters.
We can effectively design a low order IIR filter with sharp transition band rolloffs as compared
to an FIR filter with the same characteristics which would greatly increase the order
and the hardware required. This sharp transition band property of an IIR filter enables the
system to effectively isolate and simultaneously remove the interfering signal while trying
not to compromise any part of the wanted signal components. Logically, a notch filter
seems to be the appropriate choice for this implementation.
5.2.1 Why implement a notch filter?
NBI signals are signals which often times have most, if not all their power concentrated in
a very narrow band. These signals occupy a very small portion in the frequency domain but
have strong enough power contained within itself to corrupt nearby signals. The removal
of these signals therefore becomes tricky situation when they appear on or nearby the
desired signal. This is because it leaves us with the difficulty of designing a filter that is
broad enough to isolate the entire interefering signal yet narrow enough as to not remove
any other wanted components around or under it.
The notch filter implementation with a very narrow stopband was chosen to provide the
most suitable method of removing these NBI signals without removing the original infor
24
mation that was being transmitted. However, to obtain a notch filter, a highpass filter was
used in the structure. The question then arises as to why implement a highpass filter in the
structure instead ofjust a plain notch filter? It can be shown that by using a fixed highpass
filter in the structure, we can successfully create via frequency translation, a notch filter that
does exactly what we intended to do, that is to remove the unwanted signal.
5.2.2 Filter selection
The highpass filter was selected as the fixedcoefficient protoype filter for the structure
since its virtual translation in the frequency domain will produce a notch filter centered at
the desired frequency. An example ofthis translation effect is illustrated in Figure 52. This
effect can also be described by equations 5.6 and 5.7 as the translation on the zplane ofthe
transfer function H(z).
As mentioned before, the filters used in this structure are fixedfilters and not adaptive ones.
The intended purpose ofusing fixedfilters is to show that instead ofmoving the entire filter
system to the signal as one would expect, here, the signal is moved/translated to the fixedfilters
to perform the filtering processes. However, looking at the final transfer function of
the system, one could argue that the filter itself is being translated, which is not true.
Finally, after filtering, the intended signal is then moved back to its baseband.
25
r
IH(z)1
highpass filter
ro=o
IH(z)1
r
.... ,.,
...
translation by  roo translation by + roo
f(Hz)
notch filter
f(Hz)
Figure 52. Virtual translation in frequency of a highpass filter.
(
j (00 + 00 ))
H(z, (00) = H ze 0 (5.6)
Equation 5.6 shows an 'up' translation, while Equation 5.7 shows the 'down' translation of
the transfer function. This 'up' or 'down' translation depends on whether we are moving
anticlockwise or clockwise on the unit circle. The explanation for this phenomena comes
from the fact that when sampling a real signal, the frequency response of the filter repeats
every sampling frequency (periodic). Therefore, a lowpass or highpass filter can be converted
into a notch filter simply by translating the filter transfer function as shown in equation
5.6 and 5.7 on the unitcircle.
26
(5.7)
Equation 5.8 below shows the firstorder filter equation designed for this implementation.
The design was based on the fact that the 3db bandwidth of the stopband was to be as
narrow as possible. We will assume for the purposed of this thesis that a 500Hz stopband
region for the highpass filter will be sufficient to remove a given narrowband signal, since
the stopband doubles to 1000Hz when frequency translation occurs. The following equation
produces a firstorder highpass filter with a flat passband and a 3db stopband width of
500Hz.
k(Zl + 1)
H(z) = , where k = 0.9683 and r = 0.9366
I 1 rz
(5.8)
Using Direct Form II implementation, the filter structure is obtained and shown in Figure
53.
0.9683 x(n) :> yen) T IzI ]+1
<
0.9366 0.9683
Figure 53. Direct Form II implementation of a firstorder highpass filter
27
5.3 Combiner
The Combiner is the final component in the FTHN filter structure. The combiner multiplies
the incoming signal by a cosine (inphase branch) and sine (quadrature branch) and the
resultant outputs of the multiplication process are then added together.
Signals passing through the system will create images when multiplied with a sine or cosine
signal. Each multiplications with a cosine translates the signal to two different frequencies
but the signal components still hold on to their original phase relationship. Each multiplication
ofthe incoming signal with a sine wave translates the signal to two different frequencies
but inverts the phase of one of the signal component,>. This phenomena is taken
advantage of in this structure and is critical in removal of images created via the heterodyning
process throughout the filter. Figure 54 shows the structure ofthe combiner circuit.
Itt~ yen)
Figure 54. Combiner circuit.
The combiner acts the same way a splitter circuit functions via frequency translation. However,
the combiner circuit serves to bring its input signal back to baseband after multiplica
28
tion with cosine and sine. The output ofthe combiner is simply the addition of its inphase
and quadrature branches as shown in equation 5.9.
(5.9)
5.4 The Complete FTHN Filter System
The complete system for the Fully Tunable Heterodyne Notch (FTHN) Filter is given in
Figure 55.
SI roon
b] f]
Cj i}
x[n] y[n] e2
on i2
C2
sm roon b2 sinroon f4
sin roon
cos roon
Figure 55. Fully Tunable Heterodyne Notch Filter
There is a noticable doubleedge effect of using this structure as shown in equation 5.10
and proven in Appendix A which shows that although the signal is being moved/translated
to the filter, the final equation gives the impression that the 'fixed' filter itself is actually
being translated in frequency. This is the main advantage of using this structure.
(5.10)
29
As the final transfer function of the system, equation 5.10 also shows that although the
system is made up of nonlinear components (variable multipliers) , the output of the filter
is completely linear to the single tuning parameter, fo.
5.4.1 Theory of Operation
The operation behind the fully tunable hetrodyne notch filter structure shown in Figure 5
5 can be explained using Figures 56, 57 and 58. We assume that the input signal, x(n)
contains an undesired sinusoid at 3kHz and desired sinusoid at 5kHz and the fixed highpass
filter has a narrow stopband of 500Hz. The heterodyning frequency, fh (ffitl/21t)
required in this case would be 3kHz, which would translate the undesired signal into the
filter's stopband region. Frequency components on the negative axis and amplitude
changes are ignored in the following demonstration for sake of simplicity.
(a) r~A A =>'kHz XI\'3 5
(b)
0 2 /6\ /8\ ?;kHz
(c) PSjla2(f)1
6
2 fkHz
(d) r~1
/\ /\ 2 6 8 >fkHz
Figure 56. Fully Tunable Heterodyne Notch Filter operation (part I).
30
(e)
fkHz
9 11 ~kHz /\ /\
2
(f)
(g)
(h)
(k)
(I)
(m)
2
5
/\/\ 6 8
9 11 v v
fkHz
=rkHz
=rkHz
fkHz
=rkHz
Figure 57. Fully Tunable Heterodyne Notch Filter operation (part II).
31
32
1 j 27tfht 1 j 21tfht ( 2:j e + 2:j e ), Figure 56, 57 and 58 follows the signal through the block diagram
of Figure 55 showing the power spectrum plots of the inphase and quadrature components
of the input signal traversing the structure. The inphase components are plotted
against the real spectrum axis while quadrature components are plotted against the imaginary
spectrum axis.
In (a) of Figure 56, the power spectrum of the input signal, x(n), containing frequency
components at 3kHz and 5kHz is shown. In (b), we plot al formed when we heterodyne the
input signal x(n) with a cosine wave offrequency fh Hz. The positive phasor portion ofthe
cosine signal ( !ej21tfht) will translate the spectral components ofthe input signal to their
2
new locations shown at 6kHz and 8kHz while the negative phasor portion of the cosine
j21tf t
signal (!e h) will translate the spectral components of the input signal to their new
2
locations shown as 0 kHz (DC) and 2kHz. In (c) we plot a2 formed when we heterodyne
the input signal with a sine wave of frequency fh Hz. The frequency components of the
input signal are translated to 6kHz and 8kHz, except that the translated spectra lies below
the frequency axis due to the negative sign of the positive phasor portion of the sine wave
j21tfht j21tfht
(~e ). The positive sign of the negative phasor portion ofthe sine wave ( ~je )
however translates the input signal components to OkHz (DC) and 2kHz and causes these
signal components to lie above the frequency axis when the heterodyne operation is performed.
In (d), we plot bl formed when the signal components in (b) are passed through the fixed
highpass filter with a 3dB stopband width of 500 Hz. The signal component at DC has
been removed by the stopband of the filter while the other components remain since they
33
are clearly within the passband region. In (e), we plot bz formed when the signal components
in (c) are passed through the fixed highpass filter with a 3db stopband width of
500Hz. Again, the signal component at DC has been removed while the other components
of the signal remain intact.
In (t), we plot cl formed when we heterodyne the signal components in (d) with a cosine
wave of frequency fh Hz. Again, the positive phasor portion of the cosine signal
j21tfht
(!e ) translates the signal components in (d) to 5kHz, 9kHz and 11kHz, while the
2
jZ1tfht
negative phasor portion ofthe cosine signal ( !e ) translates the signal components
2
in (d) to 3kHz and 5kHz. In (g), we plot Cz formed when we heterodyne the signal components
in (e) with a since wave of frequency fh Hz. With the second sine multiplication in
the time domain, the resulting spectrum is now plotted on the real axis. Signal components
in (e) are translated to 5kHz, 9kHz and 11kHz and lie below the frequency axis due multijZ1tf
t
plication with the positive phasor portion ofthe sine signal (!je h). Signal components
2
in (e) are also translated to 3kHz and 5kHz due to multiplication with the negative phasor
j21tfht
portion of the sine signal (!je ). As observable in (g), the signal component at 5kHz
2
subsequently will be cancelled after translation due to heterodyning.
In (h), we plot e2 formed when signal components from (t) and (g) are added together. This
addition process results in the elimination of signal components at 9kHz and II kHz, leaving
behind signal components at 3kHz and 5kHz. In (i), we plot d1 formed when we hetrodyne
signal components in (d) with a sine wave offrequency, fh Hz. Signal components in
(d) are translated to 5kHz, 9kHz and 11kHz due to the multiplication with the positive
j21tfht
phasor portion of the sine wave ( !je ), while signal components at 3kHz and 5kHz
2
are the results of the multiplication in the time domain with the negative phasor portion of
34
j21tfht
the sine wave (!j e ). As observable in (i), the signal component at 5kHz subsequently
2
will be cancelled after translation due to heterodyning.
In U), we plot d2 formed when we heterodyne signal components in (e) with a cosine wave
j 21tfht
of frequency fh Hz. The postive phasor portion of the cosine wave (!e ) will translate
2
the signal components at 2kHz to 5kHz, 6kHz to 9kHz and 8kHz to 11kHz respectively.
j21tfht
The negative phasor portion ofthe cosine wave ( !e ) will translate the signal com
2
ponents at 6kHz to 3kHz and 8kHz to 5kHz respectively. In (k), we plot the summation of
(i) and U) which leaves us with frequencies at 3kHz and 5kHz.
In (1), we plot f} formed when we heterodyne signal components in (k) with a sine wave of
frequency fh Hz and in (m), we plot f2 formed when we heterodyne signal components in
(h) with a cosine wave offrequency fh Hz. In (n), we plot the addition ofsignal spectra from
(1) and (m). In (0), we plot f3 formed when we heterodyne signal components in (k) with a
cosine of frequency fh Hz and in (P) we plot f4 formed when we heterodyne signal components
in (h) with a sine of frequency fh Hz. In (q), we plot the subtraction of the spectra in
(0) from the spectra in (P) resulting in frequencies at DC, 2kHz and 8kHz.
In (r), we plot the resulting spectra when signal components in (n) are passed through the
fixed highpass filter with a 3dB stopband of500Hz and in (s), we plot the resulting spectra
when signal components in (q) are passed through the fixed highpass filter.
In (t), we plot i} formed when we heterodyne signal components in (r) with a cosine offrequency
fh Hz and in (u), we plot i2 formed when we heterodyne signal components in (s)
with a sine of frequency fh Hz. Finally, in (v), we plot the resulting spectra when signal
35
components in (t) are added to signal components in (u). As observed, the intereference frequency
designated at 3kHz have been eliminated from the system along with any images
created through the heterodyne process.
36
6MatLab Simulations
In this chapter, we will go through the simulation of the proposed system using MatLab to
verify that the FTHN filter functions as predicted at each stage of the system.
A combination of two input signals of frequency 3kHz and 5kHz, sampled at 48kHz are
used to immitate an NBI signal and a desired signal respectively. The goal here is to remove
that interference signal at 3kHz without affecting the desired signal component at 5kHz.
For purposes of clarity, we will break up the FTHN Filter structure into stages and use the
MatLab plots to describe the functionality of the system. Figure 61 shows the stages in the
FTHN Filter structure.
y[n] :
output'
\
Combine~
Stage 2 \0
sin coon
, in!
.(f '
I •
sumrcal
l
Filter \
Stage 2 \ ,
I"
t ,~, ,'n2 \
\sumimaj
+
cossin I
(/# rpswnl=sum4
( coscosl " 7! ", .I
" I !' Wo$ L I: . .
cosout2
~,
,'\
:1 si
, I
sin WoTI i : !
: I : cos Wool sinwon
, i '"o(X)rf' , /.. ,I, ,j! I '
Splitter : rilter j:' Splitter / Injerm4diate Combiner
Stage 1J Stage 1 Stage 2 /' S i • ,Stage 1
/ ' J"I' /I' tp.ge \ ' ,.j I' sinoutt.A:::: /' . ft/ \
. 12 /' Slncos! "" 3
smou.£;:: sinsin!L~ ~ sum2=sum
Figure 61. Stages of the FTHN Filter stJucture
37
Figure 62 shows the block diagram of Splitter Stage 1. Figure 63 shows the time domain
plot of the input signal added with a random noise component and its corresponding 512
point normalized power spectrum plot.
I I :
cosoutl
Input signal__::>~ Splitter ~_~
. ..~ sinoutl
Figure 62. Block diagram of Splitter Stage I.
Input Signal
100 200 300 400 500 600
2 L__' '__' ' '__'
o
F F T 0 F THE IN PUT S IG N A L
O,,.,,r, I::r'1\1,vM~(VlNrfVVf\~~·,"i(\~yf,1
05 1 5 2 2.5
Frequency ,
x 10
Figure 63. Time and frequency domain represent<!tion of the input signal.
Figure 64 shows the normalized power spectrum plot ofsignals cosoutl and sinoutl which
are outputs signals from Splitter Stage 1.
38
Output of the first Splitter
0.5 1.5
60 L ' ' L. ' I
o
Frequency 4
X 10
Or~__.__,______r......,
1:: ~1/~~t~~r~l~
~ 60 ' " ' ' L '
o 0 5 1.5 2 2.5
Freque ncy
Figure 64. Normalized Power spectrum plot of cosoutl and sinoutl.
At this stage, the signals cosoutl and sinoutl are then passed to Filter Stage 1, which is the
1st order IIR highpass filter discussed in Chapter 5. The highpass filter was designed to
have a 3dB cutoff frequency of 500Hz which provides a narrow stopband region. Figure 6
5 shows the block diagram of the highpass filter system when input signals cosoutl and
sinoutI are passed through it. This operation produces output signals cosout2 and sinout2
respectively. Figure 66 shows the magnitude vs frequency plot of the 1st order IIR highpass
filter. Figure 67 shows the normalized power spectrum plot of signals cosout2 and
sinout2 coming out of Filter Stage 1.
39
COSOUtl::>3'>'I__H_(_Z_)_....:::>~ cosout2
sinoutl =:>~i'_H_(Z_)J=:>~sinout2
Figure 65. Block diagram of Filter Stage 1.
0
10
20
en :s
8 30
::> :eOl
<II
E
40
50
60
0 0.5 1 1 5
Frequency (kHz)
2..5 x 10
Figure 66. Magnitude response of IIR highpass filter with 3dB cutoff frequency of 500Hz.
40
Output signal after the 1st high pass filters
0
CD
~ I I II
~ 20 'I I II :J
0
ViiVV~vr\~J 'v1jvfy\~~, t,~'Y'~I l\!/V\l~hA~ I ~
~ u
C/)
a. 40 '\ I III ~
"0 I \ \
Ql I I
.!!l
"iii
E 60 0z
0 0.5 1.5 2 2.5
Frequency
x 10
4
0.5 1.5 2 2.5
60 ''''''
o
Frequency
Figure 67. Nonnalized power spectrum plot of signals cosout2 and sinout2.
After Filter Stage 1, the outputs cosout2 and sinout2 are passed through Splitter Stage 2.
Figure 68 shows the block diagram of the resulting outputs obtained from passing input
signals cosout2 and sinout2 into Splitter Stage 2. Figures 69 and 610 shows the normalized
power spectrum plot of the outputs of Splitter Stage 2.
cosout21
~ cossinl
Splitter
> coscosl
>1 I :sinsinl
sinout2 Splitter
sincosl
Figure 68. Block diagram ofSplitler Stage 2.
41
Output
0.5 1 .5 2 25
I I ,
\ '( J~N1J1WINAvvf,)JV\fy!',/'''i( \lW~'"
10
:)3..
£ 20 ] ~v
~ 40
.~
(ij g 60 '__L '__' '__l
z 0
Frequency 4
X 10
0...,...,
Frequency
Figure 69. Nonnalized power spectrum plot of signals cossin I and coscosl.
Output
0.,.,.,
I::'vW~r WI~A1~1rV~'r~;~1fr
(; 60 '__' '__J. '__l
z 0 0.5 1.5 2 2.5
Frequency 4
X 10
Frequency 4
X 10
Figure 610. Nonnalized power spectrum plot of signals sinsin I and sincosl.
42
The output signals from Splitter Stage 2 are then passed to the Intermediate Stage. Figure
611 shows the block diagram of the resulting outputs obtained when passing the output
signals from Splitter Stage 2 through the Intermediate Stage. Figure 612 shows the normalized
power spectrum plot of the output signals emerging out of the Intermediate Stage.
cossin1
sincos1
coscos1
sinsin1
__$1==:::::~
111=:>~sum2
Figure 611. Block diagram of Intermediate Stage.
The output signals from the Intermediate Stage is then passed to Combiner Stage 1. Figure
613 shows the block diagram of the resulting outputs obtained when the output signals
from the Intermediate Stage is passed through Combiner Stage 1. Figure 614 shows the
normalized power spectrum plots of the output signals from Combiner Stage 1.
43
Output
0
co
J:!.
E 20
:J
II)
aC./.) /'1 I~ "" 40 ~ (J.
.~ I .
'" I (
E0
z 60
0 0.5 1.5 2 2.5
Frequency 4 x 10
0
co IJr J:!.
~ 20
:J
I~f JYVWI~\(r,A, II) ~ C/) a..
"" 40
51
~
E0
z 60
0 0.5 1.5 2 2.5
Frequency x 10 4
Figure 612. Normalized power spectrum plot of signals sum1(=sum4) and sum2 (=sum3).
sum] :1 Combiner > sumreal
sum2
sum3 :1 Combiner I :> sumimaj
sum4
Figure 613. Block diagram of Combiner stage I.
44
Output
0
1D
~
~ 20 \~ ,v{w~rrJ{II~if\ 1/'{fVl1}·W1/J\ ~~ E
'e"n \l\~
(J)
ll. 40 g
en rn
E 60 0z
0 0.5 1.5 2 2.5
Frequency x 104
0
'co
E
'E
'e"n
(/J
Cl.
"Q)
.!Il
iii § 60 ' L L ' ...l. '
z 0 0.5 1.5 2 2.5
Frequency
Figure 614. Normalized Power spectrum plot of signals sumreal and sumimaj.
The signals sumreal and sumimaj are then passed through Filter Stage 2. Figure 615 shows
the block diagram of Filter Stage 2. Figure 616 shows the resulting normalized power
spectrum plots of output signals in] and in2 coming from Filter Stage 2.
sumreal.....:>~I H(z)
sumimaJ~i=>:;;.1 H(z)
Figure 615. Block diagram of Filter Stage 2.
45
=:>~ inl
__....::>~ in2
Output
0
CD
~
~ 20
(/)
Gal
.!!l 40
~
c;
z 60
0
0
0.5
Frequency
1.5 2 2.5
x 10'
2.5
x 10'
1.5 2
Frequency
05
60 ''''''
o
CD
1:: l¥f\fAI" !rVVYMyff\V\\A~IV1Mv!~
c;
z
Figure 616. Nonnalized power spectrum plot of signals inl and in2.
Finally, the signals in} and in2 are passed to Combiner Stage 2. Figure 617 shows the
block diagram ofCombiner Stage 2 and Figure 618 shows the resulting normalized power
spectrum plot of the output signal.
in}
in2 ___:::~I Combiner If==;>~ output
Figure 617. Block diagram of Combiner Stage 2.
46
Final 0 utput
o I I
10
11
iii ·20 II
~ I'\~ ifJI\ tit/ilil! ~\J\\ 'i \~hNIIJ\\'~' 1\ '11 ~
Q. ;;
0 30 (J)
ll.
j
§ ·40 r ~ i II I V' ~ \1 I ~ 1 \1 \ 'f! 0z
·50
60
0 o 5 1.5 2 5
Frequency x '0.
Figure 618. Normalized power spectrum plot of the output signal.
As observed in Figure 618, the simulated NBI signal of 3kHz appears to have been
removed from the system, leaving behind only the desired signal at 5kHz, as expected.
6.1 Filter translation
The following section details the MatLab simulation ofthe virtual translation of the fixedcoefficient
IIR highpass filter in frequency. Figure 619 shows the original frequency
response of the highpass filter with a 3dB cutoff frequency of 500Hz prior to translation
in the frequency domain.
47
'0
~
o r:::===~~~~, (
s I
i
20
 2 S0'"0'Sc:",',,,'Sc::='2 S
Frequency (kHz) x 10 4
Figure 619. Frequency response or 1st order highpass rilter with 3dB cutorr at 500Hz.
Figure 620 shows the polezero plot of the 1st order highpass filter prior to translation in
the frequency domain.
···tr..·
!
./'
\ i
\ i
" . I:
.....,',.... j
...., .......... 1
.._~.
\,
\
'.
, \ i '
I l
··..!······t·..><tp.... 
!
0.8
0.6
0.4
0.2
0a. 0 :!! 
<1l a. N 02
0.4
06
08
,
1 O.S o
Real Part
o S
Figure 620. Polezero plot of original IIR highpass filter prior to translation.
48
Figure 621 shows the filter 'uptranslated' in the frequency domain by the heterodyning
frequency of 3kHz. Observable is the fact that the highpass filter turns into a notch filter
centered at 3kHz with twice the bandwidth of the stopband region as compared to the highpass
filter.
o .
50
100
en
:!!!. ! 150
~E
 2 00
 2 50
 300 ''"''' o 05 1 15 25
Frequency (k H z)
Figure 621. Filter uptranslated by 3kHz.
i;
!
i
t
i
oc· :..~
1
0 a.
<l> c:
~'" 0.2
0.4
0.8
02
0.4
0.6
0.8
0.6
1 0.5 o
Real Part
0.5
Figure 622. Polezero plot of highpass filter uptranslated in frequency.
49
Figure 623 shows the highpass filter 'downtranslated' in frequency by the heterodyning
frequency of 3kHz and its relative polezero plot is shown on Figure 624.
0
50
100
~
<D , 50
~
~
E
200
250
300
 2 5 2 , .5 ,
Frequency (kHz)
0.5 o
)( 10.to
Figure 623. Frequency response of highpass filter downtranslated by 3kHz.
, ..._..
08
0.6
0.4
0.2
o _ __..__1 .______ _ _. . ._._ __. .__._
(5
a.
Q)
c:
til
2 0.2
0.4
0.6
0.8
1
1 0.5 o
Real Part
0.5
Figure 624. Polezero plot of filter downtranslated by 3kHz.
50
Finally, the final transfer function of the entire system essentially creates a notch filter centered
about the heterodyning frequency, which is 3kHz. Figure 625 shows the frequency
response plot of the filter derived from the final transfer function in equation 5.10 of Chapter
5.
o ._ ,' ~:,, .".. '"
50
100
CD
~
~ 150
:>
"1§
Ol co
E
 2 00
2..5 x 10
1 1.5
Frequency (kHz)
:::L._' ' " ' 1
o 0 5
Figure 625. Final position of translated filter.
0.8
0.6
0.4
0.2
<5
0..
Q) 0
c: co
fr 0.2
0.4
0.6
0.8
1
.:....._
....  1 ........
,.,/r" .._......
/// "",..
/ \
/ ;~
, \
I.._..__L ~
i !
\ /
\ xiJ
'\ ././,/
"'....
....~ //
~_.__._~..'
I
1 0.5 o
Real Part
0.5
Figure 626. Final pole and zero positions of translated filter_
51
The plots shown in Figures 625 and 626 proves that the FTHN filter system appears to
have been translated in frequency in order to eliminate the interference frequency at 3kHz.
It is essential to understand that the filter system did not and cannot translate in frequency.
In actuality, the undesired signal was translated into the stopband region of the filter,
thereby removing it from the transmitted signal. Any and every image created through the
heterodyning process have also been eliminated.
52
7Hardware Choice
The platfonn for the hardware implementation of the FTHNF structure discussed in this
thesis was chosen to be Field Programmable Gate Arrays (FPGA's). The implementation
of the design using FPGA's was chosen since it allows for rapid prototyping and with its
relatively quick tumaround time, it proves to be an appropriate solution for the initial
scratchwork before the design is to be fabricated. Advancements in programmable logic
devices families have enabled FPGA's to be used as a viable option for implementation of
DSP algorithms and filter structures in the market today. This is primarily due to the fact
that the the device can be attainable offtheshelf and its functionality can be changed onthe
fly. For the purpose ofthis thesis, we will be discussing the structure ofthe Virtex 2.5V
XCV800 Programmable Gate Arrays obtained from Xilinx which is used to test the design
presented.
7.1 Field Programmable Gate Array (FPGA)
An FPGA is a prefabricated programmable logic device which allows logic implementation
by electrically programming the interconnects and personalizing the basic cells within the
confines of the user's laboratory. It provides, for many applications, an adequate number
oftransistors in a single chip package for the functional blocks, switches for the routing network,
and the memory capacity to control both. There are 4 main categories of FPGAs in
the commercial market today: symmetrical array, rowbased, hierarchical Programmable
53
Logic Device (PLD) and seaofgates. The difference between these structures is in the
chiplevel architecture, granularity of the function unit, method of programming and the
interconnection structure [9]. Currently there are four technologies in use which are: static
RAM cells, antifuse, EPROM transistors, and EEPROM transistors. Depending upon the
application, one FPGA technology may have features desirable for that application [8]. The
device can implement a given Circuit by electrically programming its interconnects and by
configuring the functionality of its basic cell structure [5]. The ease of reprogrammability
coupled with its hardware emulation status makes the FPGA and ideal choice for any hardware
implementation. In the next section, a brief overview of the architectural components
of the chosen FPGA is introduced.
7.2 Xilinx XCV800 FPGA structure
A Virtex 2.5V FPGA is basically madeup of 3 components:
1. Configurable Logic Blocks (CLB) which enables the construction of the purposed logic
functions.
2. Input/Output Blocks which contribute as the interface between the FPGA and the outside
world.
3. Block SelectRAM which complement the LUTs in the CLB.
These components are connected to each other via the programmable interconnects contained
within the FPGA package [4].
54
7.3 Configurable Logic Blocks (CLBs)
The basic underlying structure ofan FPGA is in its CLB's. Each CLB is made up of4 Logic
Cells (LC), each ofwhich includes a 4input function generator/Lookup table (LUT), carry
logic and a storage element. As a note, the Virtex architecture is actually divided into
smaller parts known as 'Slices'. Each CLB contains 2 Slices. Figure 71 shows the Virtex
CLB [4].
7.3.1 Function GeneratorlLookUp table (LUT)
The function generators available in the Virtex series FPGA are implemented as 4input
LUTs. Each LUTs therefore serves the purpose of storing the truth table for the desired
implementation ofup to 4 variables or when combined, can implement the truth table of up
to 6 variables. These LUTs can also be configured to serve as synchronous 16xlbit
Random Access Memory (RAM) or when combined, can also implement a 32x Ibit RAM
(or a 16x2bit RAM) [4].
7.3.2 The Arithmetic Logic
Each CLB contains dedicated carry logic to provide fast arithmetic carry capabilities
needed when implementing highspeed arithmetic functions. The Virtex CLB supports 2
separate carry chains, one per Slice. The dedicated carry path can also be used to cascade
function generators for implementing wide logic functions [4].
55
7.3.3 Storage Elements
Each Slice in the Virtex CLB contains 2 storage elemens which can be configured as Dtype
flipflops or as levelsensitive latches. The inputs to the D flipflops can be driven
either by the function generators within the slice or directly from slice inputs, bypassing the
va
tt,. X~
rt.... "
tt' ya
r+?y
CIN
function generators [4].
cour
I'B
t,.1 Y (,4
c:,~ c.~
(;1 YO r.?
C;I <it
flY
'.9
r« X r.
rJ r:
2 :<:0 r.
" rl
ax
tL'(t I
CI"
Figure 71. 2 Slice Virtex CLB
\'jll
CA .,
CQ
{',I
DY
''''
""
"
YQ
Figure 72. Detailed view of the Virtex Slice.
56
7.4 Input/Output Blocks
The Input/Output Blocks (lOBs) in the Virtex Series FPGA provide and interface between
the external package pins and the internal logic of the FPGA. Each ofthe lOB controls one
package pin and can be configured for Input, Output or Bidirectional signals. Figure 73
shows the simplified block diagram of the lOB [4].
f
(;(>1
Er,f1';,) li
CC
::,Tl >+401
(;1.1<>........... '
1',,;[ ':> '
Figure 73. Virtex Input/Output (VO) Block
7.5 Block SelectRAM
>",,+,6._<I'AD
Virtex FPGAs incorporate several large Block SelectRAM memories. These Block SelectRAMs
complement the distributed LUT SelectRAMs that provide shallow RAM structures
implemented in CLBs. Each Block SelectRAM cell is a fully synchronous dualported
4096bit RAM with independent control signals for each port [4].
57
7.6 CLB Configuration
To configure a FPGA for a given application, the design needs to be translated into configuration
data. The configuration data is obtained by converting the netlist produced during
the design stage into a bitstream file using a recognized development software for the given
device. The CLBs are then configured by loading the bitstream file into the internal configuration
memory. The method of configuring the FPGA determines the type of bitstream
file. FPGAs can be configured by a PROM. The serial PROM is the most common. The
FPGA can either actively read its configuration data out of external serial or byteparallel
PROM (master mode), or the configuration data can be written into the FPGA (slave and
peripheral mode) [8]. Since the device Virtex XCV800 device is based on the SRAM technology,
the configuration bits are stored in the RAM. The outputs ofthe RAMs controls the
switches which implements the connectivity and functionality of the design in hardware.
58
8Hardware Implementation
We will begin the discussion of the hardware implementation of the FTHN filter system
with the 8bit sine and cosine generator followed by the 8bit 2's complement registeredmultiplier.
These 2 components are the foundation of the entire heterodyne filter structure
presented in this thesis.
The structures discussed in this Chapter have been implemented using two separate reconfigurable
logic tools. A thirdparty synthesis tool from Synplicity called Synplify Pro was
used for the frontend portion of the design phase and compared to the integrated tool provided
by Xilinx, called Foundation Series. For the backend portion of the design phase,
the integrated development tool from Xilinx was used to map, place and route and configure
the design onto the FPGA chip. Along the course of this chapter, a comparison of the 2
reconfigurable logic tools is provided to demonstrate the hardware reduction capable when
using Synplify Pro for the frontend phase as compared to the Xilinx integrated tool. This
is due to the fact that the synthesis tool perfonnance ofSynplify Pro greatly overweighs the
perfonnance of the integrated development tool from Xilinx [12].
59
8.1 Sine/Cosine Generator
The Sine/Cosine generator functions to produce both sin(8) and cos(8) simultaneously for
multiplication with the incoming signal. Theta (8) for the sine and cosine values were precalculated
using the following expression [II]:
8 = 21t. n
2m
n = # of samples per period
input width (m) = log2(n)
(8.1 )
and stored in a Lookup Table (LUT). Theta (8) in equation 8.1 represents all values in radians
for n number of samples needed to represent a sine or cosine wave of one period. These
values are converted into mbit, twos complement numbers and stored in the LUTs.
For the purposes of this thesis, we've opted to have 64 samples to represent an entire sine/
cosine wave. Since the sine wave values trails the cosine wave values by 90° (a quarter
wave), we can produce both the sine and cosine values simultaneously from these 64 sampIes
simply with the use of multiplexers. This is because these 64 samples are actually
divided into 4 lookup tables containing 16 (24) samples, equivalent to a quarterwave, of
the precalculated values of sin(8) and cos(8) within the sine/cosine generator structure. A
simple 6bit (4bits for addressing and 2bits for multiplexer control) counter can be used
to address the 64 sample values and at the same time provide the control logic to produce
the sample values out of the separate sine and cosine branches. Figure 81 shows the block
diagram of the sine/cosine generator structure.
60
sm(S) cos(S)
[5]
[3:0] ,
A B C D 16 samples )
[4]
Figure 81. Sine/Cosine generator
The frequency of the sine and cosine signal produced by the sine/cosine generator is determined
by its input frequency and the total number of samples per period, n, stored within
the structure. The following equation relates the heterodyning frequency, fh, to the input
frequency of the sine/cosine generator, from:
from = fh • n
where n=64 in this case
(8.2)
Figure 82 shows the synthesized circuit for the sine/cosine generator using Synplify Pro.
61
~"
, ,
4' A.,'·
Figure 82. Synthesized sine/cosine generator circuit using Synplif)' Pro.
8.2 8bit 2's Complement Multiplier
The next significant part ofthe splitter and combiner structures is the multiplier circuit. The
multiplier in the FTHN filter system functions to multiply an incoming signal with the
output from the sine/cosine generator at the heterodyning frequency, fh. This operation
immitates the analog mixer circuit commonly found in many analog communication struc
62
tures. Since the output of the sine/cosine generator and the incoming digital signal are in
2's complement format, we'll have to design a 2's complement multiplier to perform the
multiplication process, To do so, we can easily convert an 8bit signmagnitude multiplier
into an 8bit 2's complement structure to serve as required, at the cost of some hardware
increase which is trivial. Figure 83 shows the block diagram for the proposed 8bit, 2's
YI15:0]
00000o
AI7J XORBI7! '_!
=YI15]
00000
0000
A[7]
"
A[7:0]
2', Comp BI7:0)
BI7J
complement multiplier.
B[7:O)
Figure 83. 8bit 2's complement multiplier block diagram,
8bit registers were then placed at inputs and output ofthe 8bit 2's complement multiplier
in order to ensure synchronization between the values produced by the sine/cosine generator
and the incoming signal. The resulting structure was implemented using Synplify Pro
63
for the frontend phase of the design. Figure 84 shows the the 8bit, 2's complement multiplier
created using Synplify Pro.
Figure 84. 8bit, 2's complement multiplier implementation using Synplify Pro.
8.3 Splitter
The Splitter circuit serves to split the incoming signal into 2 branches which is the inphase
branch and the quadrature branch. This structure functions to multiply the output signal
from the sine/cosine generator which is at the heterodyning frequency, fh, with any incoming
signal to produce the sum and difference frequencies between the two signals. Aprevious
implementation places the sine/cosine generator within the Splitter circuit which would
64
imply that a sine/cosine generator is incurred for each Splitter or Combiner in the circuit
[2]. Since the heterodyning frequency produces both a sine and a cosine for any desired frequency,
considerable hardware can be saved by making the sine/cosine generator explicit
to the Splitter and Combiner circuits. This way, only one sine/cosine generator would be
needed for the entire FTHN filter system. Figure 85 shows the block diagram ofthe splitter
circuit.
hnts> from sine/cosine genera\2r  8bit 2's Complemern
Multiplier ~
gnat, x(n)
 8bitM2'uslCtipolmieprlement  hnts) from sine/cosine generattrr
cos(27tf
Inputsi
sin(21tfi
Figure 85. Block diagram of the Splitter circuit.
Figure 86 shows the Splitter circuit implemented using Synplify Pro. Input ports insin and
incos shown in Figure 86 represents the connection to the sine and cosine output ports of
the sine/cosine generator respectively. As mentioned before, there is no need to duplicate
the sine/cosine generator for each Splitter or Combiner component in the FTHN filter
system resulting in considerable savings in terms of hardware.
65
:0
mult8
~2!!!l~t=>C'~Ia; A[7 0]
~i}lL:QL~""='118[7 0] Y[ 150]1....::.:..::.!>~~~L!..J:!~
split3
mult8
A[7.0]
~2§.LLJll':;:»':":'=>":"':'::18[7: 0] Y[15 O]~~l11:.!!ffi~~!lliQI:::::
split2
Figure 86. Synthesized Splitter circuit using Synplify Pro.
8.4 Fixedcoefficient Prototype Filter
As mentioned before, the firstorder highpass filter can be described using the following
transfer function:
1 k(z 1)
H(z) = , where k = 0.9683 and r = 0.9366
1
Z r
(8.3)
It is obvious from Equation 8.3 that the coefficients k and r will need to be implemented
using fixed multipliers. Assuming an 8bit number implementation, the closest binary representation
of the two coefficients are as follows:
k= 0.1111100 = 0.96875
r = 0.1111000 = 0.93750
66
To implement the these coefficients directly, the k coefficient would require 4 adders, while
the r coefficient would require 3 adders. However. a more hardwareefficient implementation
ofthese multipliers can be obtained using the Canonic Sign Digit (CSD) representation
of the coefficients coupled with the DempsterMcLeod (OM) method for constant integer
multiplication using a minumum adders. The CSD representation of k and rare:
k = 1.0000(1)00 = 1_(25
) = 0.96875
4 r = 1.000(1)000 = 1(2 ) = 0.93750
To further explain the implementation ofthese coefficients as fixed multipliers, lets assume
that our 8bit input is given as X. Therefore, the multiplication of our input X with either k
or r can be described as:
5 5 kX = (l  2 )X = X  (2 )X
4 4 rX = (l  2 )X = X  (2 )X
where (25)X is simply the binary input shifted 5 decimal places to the right and (24)X is
the binary input shifted 4 decimal places to the right.
Figure 87 shows the block diagram of the 1storder highpass filter implementation. Each
adder/subtracter in Figure 87 is made 13 bits wide in order to accomodate the shifted bits
in the structure. The final output, Y, is truncated to 8bits.
67
aces
[12:0]
[7:0]
[7:0J & "00000" [12:0)
( Shifted 5 decimal pi
to the right
(+) ()
[12:0]
I
() (+)
[12:0]
I Z' I
(+) (+)
[12:0]
~Shifted 4 decimal
places to the right
4 LSBs "fallofr'
Y(z) (+) ()
X(Z)
Figure 87. Block diagram of 1storder highpass filter
Figure 88 shows the 1storder highpass filter implementation using Synplify Pro.
68
Figure 88. Synthesized 1st order highpass filter using Synplify Pro,
8.5 Combiner
The Combiner structure multiplies incoming signals with the outputs of the sine/cosine
generator at the heterodyning frequency, fh, and subsequently sums the results created from
the multiplication process. Figure 89 shows the block diagram of the Combiner structure.
cos(27tfhnl,;) from sine/cosine genera or
8bit 2's Complemen
Multiplier 1..
Input signal, Xl (n)::3'"i
Input signal, x2(n)3;o.l
8blt 2's Complementf__J
Multiplier
sin(27tfhntJ from sine/cosine genera r L '
Figure 89. Block diagram of Combiner.
69
y(n)=x 1(n)cos(21tfhnl,;)
+ x2(n)sin(2ltfhnl,;)
Figure 810 shows the Combiner structure implemented using Synplify Pro.
mult8
[§s~in~ei[6jn([7::QjOl::::>f!..!.f'Di!L' !t~''''Y A17:0j '11":
~in~S~in~e[[7:~ol::::>:'o"l.~ :.~.":l...'18[7:01 Y[15:0.......:..:.:;,..:.....:.:.L.......
comb2
mult8
~c~os~in~e~ing[7~:olr2>::I\:~! :'.:~.Il A17:01
l!!in~c£.:Os~in~el!(7~:O·LJ ~,.;.;.:'''"''i_....;,~.c:&.'1 8[7:01 Y[150 ':;'
comb3
Figure 810. Synthesized structure of Combiner using Synplify Pro.
8.6 Final Structure
"'ol', combouU7:01
"r1 ':
The final structure of the Fully Tunable Heterodyne Notch Filter is shown in Figure 811.
ON<
Figure 811. Final synthesized structure of FTHN filter using Synplify Pro.
70
8.7 Resource Usage
The following tables lists the resource usage for each of the implementations mentioned in
this Chapter. A comparison between Xilinx and Synplify Pro is shown to further stress the
efficiency of using Synplify Pro's synthesis tool compared to the integrated development
tool offered by Xilinx. Table 81 compares the slice count for the sine/cosine generator and
the multipler.
Table 81. Resource usage comparison for sine/cosine generator and multiplier.
Component # of Slices using Xilinx's Foun 1:1 of Slices using Synplicity's
dation Series Synplify Pro
Sine/Cosine generator 36 31
8bit 2's complement Multiplier 54 53
(Total 1:1 of Slices) 90 84
Table 82. Resource usage comparison for FTHN filter components.
Component # of Slices using Xilinx's Foun # of Slices using Synplicity's
dation Series Synplify Pro
Splitter 103 106
HighPass Filter 22 34
Combiner 115 108
(Total # of Slices) 240 238
Table 83. Resource usage comparison for entire structure.
Component # of Slices using Xilinx's Foun f:I of Slices using Synplicity's
dation Series Synplify Pro
Fully Tunable Heterodyne Notch 1073 817
Filter (Total # of Slices)
71
9Final Results
9.1 Experimental Results
The Fully Tunable Heterodyne Notch (FTHN) filter structure was implemented using the
Xilinx Virtex 800 family FPGA chip. This section provides the setup and the analyses of
the final results obtained as compared to the simulation results shown earlier in Chapter 6,
using MatLab.
9.1.1 Experimental Setup
The FTHN filter structure was downloaded and configured through a PC parallel port onto
a Xilinx XSV800 V1.1 board. This board contains the Virtex 800 FPGA chip embedded
in a framework for processing video and audio signals [13]. The board also has the capabolity
of processing stereo audio signals with up to 20 bits of resolution and a bandwidth of
20 KHz using its AK4520A stereo codec, which is external to the FPGA. This option
allows us to input an analog signal from a function generator which will then be converted
into a bit stream by the codec for use by the FPGA [14]. This conversion process is controlled
via the interface shown in Figure 91. The interface aids in transforming the incoming
analog signal into a serial bit stream for use by a particular design contained within the
FPGA chip. The serial bit streams produced when an analog signal is digitized will be syn
72
chronized with a clock from the FPGA that enters the codec on the SCLK signal shown in
Figure 91 [14].
.. mclk
In
Virtex
Ird<. In_ AK4520A
FPGA .. sdk Codec ~ ... .. sdm out 
~~  sdout O1.1  ~ ..
Stereo Jad<.
(J1)
Stereo Jack
(J2)
Figure 91. Interface between codec and FPGA on the XSV800 Vl.l board.
However, in order for the interface between the FPGA and the codec to work accordingly,
a handshaking module will need to be instantiated within the highlevel vhdl code for the
design. This handshaking module creates the necessary control signals shown in Figure 9
1 above, in order for the codec to perform the proper AnalogtoOigital (NO) or Digitalto
Analog (0/A) conversions.
The output of the design was recorded using the HP Logic Wave Logic Analyzer. In order
to observe and compare the power spectrum plots obtained from the experiments with those
obtained using MatLab, these 8bit output values were first converted to its equivalent fractional
numbers before performing a 512point Fast Fourier Transform (FFT) on them. The
postFFT values were then normalized on the magnitude dB scale and plotted against frequency
to obtain the Power Spectrum vs. Frequency plots. Figure 92 shows the power
spectrum plot of the input signal.
73
Experimental Results
0
\0
.. 20 a
<ii
'[ 30 ....:.: 0
Cl
CIl "" 40
50 J0
\
0.5
Frequency
1.5 2
4
X 10
Figure 92. 512 point, normalized Power spectrum plot of the input signal.
As shown in Figure 92, the input signal contains frequency components at 3kHz and 5kHz,
represented by the two signal tones. The true average noise power for the signal is clearly
around 35dB which is sufficient for an analog signal that has been digitized for use. This
means that the SignaltoNoise (SNR) ratio of the digitized input signal is clearly at an
acceptable level.
74
Output of Sine/Cosine Generator
Orrr~,.r.,
5
10
15
iii'
~.. 20
.;";;
8 25
<J
" ...
'<; 30
Cl
C/J
""' 35
40
45
'I!'
~~~~
4
X 10
I 1.5 2
Frequency
0.5
50 ''''''
o
Figure 93. 512 point, normalized Power spectrum plot of the heterodyning signal.
For the purposes of this thesis, the tunable heterodyning frequency, fb, was set at 3kHz.
Figure 93 shows the 512point power spectrum plot of the sine/cosine signal tone at the
heterodying frequency. We can see from the diagram that the true average noise power of
the signal is well below 45dB. This proves that the sine/cosine generator implementation
was highly successful in producing the required signal tone at the heterodyning frequency.
75
Experimental Results
0
10
20
S ·30
0
c: .0:;
'
0
Cl ·40
C/J ""'
50
60
70
0 0.5 1.5 2
Frequency
x 10 4
Figure 94. 512 point, nonnalized Power spectrum plot of signal sinoutl.
Figure 94 shows the 512point power spectrum plot of signal sinoutl. Signal sinoutl is
essentially the spectrum resulting from the product ofthe input signal and the sine signal at
the heterodyning frequency (3kHz). The resulting frequency components are at 2kHz,
6kHz and 8kHz as expected. The true average noise power is about 50dB.
76
Experimental Results
O,,...,r~____,
10
20 r: N~~ ~ \\~
Q.
50
60
1 1.5 2
Frequency
0.5
70 ''~''~''
o
Figure 95. 512 point, normalized Power spectrum plot of signal cosout I.
Figure 95 shows the 512point power spectrum plot of signal cosoutl. Signal cosoutl is
essentially the spectrum resulting from the product of the input signal and the cosine signal
at the heterodyning frequency of 3kHz. The resulting frequency components are also at
2kHz, 6kHz and 8kHz as expected. The true average noise power is about 50dB.
77
Experimental Results
0,,.,...,
10
20
N
:l g
~ 30 IV
o
C/J ""
40
50
4
X 10
1 1. 5 2
Frequency
0.5
60 L.. ' ' ' ~'__~
o
Figure 96. 512 point, normalized Power spectrum plot of signal sinout2.
Figure 96 shows the 512point power spectrum plot resulting from passing signal sinoutl
through the prototype highpass filter. The frequency components at 2kHz, 6kHz and 8kHz
remain due to the characteristics of the highpass filter. Here, the true average noise power
is about 35dB. The increase in the noise power level can be attributed to ?
78
0
)0
20
'::J
'S"l
0<> 30
'0
0
til "'"
40
50
60
0 0.5
Experimental Results
) 1.5
Frequency
2
Figure 97. 512 point, nonnalized Power spectrum plot of signal cosout2.
Figure 97 shows the 512point power spectrum plot resulting from passing signal cosoutl
through the prototype highpass filter. The frequency components at 2kHz, 6kHz and 8kHz
remain due to the characteristics of the highpass filter. The true average noise power is
about 35dB.
79
Experimental Results
O,r~~',,,,
5
10
.~
8 IS
'o
Cl g;
20
25
I 1.5 2
Frequency
0.5
30 ' J ..........l ..........l ' .....J
o
Figure 98. 512 poinl, normaized Power spectrum plot of signal cossinl.
Figure 98 shows the 512point power spectrum plot of signal cosout2 after being heterodyned
with the sine signal at the heterodyne frequency. Initially, signal cosout2 contained
frequency components at 2kHz, 6kHz and 8kHz. After the heterodyne operation, the resulting
signal cossinl, shown above, contains frequency components at 1kHz, 3kHz, 5kHz,
9kHz and 11kHz respectively.
80
Experimental Results
0
10
·20
;;;
8
8'"
'0c
on
0
40
50
60
0 0.5 1 1.5 2
Frequency x 10 4
Figure 99. 512 point, nonnaized Power spectrum plot of signal coscos1.
Figure 99 shows the 512point power spectrum plot of signal cosout2 after being heterodyned
with the cosine signal at the heterodyne frequency. Initially, signal cosout2 contained
frequency components at 2kHz, 6kHz and 8kHz. After the heterodyne operation, the
resulting signal coscosl contains frequency components at 1kHz, 3kHz, 5kHz, 9kHz and
11 kHz respectively.
81
Experimental Results
0
5
10
~
<.)
5 .<..II 15 0
CI
v.>
"'" 20
25
30
0 0.5 1 1.5 2
Frequency x 10
4
Figure 910.512 point, norrnaized Power spectrum plot of signal sincosl.
Figure 910 shows the 512point power spectrum plot of signal sinout2 after being heterodyned
with the cosine signal at the heterodyne frequency. Initially, signal sinout2 contained
frequency components at 2kHz, 6kHz and 8kHz. After the heterodyne operation, the resulting
signal sincosl, shown above, contains frequency components at 1kHz, 3kHz, 5kHz,
9kHz and 11kHz respectively.
82
Experimental Results
0
10
20
5 ~ ~
....~. 30 1~ln~ Iv ~ N 0
Cl
00 "'"
40
50
60
0 0.5 I 1.5 2
Frequency x 10 4
Figure 911. 512 point, normaized Power spectrum plot of signal sinsinl.
Figure 911 shows the 512point power spectrum plot of signal sinout2 after being heterodyned
with the cosine signal at the heterodyne frequency. Initially, signal sinout2 contained
frequency components at 2kHz, 6kHz and 8kHz. After the heterodyne operation, the resulting
signal sinsinJ, shown above, contains frequency components at 1kHz, 3kHz, 5kHz,
9kHz and 11kHz respectively.
83
Experimental Results
0
10
20 ~
§
.: 30
0
0
en
"'"
40
50
60
0 0.5 1 1.5 2
Frequency
x 10 4
Figure 912.512 point, normaized Power spectrum plot of signal sum!.
Figure 912 above shows the 512point nonnalized power spectrum plot of signal suml.
Signal suml was obtained from the subtraction ofsignal cossinl from signal sincosl. This
subtraction process yielded the two original input frequency components of3kHz and 5kHz
respectively. The true average noise power level here is about 35dB.
84
Experimental Results
I I.S 2
Frequency
0
10
20
] 30
''" 0
6l 40
Q.,
50
60
70
0 0.5
Figure 913. 512 point, normaized Power spectrum plot of signal sum2.
Figure 913 above shows the 512point nonnalized power spectrum plot of signal sum2.
Signal sum2 was obtained from the addition ofsignal coscosJ and signal sinsinJ. This addition
process yields the two original input frequency components of3kHz and 5kHz respectively.
The true average noise power level here is about 45dB.
85
0
5
10
15
"fi 20
.~.. 25 ~ 0
GJ 30
l>.
35
40
45
50
0 0.5
Experimental Resulls
I 1.5
Frequency
2
Figure 914. 512 point, nonnaized Power spectrum plot of signal sumreal.
Figure 914 above shows the resulting power spectrum plot of signal sum] and sum2 after
being passed through a combiner stage. Essentially, signal sum] was heterodyned with a
sine at the heterodyning frequency and signal sum2 was heterodyned with a cosine signal
at the heterodyning frequency. The result of these two heterodyning process is then
summed to produce signal sumreal which is shown above.
86
Experimental Results
0
10
20
... § 30
§
''"
0 0 40
CIl
"
50
60
70
0 0.5 1 1.5 2
Frequency
x 10
4
Figure 915. 512 point, normaized Power spectrum plot of signal sumimaj.
Figure 914 above shows the resulting power spectrum plot of signal sum3 and sum4 after
being passed through a combiner stage. Essentially, signal sum3 was heterodyned with a
cosine at the heterodyning frequency and signal sum4 was heterodyned with a sine at the
heterodyning frequency. The result of these two heterodyning process is then subtracted to
produce signal sumimaj which is shown above.
87
Experimental Results
Or,,,,,C
10
20
30
5
'o
o
~ 40
50
60
0.5 1.5 2
70 ''''''
o
Frequency
Figure 916. 512 poinl, nonnaized Power spectrum plot of signal inl.
Shown in Figure 916 above is the power spectrum plot of signal inl. Signal inl was
obtained from passing signal sumreal through the second prototype highpass filter stage.
88
Experimental Results
O.,.r....
10
20
50
1 1.5 2
Frequency
0.5
60 '"'"''
o
Figure 917.512 point, nonnaized Power spectrum plot ofsigna1 in2.
Shown in Figure 917 above is the power spectrum plot of signal in2. Signal in2 was
obtained from passing signal sumimaj through the second prototype highpass filter stage.
89
Experimental Results
• x 10
1.5 2
Frequency
0.5
70 'l._' ' '__.J
o
60
0rr.,.,
50
20
10
&. 30
S..o.. o
~ 40
"'
Figure 918. 512 point, normaized Power spectrum plot of signal output.
Figure 918 shows the final power spectrum plot ofthe output signal obtained after passing
two input signals having frequency components 3kHz and 5kHz through the Fully Tunable
Heterodyne Notch Filter system. Clearly observable is the the fact that the designated interference
frequency component of 3kHz has been completely removed from the spectrum.
Also noticable from the PSD plot of Figure 918 is that the true average noise power level
at the resulting output of the system is about 40dB. This proves that a digital version of a
Fully Tunable Heterodyne Notch Filter structure can be successfully and efficiently implemented
using FPGAs.
90
1OFuture Work
The Fully Tunable Heterodyne Notch (FTHN) filter system discussed in this thesis has
been proven to be effective in the complete removai of narrowband interference signals
stemming from a single source. Results for the 8bit implementation discussed in this thesis
prove to be sufficient to provide the necessary elimination of the narrowband interference
signal in the channel.
10.1 Adaptive Heterodyne Notch Filter
An adaptive version ofthe filter system discussed in this thesis can be implemented to provide
automatic tracking and removal ofany narrowband interference signals in the channel.
The Least Mean Squared (LMS) algorithm is a fine candidate to be employed in implementation
of a completely adaptive version of the proposed filter system. Since the implementation
requires the removal of narrowband interference signals from broadband signals, the
algorithm can be used to calculate the error between the two signals and hence, the gradient
which will then be used to update the tuning parameter ( roo )ofthe tunable filter. In short,
the LMS algorithm can be used to drive the heterodyne signal frequency needed to translate
the interference signal to the stopband of the notch filter, but the filter itself maintains its
position in frequency.
The conversion of a tunable filter to an adaptive one can be done by slaving the tunable
filter to a simple secondorder adaptive notch filter [17][ 18][ I9]. Figure 101 shows the
91
basic block diagram of the secondorder notch filter used [20]. The incoming signal containing
a mixture ofthe wanted and unwanted signal would be fed into the inputs ofthe tunable
filter and the adaptive notch filter. The purpose of this secondorder notch filter is to
produce the required parameter (a) which moves the notch to the required location of the
interfering frequency and at the same time is subsequently mapped to the heterodyning frequency,
fh needed to tune the tunable filter. Figure 102 shows the complete Adaptive Heterodyne
Notch (AHN) filter system [17]. Thus, it is evident that we need an adaptive filter
to transform our tunable filter into an adaptive one. Perhaps the possibility transfonning a
tunable filter into an adaptive one without the use of another adaptive filter could be the
topic for another thesis.
2nd  order Notch Filter LMS Adaptive Circuit
MSB (sign bit) Only
Input
Ibit line
8bit line
16bit line
Figure 101. Basic block diagram of secondorder adaptive notch filter
92
In
~ Fully Tunable  Heterodyne Notch
Filter
11\
 ROM ~ D/A veo
I

2nd order
Adaptive
put ... Notch
~ Filter
Figure 102. Complete Adaptive Heterodyne Notch Filter.
10.2 CORDIC algorithm
The much needed sine and cosine functions used in the system were implemented via lookup
tables. However, a new method of calculating the sine and cosine functions for a particular
frequency can be used to replace the lookup table method used in this thesis. The
COordinate Rotation DIgital Computer (CORDIC) algorithm calculates the angle of sine
and cosine using phasors to yield sin(e) and cos( e) [10][ 16]. This implementation requires
the use of barrelshifters to calculate the angles required to produce a sine or cosine at the
required heterodyning frequency, fh. For an FPGAbased implementation however, this
implementation may prove to consume considerable hardware but may provide a more efficient
implementation for VLSIbased architectures.
93
t 0.3 Multiplesource Interferences
The filter system discussed in this thesis involves the attenuation of intereferences stemming
from a single source. It is highly likely that several interference sources could corrupt
the transmission channel at any given point in time and will need to be attenuated before
the desired signal is to be extracted.
One course of implementation would be to try and cascade the system discussed in this
thesis in order to attenuate each interference up to a certain number. However, simple cascading
of the structure discussed in this thesis will not work. A suitable method of attenuating
more than one NBI signal is by using adaptive filtering techniques attributable to
Kwan and Martin [22]. This method can be further refined to reduce hardware complexity
by modifying the gradientsearch algorithm employed in the structure[23].
With the capability to remove from 3 upto 10 interference sources from a channel, the hardare
implementation of this modified KwanMartin structure is a suitable thesis subject.
94
Bibliography
[1] Nelson, Karl E. Development and Analysis ofan Adaptive Heterodyne Filter, PhD
Thesis, University of California Davis, California, 2001.
[2] Azam, Asad. Hardware Implementation of Tunable Heterodyne BandPass Filters,
MS Thesis, Oklahoma State University, Stillwater, 200 1.
[3] Mundra, Pritpal S. et aI, Radio Frequency Interference  An Aspect For Designing A
Mobile Radio Communication System, IEEE transactions, 1992.
[4] Xilinx. The Xilinx Data Book 2000. Xilinx, Inc., San Jose, CA. 2000.
[5] Pak K. Chan & Mourad, Samiha. Digital Design using Field Programmable Gate
Arrays, Prentice Hall, NJ 1994, pp 113.
[6] Ziemer, R.E & Tranter, W.H. Principles of Modern Communications  Systems.
Modulation, and Noise, Third Edition, Houghton Mifflin Company, 1990, pg. 569.
[7] Jachimczyk Withold. Spread Spectrum, http://www.ece.wpi.edu/courses/ee535/
hwk1Icd95/witeklwitek.html
[8] Virtual Computer Corporation, http://www.vcc.com/fpga.html
[9] Oldfield, John V. and Dorf, Richard C., Field Programmable Gate Arrays: Reconfigurable
Logicfor Rapid Prototyping and Implementation ofDigital Systems, 1994.
[10] Andraka, Ray, A Survey of CORDIC algorithms for FPGA based computers, Proceedings
of the 1998 ACM/SIGDA sixth international symposium on Field programmable
gate arrays, Feb. 2224, 1998, Monterey, CA. pp191200
[11] Xilinx Product Specification, Sine/Cosine Look Up Table V1.0.2, Logicore, San
Jose, CA, 95124, October. 1999.
95
[12) Matveev, M., Evaluation ofthe RTL Synthesis toolfor PWIFPGA Design,
http://wwwcollider.physics.ucla.edu/cms/trigger/talksiO 108Rice /
Matveev_SYN2001.pdf, RICE University, August 10,2001.
[13) Xess Corporation, XSV800 Virtex Prototyping Board with 2.5V, 800,OOOgate
FPGA, http://www.xess.com/prodOI4_4.php3
[14) Xess Corporation, XSV8oo Board VI.I Manual, http://www.xess.com/manuals/
xsvmanualvl_1.pdf
[15) Poor, Vincent H and Rusch, Leslie A., Narrowband Interference Suppression in
Spread Spectrum CDMA., IEEE Personal Communications Magazine, Third Quarter
1994., pp.1427
[16) Yu Hen Hu, CORDICbased VLSI architecture for Digital Signal Processing, IEEE
Signal Processing Magazine, July 1992.
[17) Soderstrand, et. aI, FPGA Implementation ofAdaptive Heterodyne Filters, Proceedings
34th IEEE Asilomar Conference on Signals Systems and Computers, Pacific
Grove, California, Volume 1,2000, pp.375 378
[18) K.E. Nelson, P.V.N. dao and M.A.Soderstrand, A Modified FixedPoint Computational
Gradient Descent GrayMarkel Notch Filter Methodfor Sinusoidal Detection
and Attenuation, IEEE International Symposium on Circuits and Systems, Hong
Kong, China, June 1997.
[19) K.E. Nelson and M.A. Soderstrand, Adaptive Filtering Using Heterodyne Frequency
Translation, Proceedings 40th IEEE International Midwest Symposium on
Circuits and Systems, Sacramento, CA, August 1997.
[20) M.A. Soderstrand, Adaptive Filters, ECEN5050.377 Lecture Notes, Department of
Electrical and Computer Engineering, Oklahoma State University, OK.
[21) Ziemer, Roger E. and Peterson, Roger L. Introduction to Digital Communication,
2nd Edition, Prentice Hall, pp.562573.
[22) Kwan, T and Martin, K, Adaptive detection and enhancement ofmultiple sinusoids
using a cascade IIRfilter, IEEE Transactions. Circuits and Syst., pp. 937945, July
1989.
96
[23] Soderstrand, et. aI, Suppression of multiple narrowband interference using realtime
adaptive notch filters, Circuits and Systems II: Analog and Digital Signal Processing,
IEEE Transactions on, Volume: 44, Issue: 3 , March 1997, pp.217 225.
97
Appendix A
Fully Tunable Heterodyne Notch Filter Derivation
Part of the contents of this appendix was obtained from Karl Nelson's Thesis [I] and completed
here.
el
COS~ H ~ca;%n f
Cl f1 gl Hf
hi ~ il
x[n] f, yn] sin~ ~ 12
Hf C2 + Hf
sin~ ~ sin~
J~ cos~ sinman f4
(~
[ ( jroo) (jroo)~
bI (z) = ~H(Z) X ze + X ze IJ
98
\ ( jOO
o
)[ (2j
OO
O
) ] (jOOO)[ ( 2
j
C\(Z)=4Hze Xze +X(z) +~Hze X(z)+Xze O°O)]
\ ( jOO
O
)[ (2
j
OOO) ]. (jOOO)[ (2j
c2(z) = 4H ze X ze X(z) + ~H ze X(z)X ze OO°)]
(
jOO)[ ( 2
j
dl(z) = ~H ze ° X ze OO°) +X(z)] 4T\ H( zejOO°)[X(z)+X(ze2joo0)]
1 ( jOOO)[ (2
j
d OOO) ] \ ( jOOO)[ 2jooo ] 2(z) = 4T H ze X ze X(z) + 4TH ze X(z)X(ze )
e l (z) = d
2
(z)  d
l (z)
e 1 ( jOOO) \ ( jOOO) l (z) =  2jH ze X(z) + 2jH ze X(z)
(
~H ze2jOOO)X(zejOOO)  4\H(z)X(jzOe OO)  4\H(z)X(zjeOOO) +
[1(z) = . .
1 ( 2JOOO) ( JOOO)
4H ze X ze
(
~H ze 2jOOO)X(jzOe OO) + 41H(z)X(jzOe OO) + 41H(z)X(zjeOOO) +
[ (z) =
2 ~H( 2joo" ( jOO) ze O)X ze °
99
I ( 2
j
COO) ( jCOO)
( jco ) ( jCO)  4j H ze X ze + 4
1j
H(z)X ze ° 4
1j
H(z)X ze ° +
[3(z) =
I ( 2
j
COO) ( jCO) 4j H ze X ze °
I ( 2
j
COO) (jCOO) I ( jCOO) I (JCOO 4}H ze X ze + 4}H(z)X ze 4}H(z)X ze ) 
[4(z) =
1 ( 2
j
COO) ( jCO) 4jH ze X ze °
I ( 2j
COO)
( jCO) (2j
CO IV( jCO) gl(Z)=2Hze Xze O+~HZe °r~ze °
1 ( 2
j
COO) ( jCOO) I ( 2
j
g2(z) = 2jH ze X ze  COO) ( jCOO)
2j
H ze X ze
I [( 2
j
COO) (jCOO) (2
j
hi (z) = 2H(z) H ze X ze + H ze COO) X( zejCO° )]
I [( 2
j
CO) (jCOO)
( 2
j
h CO) ( jCO)] 2(z) = 2jH(Z) H ze ° X ze H ze ° X ze °
I ( jCOO)[ ( 3
j
COO) (2
j
. 4H ze H ze X ze COO) + H(zjeCOO)X(z)] t
1( (z) =
(
jCO)[ ( jCO) ( 3
j
CO) ( 2
j
~HZe ° Hze °X(z)+Hze °Xze CO0 )]
(
jco )[ ( 3
j
CO) ( 2
j
. ~H ze ° H ze ° X ze CO° )H(zjeCOo)X(z)] t
12(Z) =
(
jCO)[ ( jCO) ( 3
j
CO) ( 2
j
~H ze ° H ze ° X(z) + H ze ° X ze CO0 )]
(
jCOo) ( jCOo) Y(z) = H ze H ze X(z)
100
VITA
Dhinesh Sasidaran
Candidate for the Degree of
Master of Science
Thesis: HARDWARE IMPLEMENTATION OF A FULLY TUNABLE HETERODYNE
NOTCH FILTER IN FPGA
Major Field: Electrical Engineering
Biographical:
Personal Data: Born in Sandakan, Malaysia on January 27th, 1975, the son of
Stanley Sasidaran and Kanniammal.
Education: Graduated from High school in Malaysia; received an associate degree
from an affiliated school in Subang Jaya, Malaysia, as part ofOklahoma
State University twinning program; received a Bachelor's of Science
degree in Electrical Engineering with Computer option from Oklahoma
State University, Stillwater, Oklahoma in May 1999. Completed the
requirements for the Master of Science degree with a major in Electrical
Engineering at Oklahoma State University in May 2002.
Experience: During the Master degree worked as a Research and Teaching
Assistant with the Department of Electrical Engineering at Oklahoma
State University, 1999 to present.