INTERCONNECT DESIGN WITH LARGE
TRANSISTOR CONSTRAINTS FOR
MULTICIDP MODULES AND
LARGE DIE SOI/SOS
By
JIEWEN
Bachelor of Science
Huazhong University of Science and Technology
WuHan, China
1989
Submitted to the Faculty of the
Graduate College ofthe
Oklahoma State University
in partial fulfillment of
the requirements for
the Degree of
MASTER OF SCIENCE
May, 1998
INTERCONNECT DESIGN WITH LARGE
TRANSISTOR CONSTRAINTS FOR
MULTICIDP MODULES AND
LARGE DIE SOI/SOS
Dean of the Graduate College
11
ACKNOWLEDGEMENTS
This study was conducted to develop a set of general design guidelines and
perfonnance estimation equations of long interconnects for highspeed multichip
modules and large die SOVSOS applications. Analysis and simulation results are
presented. A novel layout for transistors with large width is also developed.
I wish to express my sincere appreciation to my major advisor, Dr. Chriswell
Hutchens for his intelligent supervision, constructive guidance and inspiration. My
sincere appreciation extends to my other committee members Dr. Louis G. Johnson and
Dr. Scott Shepard. I would like to thank the Naval Ocean Surveillance Command for
providing the research opportunity and financial support to this project.
Moreover, I wish to express my sincere gratitude to my colleagues who provided
suggestions and assistance for this study.
I would also like to give my special appreciation to my wife, Li Zhou, for her
strong encouragement at times of difficulty, love and understanding throughout this
whole process. Thanks also go to my parents for their support and encouragement.
Finally, I would like to thank the Department of Electrical and Computer
Engineering for supporting during these years of study.
111
Chapter
TABLE OF CONTENTS
Page
1. INTRODUCTION.. . .. . . .. . .. . .. .. . .. 1
1.1 Objective................................................................................ 3
1.2 Organization. . . .. .. . .. ... . .. . .. ... . . .. .. . .. . . .. .. . ... .. . .. . .. . .. . . . . .. . .. . .. . .. . .. . .. ... . 5
2. EXTRACTION OF R. L, C AND 20................. 7
2.1 Transmission Line. . . .. . . .. .. . .. . . . ... ... .. . .. . .. . .. . .. ... . . . . .. . ... .. . ... .. . .. .. . .. . .. . . .. 7
2.2 Selection ofMaterial for the Substrate................................................. 9
2.2.1 Effective Dielectric Constant of Substrate. 9
2.2.2 Selection ofMaterial of Substrate. .. 10
2.3 Extraction of Self Capacitance and Inductance of Microstrip ,.... 11
2.3.1 Calculation of Self Capacitance (pF/cm) and inductance
Microstrip(nH/cm)........................................................... 11
2.3.2 Properties of Self Capacitance and Inductance of Microstrip. 12
2.3.3 Comparison of Self Capacitance on Insulating Substrate and on
OxidePassivated Silicon Substrate........ 14
2.4 Extraction of Self Resistance (nlcm) ofMicrostrip. .. . . .. . .. . .. ... . .. .. . . .. . .. . 15
2.4.1 Calculation of Sheet Resistance. . . .. . .. . . .. .. 15
2.4.2 Skin Effect....................................................................... 16
2.4.2.1 Calculation of Resistance with Skin Effect. . . .. .. . .. ... . .. ... . .. .. .. 16
2.4.2.2 CutoffFrequency. 17
2.5 Computation of Characteristic Impedance 20 (n)... 18
iv
2.5.1 Characteristic Impedance Zo of Transmission Line.. 18
2.5.2 A Comparison ofthe Microstrip Characteristic Impedance on
Different Substrates. .. . . .. . .. . .... ... .... .... ... .. . .. .. ... .. .. ...... . .. . .. . .. .. 19
2.6 Points of.Design.................................... 21
3. DESIGN OF TRANSMISSION LINES 23
3.1 Lossless, Lossy and Fully Lossy Transmission Line.......................... ...... 24
3.1.1 Definition of Lossless, Lossy and Fully Lossy Transmission Line.... . . 24
3.1.2 Characteristic ofThree Types of Transmission Line...................... 25
3.2 Optimal Delay Design ofA Transmi.ssion Line..................................... 27
3.2.1 First Incidence Voltage..... 28
3.2.2 Lumped RLC Model for a Lossy Transmission Line 29
3.2.3 The Delay Estimation for a transmission line............................... 32
3.2.4 Delay Factor Sensitivity Analysis.............. .. 34
3.2.5 Oscillation of Series RLC Circuits............................................ 35
3.2.6 Optimizing the Delay........................................................... 37
3.3 Peripheral Parts' Effect on Interconnection Performance.......................... 39
3.4 Loss of Transmission Line '" 41
3.5 PSPICE Simulation of Tran.smission Line Signal Delay 43
3.6 Points ofDesign. 46
4. DESIGN CONSIDERATIONS TO ELIMINATE SELF GENERATED NOISE... 48
4.1 Reflection Noise " .. . .. . 49
4.1.1 Series Termination.............................................................. 49
4.1.2 Optimal Resistor Value ofTermination. 51
4.1.3 Signal Termination Simulation................. 54
4.2 Driver Size Design........... .. ... 56
4.2.1 Driver Size Estimation Model. , ... . 56
4.2.2 Simulation and Discussion. . ... .. . .. . .. .. ..... .. 58
v
4.3 Crosstalk.................................................................................. 62
4.3.1 Calculation of Crosstalk '" .. 63
4.3.2 Simulation of CrossTalk..... .. .. . .... . 67
4.3.2.1 The Accuracy ofMathematical ModeL......... 68
4.3.2.2 CrossTalk Vs. Spacing Between Two Signal Lines. 69
4.3.2.3 CrossTalk Vs. TenninationResistance '" 71
4.3.2.4 CrossTalk Vs. Transmission Line Driver Size ,....... 72
4.3.2.5 CrossTalk Vs. Transmission Line Length.......................... .... 73
4.3.2.6 Comparison of Coplanar Waveguides and Adjacent Microstrips.... 74
4.3.3 Discussion and Reduction of CrossTalk ,.... 76
4.4 Simultaneous Switching Noise (Ground Bounce)........ 78
4.4.1 Analysis of Simultaneous Switching Noise " ... .. . . 80
4.4.2 Forming Damped RLC Equivalent Circuit of Power Trace................ 83
4.4.3 Simulation of Ground Bounce.... .... .. ... ... . .... .. . 85
4.4.4 Summary of Ground Bounce Reduction ,............................... 91
4.5 Points of Design. 92
5. NOVEL LAYOUT DESIGN FOR LARGE TRANSISTOR. .. 96
5.1 Overview of problems. 97
5.2 The Effect of Rg onfr,/max, Thennal Noise and Transient Response 98
5.2.1 Cutoff Frequency fr. . .. ... ... . .. .. . .. ... .. .. .... .. . .. ... .. .. .. . .. ... . ... . 99
5.2.2 Maximum Frequency ofOscillationfmnx................................ 100
5.2.3 Thennal Noise ,..... 102
5.2.4 Device Delay. ... ... .... ... .. .. .. .. . .. . .. . .. . .. ... .. .. .. .. .. .. ... ... ... .. .. .. 103
5.3 The Effect ofRs on gm, gds and Bandwidth...................................... 104
5.4 Novel Structure for Large Transistor. . .... ....... ...... ...... .. .. ... ... ... ... .. . 106
5.4.1 Selection ofBasic Cell. 107
5.4.2 Novel Layout Based on Triangle and Diamond Cell..................... 108
5.5 Comparison of Triangle and Finger Structure................................... ... 113
5.6 Conclusion.............................................................................. 115
vi
6. CONCLUSION AND SUGGESTION 116
6.1 Conclusion............................................................................... 116
6.2 Test Structure........................................................................... 120
6.3 General Design Procedure and Suggestions......................... 122
BIBLIOGRAPHy..... .. .. . .. .. .. . .. .. .. . 128
vii
Table
LIST OF TABLES
Page
2.1 (a)(b) Example cal. Parameter data of a lossy transmission................. 21
3.1 Definition of lossless, lossy and fully lossy transmission line '" 25
3.2 Sensitivity of line delay to various parameters .... .. . . .. . .. .. .. .. . .. ... . .. . .... . . . . .. .... 34
3.3 Calculation and simulation data of signal delay for a transmission line............... 44
4.1 Series termination simulation data ,.. .. 53
4.2 The effect ofdriver width on signal risetime ,............................ 59
4.3 Risetime calculation and simulation data with different line lengths.............. 60
4.4 Calculation and simulation data for mathematical model accuracy........ 68
4.5 Simulation and calculation data of crosstalk vs. Spacing '" . . . . . .. . .. 70
4.6 Simulation data of crosstalk vs. termination resistance RI • . •• ••• • •• •••••• ••• • •• . •. • .•• • 72
4.7 Simulation data of crosstalk vs. driver size. . . . . . . .. . 73
4.8 Simulation and calculation data of crosstalk vs. different line lengths................ 74
viii
4.9 Crosstalk simulation data for waveguides with separating GND trace
and adjacent microstrip lines with separating GNU trace.............................. 75
4.10 Ground bounce simulation data. .. .. .. .... ... .. . .. . ... .. .. . .. . .... ... ... ...... .. .... . .. .... 88
5.1 The extracted data comparison between triangle and finger structure........... .... 114
ix
Figure
LIST OF FIGURES
Page
1.1 A simple diagram of interconnection.. .. . .. . . .. . . . . 4
2.1 Crosssections of typical transmission line structure................................... ... 8
2.2 Crosssections ofmicrostrips on insulating substrate (a) and oxidepassivated
silicon (b). . .. ... . . . .. . . ... .. . ... .. . .. . .... . . .. . .. ..... .. . ... .. . .. . .. .. ... . .. . . . .. .. . .. ... . .. .... 11
2.3 Microstrip self capacitance and inductance versus line width (w) and substrate
height (h).. 13
2.4 Self capacitance on oxidepassivated silicon, sapphire and GaAs....... .... ... .. ..... 14
2.5 Effect of parallel loads on characteristic impedance.................................... 19
2.6 Properties ofcharacteristic impedance. .. ... . .. . . . . ... .. . .. . . . . 20
3.1 The basic lumped RLC segment for a lossy transmission line.... .... .. . .. .. . ... .... ... 30
3.2 (a) "Tee" type symmetric lumps; (b) "Pi" type symmetric lumps;
(c) "Gamma" type lumps. . .. . ... .. . .. .. ... . .. . . . . . .. . .. ... . .. ... . . .. . . . .. .. . . .... . .. .. .. . . . . 31
3.3 Lumped and distributed model for interconnection...................................... 33
3.4 Typical series RLC circuits and typical response........................................ 36
x
3.5 Delay versus line width................ 38
3.6 Graphical illustration of bond wire delay................................................. 39
3.7 Interconnect equivalent circuit with bond wire and pads , 40
3.8 Equivalent RLC circuit ofinput and output ends......................................... 41
3.9 (a) Resistance attenuation constant versus line width; (b) Resistance
attenuation versus operating frequency......................................... 43
3.10 Delay simulation schematics and segments. ... ...... ....... ... .. .... .. ..... .. ... ... ... . 44
3.11 Delay simulation results (a), (b), (c) and (d)......................................... .... 45
3.12 Comparison of calculation and simulation data for signal delay. ... ... .... ... .. .... . 45
4.1 (a) Parallel termination; (b) Series termination......................... 49
4.2 (a) Secondincidence switching problem of series termination with multiple loads;
(b) Parallel fanout with multiple series termination.................................... 51
4.3 The function of termination resistance, Rt, vs. (a) load capacitance CL;
(b) line resistance, RUne; (c) Driver channel resistance, Ron........ 53
4.4 Simulation waveform of series termination
(a) Optimal termination with different transmission line length;
(b) Different termination resistance with fixed line length i.e. line resistance....... 55
4.5 Estimation model of signal risetime....................................................... 57
4.6 The simulation results of signal risetime (a) risetime versus transmission line
length and (b) risetime versus driver size................................................. 59
4.7 Risetime simulation schematics and segment " .. . .. 59
Xl
4.8 Risetime comparison between calculation and simulation (a) Zo=50n and
(b) Zo=75.Qwith different load capacitance, termination resistance and line width 61
4.9 Risetime comparison between cal. and sim. with different driver size............... 61
4.10 Crosssections of (a) coplanar waveguides; (b) microstrips. . .. . .. . .. 64
4.11 Circuit model for crosstalk due to capacitance coupling. . .. . .. . .. . . .. .. . .. ... . .. .. . .. 65
4.12 Capacitance crosstalk 0 f coplanar waveguides versus ground line width
and signal frequency. . .. . .. . .. . .. . .. . .. . . .... . .. . . .. .. . ... . ... . .. .. . . . . . .. . ... .. . .. . .. . . . ..... 66
4.13 Capacitance crosstalk simulation (a) Simulation schematics;
(b) One sample simulation waveform........ .. . .. .. . .. . .. .. . . .. . .. 67
4.14 Crosstalk comparison between simulation and calculation data. .... .. ... .. ..... ... .. 69
4.15 Capacitive crosstalk versus spacing oftwo signal lines. 70
4.16 Crosstalk versus termination resistance.... 72
4.17 Crosstalk versus driver size.............. .. .. .. .. .. 73
4.18 Crosstalk versus line width , 74
4.19 Effect ofGND trace on crosstalk. 75
4.20 Equivalent circuit and switching current model.. '" " , 80
4.21 Equivalent RLC circuit for power supply system , , 83
4.22 Ground bounce simulation circuit and typical response............................... 85
4.23 Ground bounce simulation results (a), (b), (c), (d) and (e)............................ 87
4.24 Ground bounce vs. Decoupling capacitance to load capacitance ratio............... 88
xii
5.1 Equivalent circuit models used in analysis ofRg effect on transistor performance.
(a) lumped model; (b) smallsignal model ofa MOSFET. . .. . .. ... . . . . .. . .. . .... . .. .... 98
5.2 Calculatedfr andfmax data versus test data.................... 102
5.3 Rs effect on gm. gds and bandwidth '" 105
5.4 (a) gm versus transistor width; (b) gds versus transistor width " '" .. , 106
5.5 (a) Polygon with n identical edges;
(b) Polygon perimeter versus number of edges , . . .. . .. 107
5.6 Triangle and diamond basic cell and layout structure. (a) triangle cell;
(b) layout structure based on triangle cell; (c) diamond cell;
(d) layout structure based on diamond cell............................................. 109
5.7 Comparison of triangle and diamond structure (a), (b), (c), (d) and (e).. ..... ...... 113
5.8 Side by side comparison of layouts with triangle and finger structure. . .. . .. .. . . .... 113
6.1 Test structure for transmission line and large transistor............................... ]21
xiii
NOMENCLATURE
Co Speed of Light in Vacuum
C Line Capacitance per Unit
Ccoupling Mutual Capacitance for Crosstalk
Cgs Gate to Source Capacitance of Transistor
Cdb Drain to Body Capacitance of Transistor
Cline Total Line Capacitance
Clump Capacitance of Lumped RLC segment
Csource Capacitance of Signal Source
Ctotal Total Capacitance ofInterconnection
CD Decoupling Capacitance
CL Load Capacitance
d Interconnect Line Length
db Bond Wire Length
dmax Maximum Interconnect Line Length
f Signal Operating Frequency
fc Cutoff Frequency of Skin Effect
fT Cutoff Frequency of Transistor
fmax Maximum frequency of transistor
gm Transconductance Parameter
~s Drain to Source Transconductance Parameter
h Height of Substrate
L Line Inductance per Unit
Channel Length for Transistor
Lb Bond Wire Inductance
xiv
L\ump Inductance of Lumped RLC segment
Lline Total Line Inductance
Ltotal Total Inductance of Interconnection
N Number of Lumped RLC segments
Q Quality Factor
r Radius of round Wire
R Line Resistance per Unit
Rg Gate Resistance of Transistor
Rs Source Resistance ofTransistor
Rcritical Resistance set to "critical damping" for Series RLC circuit
Rlump Resistance of Lumped RLC segment
Rline Total Line Resistance
Rsheet Sheet Resistance ofMetal Trace
Ron Tumon Resistance ofTransistor
Rout Output Impedance ofDriver
Rs Source Output Resistance
Rt Tennination Resistance
Rteff Effective Tennination Resistance
Rtotal Total Resistance oflnterconnection
S Spacing Between two Parallel Traces
t Thickness of Interconnection Line
tb Bond Wire Induced Delay
41 Delay of Interconnect including Buffer Chain
411 Delay of interconnect
4Jb First Stage Delay ofBuffer Chain
!ds Delay of One Lumped RLC Segment
tr Timeofflight
tox Thickness of Oxide Layer
tr Signal Risetime
VI2 Crosstalk Voltage
Vfirst First Incidence Voltage
xv
Vin Input Voltage
VA Fast Rising Portion of Unit Step Signal Response for a Transmission Line
Vdd Positive Power Supply
VGS Gate to Source Voltage
V1H Minimum Input High Voltage
V1L Maximum Input Low Voltage
VR Slow Rising Portion ofUnit Step Signal Response for a Transmission Line
VT Threshold Voltage
W Interconnection Width
WefT Effective Width ofInterconnection
wg GND trace width
W Channel Width ofTransistor
WefT Effective Channel width ofTransistor
Zo Characteristic Impedance of Transmission line
Zioad Effective Load Impedance
a Scaling Factor ofBuffer Chain
aD Dielectric Attenuation Constant
aR Resistance Attenuation Constant with Skin Effect
as Resistance Attenuation Constant without Skin Effect
~ Electrical "Length" of Lumped RLC segment
E Dielectric Constant of Material
EO Permittivity of Free Space
EefT Effective Dielectric Constant
Er Relative Dielectric Constant
}..l Magnetic Permeability of Free Space
Transistor Self Gain
}.1r Relative Magnetic Permeability of Material
p Resistivity of Material
Os Skin Depth
0) Signal Frequency
xvi
v Signal Propagation Speed
't Signal Delay of per Unit
ilC Mutual Capacitance per Unit
ilv Inductance Induced Voltage
xvii
CHAPTERl
INTRODUCTION
The development of integrated circuit has gone through the stages of smallscale
integration, medium scale integration and very large scale integration (VLSD. This
technology revolution increases complexity and density of semiconductor devices
allowing electronic systems to reach even higher performance. To keep pace with the
advances in IC technology, a higher performance packaging and interconnection have
been developed [5][7]. Large die SOI/SOS and multiple chip modules (MCMs) are
developed as advanced system applications with complex functions and high speed. In
large size single die and MCMs applications, the interconnection density and length
increases dramatically. For example, the die size has grown up to 20mm x 20mm [6] in a
recent report. In MCMs, the wiring capacity is greater than 400em/cm2
, and the size
reaches 127.5mm x 127.5mm (IBM ES900) [1] with the maximum length reaching to tens
of em. Simultaneously, as the fabrication technology has improved, the device geometry
has scaled down to Lef! =0.09jOn, with a highest unitycurrentgain frequency of
lOOGHz for NMOS, (IT) [55]. Due to the greater line length, finer metall/metal2 etc.,
small dielectric thickness and higher operating frequency (a few GHz), the interconnect
can no longer be modeled as a lumped circuit and becomes a critical factor in large highspeed
system design [2][3].
The electrical high performance constraints of an electronic system are the system
working frequency (i.e. system bandwidth, settling time or clock frequency), signal
2
integrity and noise level. For a given architecture, the system must be designed to run at
a maximum operating frequency correctly and reliably. To maximize operating
frequency, the delay in critical paths, i.e. the paths with maximum delay, should be
minimized. The system reliability is limited by the system noise level. Electrical noise
may induce inadvertent logic transition, i.e. errors in the system. To achieve high
performance, both maximum operating frequency and acceptable noise level are the most
important issues in the design exclusive of process yield.
In an electronic system, total delay is the sum of various delays in the system.
Delays caused by devices and interconnections are the two dominant factors. Device
delays are reduced by improvements in fabrication technology. Since the fabrication
technology has made significant advances in recent years, interconnect delays are
becoming the dominant problem replacing gate delay. Interconnect capacitance can
become larger than gate capacitance hence determining the overview speed performance
of the system. This large capacitance also increases power consumption and noise. For a
properly designed interconnect, delay is totally determined by the conductor material and
the line geometry.
Circuit density is the maxlITlum number of electronic elements that can be
contained in a chip or MCMs [1][2]. It is determined by the wiring capacity. Wiring
capacity is affected by several factors, one ofwhich is wiring density. Wiring density is a
function ofminimum line width, line separation and via size. The characteristic length of
a line with minimum line width, separation and via size is specified by electrical effects.
Too high a density can result in unexpected noise. If an interconnect is not properly
designed, signal reflects and shape degrades significantly. In addition, two parallel signal
3
lines must be separated by a specific minimum spacing to avoid excessive crosstalk
nOIse.
In highspeed digital design, in contrast to low frequency design, the parasitic
circuit elements of an interconnect, such as resistance, capacitance and inductance can
not be neglected. These design issues are focused on the behavior of passive circuit
elements, such as the wires, circuit boards and integratedcircuit packages. At low
frequency, the effects of passive elements are typically neglected as just parts of a
product's packaging. However, in high frequency application, they playa direct and
important rule in electrical performance [2].
Interconnection has a greater and greater effect on system electrical performance.
The proper interconnect (including packaging) design distributes to the achievement of
high speed, high reliability and lower power dissipation in high speed and highdensity
applications. The effects of parasitic parameters of an interconnect line on signal
propagation (ringing and reflection, etc.), interaction between signals (crosstalk) and
other interference (simultaneous noise, etc.) has become very critical issues in designing
valuable high speed system.
1.1 Objective
The objective of this thesis is to develop a novel layout for large transistor based on
triangle cell to mitigate the gate and source resistance limits on transistor performance. A
set of general design guidelines and theoretical parameter and performance estimation
equations are also developed for interconnects with long lengths or used in high speed
4
applications (a few GHz) on MCMs and large SOUSOS dies. This research is based on
the investigation of interconnect parasitic parameters extraction, review of transmission
line properties, signal delay analysis, crosstalk estimation, simultaneous nOIse
calculation, termination resistance selection, proper driver design and novel layout
realization. The simulation and layoutextracted results are also presented to support this
proposal.
Figure 1.1 shows a simple interconnection diagram. The main parts include
interconnection wires, loads, signal drivers and power supply. The design issues covered
in this thesis are outlined as follows.
Po.. .,. Supply
Interconnect
1 c, _
T
receiver
GroLrl4Trace
Fig. 1.1 A simple diagram of interconnection
1. Chapter 2. Extraction and calculation of electrical parasitic parameters of an
interconnection.
2. Chapter 3. Interconnection types, lossless, lossy and fully lossy transmission line;
and the application of each.
3. Chapter 3. Maximum line length and proper signal risetime applied.
4. Chapter 3. How to achieve the optimal delay; Line geometry design (width, selection
ofcharacteristic impedance).
5
5. Chapter 4. Proper tennination methods (parallel or series) and the optimal
termination resistance.
6. Chapter 4. Proper driver size and fanout topology design
7. Chapter 4. Crosstalk reduction and effect of distribution parameters.
8. Chapter 4. More issues on line geometry design (line spacing and tennination)
9. Chapter 4. Controlling ground bounce, estimating decoupling capacitance and effect
ofdistribution parameters.
10. Chapter 5. Limitations in the design of transistor with large effective width. A novel
transistor layout and its advantages.
1.2 Organization
Chapter I introduces the background and proposes for this study.
Chapter 2 reviews the extraction of parasitic parameters, i.e. self capacitance,
inductance, resistance and characteristic impedance of an interconnect. The effect of
substrate material, line width, substrate height and operating frequency is also discussed.
Chapter 3 discusses basic issues of a transmission line design, especially in
optimal delay design. Three different types of transmission lines and their characteristics
are discussed. A distributed Lumped RLC model is used for lossy transmission line
simulation. Optimal delay design issues, including delay estimation, peripheral part
effect, i.e. bond wire and pads, and parameter sensitivity to delay, are discussed and
simulation results are presented. The signal loss for very long interconnects is also
included in this chapter.
6
Chapter 4 analyzes the control of reflection, crosstalk and simultaneous noise.
The proper driver size design is also covered along with the proper selection of a
termination type and resistance value. In section 4.1, signal reflection and termination
method is studied and simulation results are presented as verification. In section 4.2,
proper driver size design is discussed. In section 4.3, a crosstalk estimation model is
reviewed and the effect of a GNU separation, termination resistance, driver size and line
length on crosstalk are discussed in detail. The simulation results confinn the selected
model. In the last section, a simultaneous noise model is presented along with analysis
and verification through simulations. In conclusion, simple guidelines for proper
termination, GNU trace width design for reduction of crosstalk and higher trace density,
decoupling capacitan.ce selection and proper driver size design are given.
Chapter 5 presents a novel layout for large transistor based on the analysis of gate
and source resistance limitations on transistor performance, specially cutoff frequency Jr,
maximum frequency of oscillation/max [4], thermal noise, gate delay, transconductance
gm and output conductance gds. The extracted results and comparison with a conventional
fmger structure are presented.
Chapter 6 summarizes the conclusion and recommendations. A test structure and
general design flow diagram are presented.
7
CHAPTER 2
EXTRACTION OF R, L, C AND Zo
With the increase of circuit operating frequency and the advent ofdeep submicron
technologies, the VLSI interconnects become one of the most important limiting factors
in highspeed and highdensity circuit performance. For systemlevel designs, such as
large onchip circuits or VLSI, multichip modules (MCMs) and printed circuit boards
(PCBs), the interconnects can induce considerable delays and coupling noise due to
transmission line effects. In general, the interconnect delay and coupled noise must be
considered in the evaluation of total system performance.
To model the interconnect effects, the electrical parameters must be first
extracted. The general description of the electrical parameters of an interconnect,
assuming it is a transmission line, requires five electrical parameters: line capacitance,
line inductance, line series resistance, line shunt conductance and line characteristic
impedance [8][9]. In VLSI and MCMs applications, the shunt conductance can generally
be neglected without losing generality. These parameters are determined by the
interconnect geometry and play a very important role in the analysis of interconnect
perfonnance, such as generated noise and delay. The following parts of this chapter give
out a general and relatively simple estimation ofinterconnect electrical parameters.
2.1 Transmission Line
8
Interconnects in VLSI and MCMs applications can be represented by several
different models. The RC and transmission line models are the two most frequently used
models. In the RC model, only resistance and capacitance effects are considered, but in
the transmission line model, the effect of line inductance is included. The RC model is
normally adequate for lower clock frequencies and short interconnects giving fairly
accurate results for those applications. However, if the interconnect is sufficiently long
or the clock frequency is sufficiently fast, a transmission line model must be used since
the RC model is no longer sufficient. In Chapter 3, the definition for a RC and
transmission line model will be discussed in detail. In MCMs applications, interconnects
are normally considered as transmission lines.
,,'
'"
lbl
,..
Figure 2.1 Crosssections of typical transmission line Structure
Figure 2.1 presents the crosssections of different transmission line structures
which are used to model the different interconnects in different electrical applications.
The wire above ground model (2.la) can be used to represent a bond interconnect.
Figure 2.1b is a coaxial model used for local area network or test probe connections. The
onchip interconnect is normally modeled as microstrip line (2.1 c) and both microstrip
and strip line (2.1 d) are used in MCMs and PCBs. In recent years, the microstrip has
been used extensively because it is easier to be fabricated and supplies a free and

9
accessible surface for solidstate device. A strip line is more expensive than microstrip.
In this thesis, all transmission lines are microstrips.
2.2 Selection of Material for the Substrate
The selection of the substrate on which the die will be mounted is one of the
considerations for MCMs application. In the following sections, it will be illustrated that
some electrical parameters of interconnect like line capacitance Cline and characteristic
impedance 20 are dependent on the dielectric constant of substrate. Different choices of a
substrate material result in different signal delays and losses. Reference [10] gives out
the advantages and limitations of two commonly used substrate materials, organic and
ceramic. In this part, The guideline ofMCMs substrate selection is illustrated.
2.2.1 Effective Dielectric Constant of Substrate
The relative dielectric constant is defined as Br =clBo (co =8.854.1012 F / m).
The effective dielectric constant depends on the selected material, line width and
substrate height. J. Howard gives out the following formula for effective Br as in (2.2.1)
[2],
(2.2.1)
(2.2.2)

to
where h is the height of substrate, weff is the effective width of signal microstrip, t is the
thickness of signal microstrip and 5r is dielectric constant of substrate material. Fig. 2.2
shows the typical crosssection of microstrip.
Dielectric constant has effect on signal delay and loss. More detail discussion
will be given in Chap. 3. Nonnally, the dielectric loss can always be neglected in MCMs
applications when maximum frequency is less than 10GHz [11][15]. But large magnetic
loss should be considered for Si in high frequency application.
2.2.2 Selection ofMaterial of Substrate[ 11]
• 5r should remain constant over the frequency and temperature range ofinterest.
• 5r often reduces slightly (5%) as frequency increases from dc to high frequency.
The value of 5r around 100M10GHz should be used for simulating highspeed signal
propagation, not the dc value.
• Dielectric resonance may exist at microwave frequency (» 1OGHz), but IS not
general concern for MCMs applications.
• Low dissipation factor or loss tangent (tan (5).
• For Polymer dielectrics, 5r increases with ambient humidity.
• High thennal conductivity.
• Low expansion in XY (substrate) plane.
• 5r should be as small as feasible. In this thesis, 5r =2.6 4.3 for MCMs; 5r=4.0 for
Si02; 5,=10.5 for sapphire.

11
2.3 Extract Self Capacitance and Inductance of Microstrip
Line capacitance and inductance are very important electrical parameters of
interconnects. They detennine the interconnection delay and coupling noise (mutual
capacitance and inductance).
2.3.1 Calculation of Self Capacitance and Inductance of Microstrip (pFlcm)
Figure 2.2 shows the crosssections of microstrips fabricated on insulating
substrate and oxidepassivated silicon substrate.
&idlS?Sl5?5?1 t
h
.J.
~
(e)
+i~ •
R h
~
(b)
Fig. 2.2 Crosssections of microstrips on insulating substrate (a) and oxidepassivated silicon
In the above figure, w is microstrip width, h is the substrate height
(lOOj.On250j.On for SOS and Bulk applications; JOj.On  301Jrn for MCMs application
[15]). tox is the oxide thickness (field oxide plus bulk oxide) for Sal (5000AO JOOOOAO).
Under such conditions, the formulas suitable for calculating capacitance and inductance
of an microstrip which can be derived from characteristic impedance of a microstrip
transmission line have been studied previous~y by Scheider [12] and Hassegawa et al.
[13]. These fonnulas are:

C = 1 ( 8h wefJ J n+
WefJ 4h
L = J.1.o In(~ + W
efJ J
21r WefJ 4h
(2.3.1)
(2.3.2)
(2.3.3)
12
Equation (2.3.1) is used for a microstrip on an insulating substrate (SOS and
MCMs) and (2.3.2) is used for a microstrip on an oxidepassivated silicon substrate
(SOl). The same equation (2.3.3) can be used to estimate the inductance for a microstrip
for SOS/SOl and MCMs with proper ground plane [14].
2.3.2 Properties of Self Capacitance and Inductance ofMicrostrip
The plots in fig. 2.3 shows capacitance and inductance change versus line width
and substrate height. The selected substrate materials are sapphire, gallium arsenide and
oxidepassivated silicon. The height (h) used for calculation is 25pm for MCMs and
250pm for SOS. tox (6000AO) is used for SOL Induced capacitance reduces quickly as
the height of substrate increases for SOS and MCMs applications. To keep capacitance
to a small value, larger substrate height and narrow line width are preferred. When line
width is much smaller than the height of substrate, i.e. h/w»3, the capacitance reduces
slowly. This implies that the capacitance can't be reduced more when the thickness of

13
substrate increases beyond h/w» 3. For SOl, thicker isolating layer and narrower line
induces smaller capacitance.
1l"ID''''
I 6"10"" ~j
L(w) J
1 "10'7 1
2"10'""7
w
line widll1 (um)
(a)
LVlII.w
(c)
t ~I.,,,I.J
~lIl)lIlo
J
t
C b
'.
J'"
(b)
L vs. h
o 0 5'105 0.0001 0.00015 0.0002
1\
1Ub._. height (um)
(d)
Fig 2.3 Microstrip self capacitance and inductance versus line width (w) and substrate height (h)
The inductance for SOS and MCMs reduces as the width of the transmission line
increases. To keep the inductance small, wider lines are preferred. However this will
increase the capacitance and results in decreased wiring capacity. The inductance for
SOl wiring increases as line width increases and substrate height decreases
(L ex In(w/4h) ». A narrow line has both a smaller capacitance and inductance for a SOl
system. In highspeed application, the reduction of inductance is a very important issue.

14
The proper selection of line width is detemrined by which parameter, capacitance or
inductance, is dominant in system perfonnance.
Besides the selfcapacitance and inductance, there is also mutual capacitance and
inductance between two or more adjacent parallel transmission lines. We will discuss the
model and resulting design method in the "crosstalk" section in Chapter 4.
2.3.3 Compare the Selfcapacitance on Insulating Substrate and on Oxidepassivated
Silicon Substrate
/
/
1"10
Fig. 2.4 Self capacitance on oxidepassivated silicon, sapphire and GaAs
Figure 2.4 shows that the line capacitance increases as the line width increases on
all three substrates. The interconnection made on an insulating substrate (Sapphire,
GaAs) induces considerably small capacitance (O.5pF5pF). The capacitance on silicon
substrate is larger than that on insulating substrate. However, this advantage diminishes
at small line widths. The capacitances are scaled differently, being a logarithmic function
on the insulator but a linear function of line width on the silicon substrate. The reason for
larger capacitance on silicon is the thin oxide layer, lox, fonning a large capacitor. For the
purpose of capacitance estimation of onchip interconnects, the thickness of field oxide
(bulk) or thickness of field oxide plus buried oxide (Simox) should be used.

15
2.4 Extract Self Resistance of Microstrip (Q/cm)
2.4.1 Calculation of Sheet Resistance
The resistance of conductors in MCMs and large die SOVSOS has a significant
effect on signal integrity, delay and termination. At low frequency, the line resistance is
its dc resistance and is given by equation (2.4.1), where p is conductor material
resistance, t is line thickness, Rsheet is the sheet resistance of metal trace, Rsheet = pit, d
and weffare line length and width respectively.
d d
R Ulle =Pt =Rsheet
w ejJ wef!
(2.4.1 )
D.B. Tuckerman [15] points out the following issues should be noted in MCMs
applications:
• Thin film resistivities are greater than bulk resistivities and depends on the grain size
and impurities.
• Alloy resistivities are greater than pure metal resistivities.
• High temperature resistivities are greater than that at room temperature. For Ai and
Cu, it is normally O.3rt:r"'O.4%tc. This resistance increase can be significant at high
temperature applications.
• Conductors often have a nonrectangular crosssection. To estimate resistance more
accurately, more complex models should be used.

16
• Line width and line thickness may vary from design value by up to 10% because of
process factors.
2.4.2 Skin Effect
At low frequencies, the current is distributed uniformly throughout the cross
section of conductor through which it flows; however, at high frequency, the current
distribution can be imagined as concentric tubes. The inner rings have more inductance
than the fatter outer rings. The current follows the path with least inductance at high
frequency, i.e. the current is concentrated on the surface of conductor. This is known as
skin effect.
2.4.2.1 Calculation of Resistance With Skin Effect
A constant called skin depth Os is used to measure the skin effect. It is the
distance at which current density becomes a fraction 1/e of its value at the surface. The
skin depth Os is expressed as (2.4.2). It is inversely proportional to the square root of
frequency. Here,fis the operating frequency and f..i =41rX 107 Henrys/meter. For Al
and Cu, p =2 ~ 3f.10.· em [15]
(2.4.2)
17
So the effective resistance of transmission line with skin effect is
(2.4.3)
For example, for a 3.3J.Dn plated Cu trace, p =2.8pO.·cm. when f=lGHz,
8. =2.6J.Dn; whenl=10GHz, 8. =O.8,um and 25% larger for Al on die. As the signal
frequency increases, skin depth becomes thinner resulting in increased line resistance.
Equations (2.4.1) and (2.4.3) shows that at low frequencies, a conductor has a
constant dc resistance; while at high frequency, resistance grows proportional to the
square root of frequency.
2.4.2.2 Cutoff Frequency
There is a cutoff frequency [2J [15J for any interconnect with a specific thickness,
at which the conductor thickness is equal to the skin depth. It is defined as (2.4.4). For
every interconnect, the cutoff frequency, fe. offers a criterion to determine if the skin
 p (2.4.4) Ie  1rf.l12
effect can be ignored.
When f < Ie' skin effect can be ignored. The proper thickness of conductor is
roughly equal the skin depth t ~ 8, or t ~ Jp/(fffl!) (equation 2.4.2) to achieve the
maximum line length at the lowest resistance (see Section 3.2.1). Too thick a trace
doesn't help to reduce resistance and increases material cost and signal distortion. The
18
effect of skin effect on signal attenuation and selection of transmission line types is
discussed in Chapter 3.
2.5 Computation of Characteristic Impedance Zo
2.5.1 Characteristic Impedance Zo of Transmission Line
Characteristic impedance 20 is another basic parameter of transmission line. It is
defined as
2= R + JOJL =(L )"2 JI+ R
o G+ jUJC C I JOJL
where R is the resistance per unit along the line
L is the per unit inductance along the line
G is the per unit conductance shunting the line
C is the per unit capacitance shunting the line
When RIJOJL «1, i.e. OJ» RIL
(2.5.1)
(2.5.2)
The characteristic impedance at lower frequencies is not real or constant. It has a
substantial capacitive component. A "50,Q line" or "75,Q line" is only a meaningful
concept at sufficient high frequency.
The different transmission line structures, such as microstrip, stripline, ooaxial
line, etc., have different approximate equations for 20 [2]. The microstrip 20 is
approximately given by
.......
19
(2.5.3)
Parallel capacitive loads and peripheral parts, such as bond wire and input/output
pads, change the value of characteristic impedance. In the case shown in figure 2.5, the
effective Zo is given by equation (2.5.4). Note, the nontransmission line parameters (Lb,
Cpad, Csource) should be comparable to the transmission line per unit Land C in this case.
Zeff =
C.ource + Cline + NCL + 2Cpod
(2.5.4)
N identical loads
fig. 2.5 Effect of parallel loads on characteristic impedance
2.5.2 A comparison of the microstrip characteristic impedance on different substrates
Figure 2.6 gIves out some information of characteristic impedance (Zo).
Microstrips with same geometry on different substrate have different Zo (plot (a». Plot
(b) compares two Zo estimation models (equation (5.2.2) and (5.2.3» and Plot (c)
compares Zo and line resistance and gives important information for Zo selection.
• Plot (a) presents the change of Zo on different substrates with the change of line
width. ZOsl, ZOsa and ZOga are characteristic impedances of microstrips on Si, Sapphire
and GaAs respectively. The plot implies Zo reduces and the change becomes slower
as the line width increases. A line built on sapphire has lower characteristic

20
impedance than that on a silicon substrate. To get a smaller 20• larger dielectric
constant should be chosen.
• A comparison of 20 estimation using equations (2.5.2) and (2.5.3) is shown in plot
(b). The equation (2.5.2) is simple and accurate enough and is also useful in line
inductance estimation using TDR (See Chapter 3).
J ~(..)100 '. .I " .S! zo.( .... ) ...... '
~" <':'" l ~..)50 "  :"'':''' '.'~.''': :. •..:
(a)
~(I 10
, %"'0 ""'0 '"10 ,°'10"10
(b)
"
,.
200 ,.1,1,
w
line widlh
(c)
Fig. 2.6 Properties of Characteristic impedance
• From plot (c), when 20 has a large value, the line resistance is very large. That
implies higher resistive attenuation. The high 2 0 (>1OOil) should be avoided in
MCMs application due to high line resistance. But larger 20 helps to achieve smaller
driver size (smaller power dissipation but lower speed) (see section 3.2.1). So there is

21
a tradeoff in the selection of the proper 20 between signal loss and line length/driver
design.
• Line resistance becomes smaller than 20 as the width increases (plot (c)). An
additional series resistance should then be added to achieve the optimal delay and
tennination, Rtolal ~ (l ~ 3)20 (See section 3.2.6)
2.6 Points of Design
Table 2.1a Example cal. parameter data of a lossy trans. line. (t = 5f.Dn , (with skin effect))
W(f.Il1l) C(Pf/cm) L(nH/cm) R(f)/cm) Zo(.Q) dm1n(cm) dma:lcm)
28,83 2.233 3.568 3.29 40 1.216 11.4
16.85 1.749 4.36 5.08 50 0.98 10.1
3.915 1.128 6.336 13.91 75 0.54 6.1
0.707 0.828 8.273 36.77 100 0.272 3.3
Table 2.tb t = If.Dn (without skin effect)
W(f.Il1l) C(Pflcm) L(nH/cm) R(f)/cm) zorn) dml.(cm) dmn.lcm)
32.5 2.247 3.59 9.91 40 0.4 3.8
20.2 1.76 4.394 15.35 50 0.326 3.3
6.11 1.138 6.387 42.5 75 0.176 2.0
1.52 0.834 8.34 113.2 100 0.088 1.1
Table 2.1 gives out example calculation data of C, L. Rand 20 with h =25f.Dn
(MCMs), f =IGHz (55 = 2.6f.Dn). Concluding the analysis above, the following design
highlights are most important consideration for R, L, C and 20 extraction. The line
geometry, signal frequency and material of conductor and substrate determine
interconnect parameters.
• Use verified physical data for the technology in the intended design
• Dielectric constant Gr
22
• Conductor sheet resistance
• Layer thickness (h) and conductor line width (w)
• Intended characteristic impedance (Zo)
• Interested operating frequency
• Thickness of metal trace t has no influence on L, C.
• Line capacitance increases but inductance decreases as the line width increases or
substrate height decreases for MCMs and SOS.
• The design of line width and substrate height is determined by either the self
capacitance or inductance, which is dominant in system performance. Factors
considered include signal delay, integrity and coupling noise
• If the maximum line length is desired, the thickness ofmetal trace should be set to the
skin depth t =Os (f) . Too thick a metal trace is not helpful in improving the
performance of a transmission line. If t > Os (f), extraneous material is wasted; if
t < Os (f) , higher resistance will be resulted. Under the satisfaction of signal delay
(risetime) and loss requirements, the thickness ofline is preferred to be thinner with a
maximum value os(f).
• If thickness t is less than skin depth, the resistance of trace will increase. This
characteristic helps to design short lossy transmission lines, for example, an onchip
transmission line.
• Too high a characteristic impedance should be avoided because of larger line
resistance. The most popular used values of Zo are 5012 (75.Q) or less (3012 100il).
The parallel loads may reduce the effective value of Zoo

23
CHAPTER 3
DESIGN OF TRANSMISSION LINES
As the signal frequency and circuit density increase, the performance of
interconnect becomes increasing significant. In an electronic system, interconnects
include: onchip wires, wires on the MCM substrates, wires on PCBs, the package pins,
lead frames, bonding wires and solder bumps, etc. Their electrical performance varies
widely and depends on the lengths and crosssections of interconnects and operating
frequencies. The most popular used models are the RC and transmission line models.
As mentioned in part 2.1, the transmission line model is used for high frequencies
and long interconnects. In this model, interconnect inductan.ce has been considered. N.
Sherwani and Q. Yu [1] offer a simple merit to determine whether the RC or transmission
line model should be used for given geometry. In brief, when the signal risetime, tr, is
much less than signal timeofflight, tf' i.e., t r < 2.5tf' a transmission line model should
be used. On the other hand, when tr is much larger than tf' i.e., t r > 5tf' lumped RC
model is sufficient. When tr is between 2.5tf and 5tf' either model will suffice. tf is the
timeofflight of the signal and is given by:
(3.1 )
where Co is speed of light in vacuum (3.108m/ s); Sr and fir are the relative permittivity
and permeability of propagation medium. fir is approximately 1 for nonmagnetic
material.
24
For MCMs applications, intercoIUlects are typically modeled as transmission lines
due to short risetime and long lengths. In figure 2.1, four typical transmission line crosssections
were presented. Compared to ordinary pointtopoint wiring, a transmission line
has less signal distortion, less radiation and less crosstalk due to the reduction of line
inductance and the short distance to the ground plane [2].
3.1 Lossless, Lossy and Fully Lossy Transmission Line
An ideal transmission line consists of two perfect conductors. There are:
balanced (twisted pair) and unbalanced (coax, microstrip and stripline) transmission lines.
An unbalanced transmission line is also called a singleended line. In this type of
transmission line, signal current flows through one signal trace and returns back along the
ground trace. The ground trace is usually wider than signal trace and can be shared
among many signal traces [2].
Every transmission line goes through lossless (LC) ~ lossy (RLC) ~ fully lossy
(distributed RC) transition as operating frequency or length increases. The key factor is
the total line resistance (Rune). The ratio of 20 =JL/C (.Q) to line resistance per unit R
(f2/cm) determines the critical useful length.
3.1.1 Definition of Lossless, Lossy and Fully Lossy Transmission Line
Recall the formula (2.5.1), if the conductance G is ignored, the transmission line
characteristic impedance is a function of frequency.
2  ~+j{j)L _(L)~ ( R J 0   + 1+
jwC C j{j)L
(3.1.1)
25
The following Table gives out a definition ofthe three type transmission lines
Table 3.1 DefInition oflossless, lossy and fully lossy transmission line
types Defmition(I) Definition(TI)
Lossless R «1 R R,olaf «Zo or m» 
mL L
Lossy R R R,olaf ~ Zo ~1 or m~
wL L
Fully lossy R R R,otaf »Zo »1 or w« 
{j)L L
The critical length of each transmission line type is given by:
(3.1.2)
where L, C and R are the inductance, capacitance and resistance per unit of a
transmission line. For lossless line, K ~ 0.1; for lossy line, 0.1 ~ K ~ 2 ~ and for fully
lossy line, K ~ 2. The critical length increases from lossless to lossy and fully lossy.
The skin effect in high frequency applications will reduce the critical length [1 S].
For example, if R =10fllcm (recall table 2.1) and 20=50.0, when d ~ O.Scm;
O.Scm ~ d ~ 10em and d ~ 10cm, we have lossless, lossy and fully lossy transmission
lines respectively.
3.1.2 Characteristics of Three Types of Transmission Line
Normally, the interconnects, such as wires on the PCB, package pins, lead frames,
bonding wires and solder bumps, all have low resistance due to their large crosssections.

26
As a result, these interconnects can frequently be treated as lossless transmission lines or
inductors.
For MCMs wmng, because of their small dimension and long length, the
resistance is usually significant and they are treated as lossy transmission line. This case
will be more common for large die onchip interconnects in the future.
A brief description of the properties of lossless, lossy and fully lossy transmission
line is presented as follows [15]:
a. lossless transmission line
• R is neglected and 20 IS a real constant In the frequency of interest.
• No energy loss occurs in the line.
• Propagation delay is linear with length and the signal propagation speed is
given by formula (3.1).
• The signal is undistorted along the line but should be terminated.
b. lossy transmission line
• R, L and C can not be ignored and 20 is complex and frequency dependent.
In most cases, 2 0 Rl JL/C .
• Significant energy loss exists In bne and senes termination or nontermination
is useful because of significant line resistance (DC losses) (more
discussion in section 4.1)
• Signal delay ranges from linear to quadratic
• Signal is somewhat distorted
c. fully loss transmission line
27
• L is neglected. Zo is complex, frequency dependent and is not an useful
concept at any frequency.
• High line energy dissipation and no signal reflections.
• Signal propagation is proportional to RC, and quadratic with length.
, ~ RC ~ length 2
.
If there are multiple loads along the line, attempts should be made to use a
lossless transmission line since the signal has no distortion and only delay at different
points along the line. Use of a lossy transmission line can be difficult for multiple loads
due to the signal distortion. If there is only one load on the end, both lossless and lossy
transmission line can be applied. When a lossy transmission line must be applied to
The selection of transmission line type for an application depends on loading,
operating frequency and line length. For long interconnects on large single die or MCMs,
connect multiple loads, parallel fanout is preferred.
( (3.1.3)
L)I/2 (L)I/2
0.1 C ~ RUne ~ 2 C
they are usually lossy transmission lines. The resistance Rune is limited by
3.2 Optimal Delay Design of a Transmission Line
All electrical devices from basic gates to large chips have their speci.fic delay.
The cumulative effects of inductance and capacitance result this delay. The gate delay
reduces faster due to the scaled down device geometry and the interconnect delay
becomes one of the most important limiting factors in today's highspeed and highdensity
circuit perfonnances. As a result, it is vital to minimize interconnect delay to
28
achieve the highest performance. The interconnect delay is determined by many factors,
such as line length, conductor geometry and material, etc. In this section, the design of
optimal delay will be discussed.
3.2.1 First Incidence Voltage
Assuming a unit step signal is applied in the input end of a transmission line, the
response of this line at a distance x from the input end is consisted of two parts: the fast
rising portion, VA, and the slow rising portion, VR• VA =eax. is an attenuated function
exponentially dependent on attenuation constant a and the distance x; VR represents a RClike
behavior [1 ][16].
To achieve minimum propagation delay on a transmission line, the fast rising
portion, VA, must have sufficient amplitude. In another words, the first signal (first
incidence voltage) to arrive at the end of the line must have sufficient voltage to switch
the receiver, e.g. its value should exceed VlH on I ~ 0 transition or VIL on a 0 ~ 1
transition. VlH is minimum voltage that is required to be input of receiving device for a
logic 1; VIL is the maximum voltage that is applied to the input of a receiving device for
logic O. This situation is referred to as first incidence switching [16].
The first incidence voltage at the receiving end is given by

Vflr!1 = Zo . e(R~zo)
Vin ROUI + Zo
(3.2.1)
(3.2.2)
29
3.2.2 Lumped RLC Model for A Lossy Transmission Line
where V/n is the open circuit output of driver, R is the per unit resistance of transmission
line, d is transmission line length and dmax is the maximum length for fixed driver size,
characteristic impedance Zoo When Zo » ROU1 and Vin equals Vdd /2 :
To get enough firstincidenceswitch value Vjirst' the resistance R should be small
and Zo should be significantly greater than driver output impedance Roul ' Because Zo of
a transmission line will always be chosen between (30n100n), the output impedance of
a CMOS driver is designed around (5n200). If Zo is selected too small, a large width
driver is required to achieve small output impedance. Too a large driver width results in
higher power dissipation and device performance limitations due to the increased gate
(Rg) and source resistance (Rs) (see Chapter 5). If Zo is too large, line resistance will be
large (see section 2.5.2). This may in turn create problems in meeting the signal risetime
and loss requirements resulting longer line unavailable The selection of 20 should be a
tradeoff between signal speed/loss and driver size/power consumption.
(3.2.3) d~x ~ 1.38Z01R
As mentioned in the beginning of this chapter, the RC and transmission line
models are the two most popular models being used to describe the properties of
interconnects. A lossy transmission line can be modeled and simulated as a series
lumped RLC segments using lossless transmission line sections separated by lumped
resistance and conductance. Figure 3.1 presents the structure of this basic segment [17].
30
The characteristic impedance (20 =JL/C) and lossless transmission line delay
('[ =d$ • .JLC ) for each segment are the same and the segment delay is the total delay
divided by the number of segments. ds is the line length of each segment.
O./\NVI_l L09sless Tran. Une
Fig.3.1 The basic lumped RLC segment for a lossy transmission line
(3.2.5)
(3.2.4)
The only consideration in basic segment design is the number of segments should
is much smaller than signal risetime. In another words, the RLC lumped segment's
Assuming {J= Jll 0, the number oflumped sections. N. is given by:
can be thought as the electrical "length" of each lumped segment (fJ =X'  ){o)
propagation delay d$ (LCyl
2 should be a small fraction fJ of the risetime. The quantity f3
offer a fine enough granularity such that for each lumped segment. the propagation delay
where d is total transmission line length; L and C are line inductance and capacitance per
unit respectively. The lumped capacitance. inductance and resistance are given by:
(3.2.6)
(b)
(3.2.8)
(3.2.7)
G....
(a)
c...,
C·d
Clump =N
31
For example, assuming a lossy transmission line with Zo=50n, d=3cm,
This series lumped segment model of a lossy transmission line can be used in
with number of segments, N, equal 8 then Clump=O.66pF, L1llmp=J. 648nH, and
C=1.76pF/cm, L=4.394nH/cm, R=15.35J21cm (Table 2.1) and signal risetime tr=350ps.
inverter) to avoid introducing unphysically high frequencies, which may excite resonance
PSPICE for transmission line simulation. The input should be "filtered" (i.e. using an
ofthe individual lumped segment.
Rlump=5.76Q.
L".,
(c)
Fig. 3.2 (a) "Tee" type symmetric lumps; (b) "Pi" type symmetric lumps; (c) "Gamma" type
lumps;
32
Figure 3.2 gives out other three types, but equivalent segments used for simulation
where G is always neglected. In this thesis, a "Gamma" type lumped segment is used and
recommended to reduce network size.
3.2.3 The Delay Estimation for A Transmission Line
The extraction fOlTIlUlas for capacitance, inductance and resistance of a lossy
transmission line were illustrated in Chapter 2. It is known the line capacitance,
inductance and resistance are functions of the line width w. Roughly the following
equations are held:
R(w) ex: };(w)
C(w) ex: 12 (w)
L(w) ex: 13 (w)
(3.2.9)
(3.2.10)
(3.2.11)
Figure 3.3 presents an interconnect driven by cascaded buffer chain (a) lumped
model; (b) distributed model (series RLC model).
It is well known that the cascaded buffer chain with increasing width ratio,a,
offers the minimum delay and it is easy to show a =e(2.718) for ideal case. Practically
a always varies from 2.5~5 depending on the process.
For a lumped model, the delay of an interconnect with a capacitance load at the
end is related to line width. Using the Elmore delay equation, it is given by:
(3.2.12)
\
33
Where Rout is the output impedance of the last stage of buffer chain. Combining driver
delay with (3.2.12), the total delay is
(3.2.13)
where tdb is the first stage delay in the buffer chain; Rs is sum of driver output
impedance, Rout. and tennination resistance R{ (R =R + R ) , sour r'
.
R.,. I R.
1i C",.12 c:rlc
J'ul_1 Lump.dmodel I TL
(a)
(b)
Fig. 3.3 Lumped and distributed model for interconnection
For lossless and lossy transmission lines, the signal propagation delay roughly
equals to timeofflight and is determined by the line inductance and capacitance. Except
for the signal amplitude loss, a lossy transmission line has the same properties as a
lossless transmission line. The delay of only the transmission line and the total delay
including driving buffer and pad inductance are given by (3.2.14) and (3.2.15), where
34
L line and Cline is total inductance and capacitance of the transmission line respectively.
The present of series inductance (bond wire) increases delay slightly by approximatly
Lb/ZO (see section 3.3).
(3.2.14)
(3.2.15)
3.2.4 Delay Factor Sensitivity Analysis
The transmission line delay is a function of driver output impedance Rout, series
termination resistance R" line resistance Rline , capacitance Cline and inductance Lline,
supply voltage Vdd, load capacitance CL, and driver end capacitance, CD. It can be
presented as:
(3.2.16)
Ayman & Karem [18] gave out the analysis for the sensitivity of delay versus
these parameters. They pointed out the delay of lossless lines is a linear function of
CL / Cline; and for a lossy transmission line, the driver output impedance and line
resistance can not be neglected. Ayman & Karem's analysis data are presented in table
3.2. The sensitivity of delay to parameters is briefly summarized as follows.
Table 3.2 Sensitivity ofline delay to various parameters
Parameters Sensitivity
Line length d 0.936
Line resistance per unit R 0.0493
Line capacitance per unit C 0.474
Load capacitance CL 0.120
Driver output impedance Roul 0.0254
35
•
•
•
•
The sensitivity to line length is close to one, which means that line length increases
by 5%, the delay increases almost 5%. Reference [15] confinns the same result.
The sensitivity to line capacitance is about 0.5, which can be derived directly from the
lossy transmission line delay equation t d =: dJLC .
The sensitivity to line resistance Rune is about 5%. Compared to the sensitivity of the
line capacitance, the sensitivity to line resistance is much smaller.
The sensitivity of driver output impedance is negative because delay decreases with
stronger driver.
The sensitivity to dielectric constant 6, is dependent on different types oftransmission
lines. For a diffusion transmission line, t d  Rto,a/Cto,al' the sensitivity to 6, is 100%;
For lossless transmission line, t d  (L(Cline +Cload ))1/2
, if Cline =: Cload ' the sensitivity
is 25%; For lossy and lossless transmission lines, the sensitivity is almost equal.
The sensitivity implies the priority of factors in optimizing delay. First, the
possible shortest line length is preferred by optimal placement and wiring. Second, it is
•
more advantageous to decrease line capacitance before trying to decrease resistance in
order to decrease the delay. A narrower line is preferred if the risetime and signal loss
specifications are satisfied.
3.2.5 Oscillation of Series RLC Circuits
When designing a transmission line, the resonation of the interconnect line must
be considered. A series RLC circuit will resonate when loop resistance equals zero. The
concern is excessive overshoot and undershoots due to under damping. Overshoot is not
36
a critical detriment to digital applications (this is not the case for ground bounce.), but
undershoot can cause logic faults and increase the effective delay. The equivalent RLC
circuit and its response are shown in figure 3.4. The extra delay induced by the
resonation is illustrated in figure (b).
~I
(a) (b)
Fig 3.4 Typical series RLC circuits and typical response
The resonation frequency of a RLC circuit and Qfactor are given by:
(3.2.17)
(3.2.18)
if R =2.JL/C , the real part of the frequency equals 0 and Q=0.5. This is
critical damping for a series RLC circuit. For a lossless transmission line.
RcriticaI ~ J LIC ~ Zo; for lossy transmission line, Rcritical ~ (1 ~ 7r)JLIC ~ (1 ~ 7r)Zo [15].
The series resonation of a RLC equivalent circuit is only a problem with a low
resistance line (lossless or lowlossy transmission line) and very wide CMOS driver (very
low output impedance). In this case, the Q factor can be very high. The following
solutions can be used to increase circuit damping toward the "critical damping"
condition.
37
a. Reducing line width or decreasing conductor thickness (if this is possible without
hurting signal risetime) to increase line resistance.
b. Using a larger tennination resistance.
c. Reducing driver width to increase its output impedance, however it should be noted,
this will increase the buffer delay causing an increase in the total delay.
d. If there is no room to increase the resistance, the inductance in system including the
bond wire inductance and/or line inductance should be reduced by using a thinner
substrate, wider conductor, parallel fanout topology, etc.
3.2.6 Optimizing the Delay
Optimizing the delay of a transmission line is to optimize the dimension of the
line and the size of driver, especially the transmission line width. If the series resistance
is too small, the circuit will ring; if it is too large, the delay will increase (for the RC
model). In Chapter 4, it will be shown out that the series resistance also plays important
role in proper termination of a transmission line. For this reason we will have a tradeoff
between the resonance and delay. Usually the optimal delay can be achieved when
RIo/a! =(1 3)20 [15], that implies
(3.2.19)
where Rlo/al = Rau, + RUne + R, ;
L L +L . Lb is the inductance ofbond wire', /o/al = b line ,
C =CI · + CI d +Cp ; Cp is capacitance ofpad; /0/01 me oa
Now considering the two extreme cases:
38
a. For a very wide line. RI , ~ 0; LI , ~ O· C. ~ 00 and f'  R C,  w·
/Ile me' line out Ime ,
b. For a very narrow line. Rline
~ 00; Lline
~ constant (very high); C ~ constant (very
For wide line, delay increases as the Cline increases, e.g. w increases; For narrow
line, delay increases as RUne increases e.g. w decreases. This implies there should be
optimal line width to achieve the minimum delay without signal resonance. Figure 3.4
shows the curve ofdelay versus line width [15].
V'ry' DIITOW lint
t...R.••C,11w
..orywidolillo
teR_C,••~\I'
Wopt
Fig. 3.5 Delay VS, line width
Lin. Widlh
Equation 3.2.19 gives out the range of total resistance for a transmission line,
which leads to optimal delay without signal resonation. R,o,a/ makes the circuit more or
less critically dumped. Going to a lower resistance than required doesn't improve the
system performance and in fact can introduce resonance and extra delay. From figure
3.5, it is shown that there is a very flat region around optimum line width. The choice of
line width also has an effect on driver size design and termination resistance selection due
to line resistance [19]. In practice, in the initial design stage, one or two line widths
should be selected and then adjusted by other design considerations (signal termination,
crosstalk, etc.).
39
3.3 Peripheral Parts' Effect on Interconnection Performance
Peripheral parts, such as bond wires and pads, also have a significant effect on
interconnect perfonnance. Bond wire induces extra inductance and pad capacitance
maybe larger than interconnect line capacitance. When evaluating the overview
performance of the system, those effects must be considered.
A bond wire is always modeled as an inductance. It is estimated by [15]:
(3.3.1)
where r is the radius and db is the length of round wire. This inductance induces extra
delay (tbd =Lb/ZO ) for signal propagation. For example, db = 1.25mm , r = 501Jf1'! ,
Zo = 50n, Ld = O.79nH and t bd = 15.8ps. Figure 3.6 presents a graphical analysis of
this induced delay (assuming LIZo« risetime).
+ IN 
+
(a)
Figure 3.6 Graphical illustration ofbond wire delay
From fig 3.6 (b),
(b)
I:1t L =_b
20
(3.3.2)
40
Equation (3.3.2) is used for lumped model analysis. The bond wire inductance also has a
significant effect on the power distribution. This inductance would induce a greater
possibility of high "simultaneous noise" and power distribution line oscillation. These
issues will be further discussed in Chapter 4.
,,
:~~
:i8I ,r~ c~Jnjc' :1~
Fig. 3.7 Interconnect equivalent circuit with bond wire and pads
At both ends of transmission line, there are output and input pads. These pads
add extra capacitance to interconnect. They have effects on signal propagation delay as
well as characteristic impedance. Figure 3.7 presents the equivalent circuit. The
effective characteristic impedance is given by equation (2.5.4) (see section 2.5.1) and
effective delay is:
(3.3.3)
(3.3.4)
41
Fig, 3.8 Equivalent RLC circuit of input and output ends
When selecting bond WIre, the resonation of series RLC should also be
considered. The equivalent circuits at ends of output and receiver are shown as in figure
3.8. For fixed Rout. Cline, Rune and eL, correct package technology (Lb) is required to
achieve a low quality factor, Q, avoiding resonance (equation 3.3.4). In order to improve
the system performance, the pad capacitance and bond wire should be made as smaLL as
possible. In simple terms, pad out must match the die process technology.
3.4 Loss in a Transmission Line
In this section, signal integrity along a transmission line is discussed. The signal
attenuation constant of a microstrip model depends on line dimension, electronic
properties of substrate and conductors and the operating frequency. Normally there are
two types of loss in transmission line model, one is dielectric loss due to substrate and the
other is ohmic skin loss in strip conductors and ground plane £1] [11]. The signal loss of
a transmission line with length d can be expressed as
V(x=d,t=td ) ad '= = e
V(x=O,t=O)
where a is attenuation constant and given by:
(3.4.1)
42
(3.4.2)
where aR is resistance attenuation constant of line without skin effect·,
as is resistance attenuation constant of line with skin effect,
aD is dielectric attenuation constant.
The signal conductor loss is caused by line resistance. Thickness of the line, t, is
used in the resistance calculation at low frequency and skin depth 8s for high frequency.
aR and as are given by:
a =~ P R 
2Zo 2wtZo
The dielectric attenuation constant is defined as:
:ifJe"fJ aD = tanB
Co
(3.4.3)
(3.4.4)
(3.4.5)
where Co is light speed in vacuum and tanB is dielectric loss tangent and is restricted to
lower than 0.001. According to reference [1], tanB =a/(m· 8,). Here, a is the
conductivity of the dielectric substrate and m is the angular frequency. SimplifYing
equation (3.4.5),
(3.4.6)
From equation (3.4.6), it is observed that if the substrate conductivity is frequency
independent, the dielectric attenuation factor is also frequency independent. And if the
43
dielectric constant and conductivity are chosen correctly, the dielectric loss are negligible
at most application frequencies.
0.4 rrr,r,r,
0.3
0.1
<ao(f)
":0   0.'
Qp(f)
.... '. ..
(a)
1'10 1'10 1'10 1'10 1'10 1'10
(b)
Fig. 3.9 (a) Resistance Attenuation Constant Versus Line Width; (b) Resistance Attenuation
Constant Versus Operating Frequency
Figure 3.9 presents the change of resistance attenuation constant versus line width
w and operating frequency f From the plot shown above, the conductor attenuation
factor reduces as the line width increases due to the decrease of line resistance. On the
other hand, the conductor attenuation factor goes up fast as the frequency increases due to
the skin effect increasing the line resistance. Therefore as signal frequency goes high, the
loss can not be neglected. Signal loss is another important limitation for transmission
line length in highspeed application.
3.5 PSPICE Simulation of Transmission Line Signal Delay
The Figure 3.10 gives the delay simulation schematics and segments. Here
simulation is valid for line length (d) and the number of segment (N) satisfying
d/tr
~ N/(p.JLC) (see section 3.2.2).
44
(a)
Figure 3.10 Delay simulation schematics and segment
11 11
(b)
Table 3.3 contains calculation and simulation data of signal delay for a
transmission line with a characteristic impedance of 50n and 75n and Figure 3.11 is
simulation result for different lengths, series tennination resistances and different
characteristic impedances. Figure 3.12 gives out the comparison of calculation and
simulation data for signal delay.
a. Zo=50 ohm, C=1.749Pf/cm, L=4.368nH/cm, R=5.05{}/cm, W=16.85um, t=3.0um, (table 2.I(a», N is
number of segments
Table 3.3a, Calculation and simulation data of signal delay for transmission line
Length N Clump L!ump R1ump Tdclay Tdclay (Sim)
(cm) (pF/cm) (nH/cm) (n) (Cal)(ps) (ps)
0.5 2 0.4372 1.092 1.26 43.7 57.52
1.0 3 0.583 1.456 1.682 87.4 109.78
1.5 4 0.6558 1.638 1.892 131.1 157.2
2.0 5 0.6996 1.747 2.018 174.8 198.54
2.5 7 0.6246 1.56 1.802 218.5 252.46
3.0 8 0.6558 1.638 1.892 262.2 298.5
b. Zo=75 ohm, C=1.128Pf/cm, L=6.338nH/cm, R=13.82{}/cm, W=3.91um, t=3.0um
Table 3.3b
Length N Clwnp L1ump R1ump Tdclay Tdclay (Sim)
(cm) (pF/cm) (nH/cm) (n) (Cal)(ps) (ps)
0.5 2 0.2819 1.584 3.455 42.27 57.8
1.0 3 0.3759 2.113 4.607 84.54 108.6
1.5 4 0.4229 2.377 5.183 126.8 156.8
2.0 5 0.4511 2,535 5.528 169.1 . 208.5
2.5 7 0.4028 2.263 4.936 211.4 247.55
3.0 8 0.4229 2.377 5.183 253.6 295.7
45
!i
•••••.•.•.•..1
!~
I ... ;····... . ...•...............•...•.............•....•..
• .._ L_ to....
• t(nll) .fo('h11 ....,1.)
·.·T·....·.~··
i! 1;
,..: _...•.........._._.._ _ ~ _ _.._,
: j
I I
i 1
;
1
.J...~••. _ ••••••••••;:;;; ••••. .••.•••;:;;.; •••••••  .•.•~:;.;:••••••••• ;~_ •••. __•• ~•.J
• NUlil .<ni11 .~.1'·1
(a) (b)
"·7' .
...•! j ~ .....•...........~•...•..__..._.••.... __....._.~.•........_........._•..._.... ~ .. .._ •._ ,._ "._ 1.
• "1"':'1 . '1""~1 ""In,••
II•• i·" _  _ ,
! I
I!
. I ·t••• ········_·····__••••······•·•·••• ···········_·_.· ._ _ .•••.. _ •••1
• 1._ .,... ,.... 1._ 1._
.ltillt'll ·.l...·' .IolUU,
1\
(c) (d)
Fig. 3.11 Delay Simulation results. a. 2.0=500, cm R.. =450, R.,n=3.530, length =0.5; b. Zo=500,
Rr450, Ron=3.530, length = 3cm; c. 2.0= 750, Rt = 700, Ron=3.530, length =O.5cm; d.
Zo= 750, Rt = 700, Rnn=3.530, length =3cm; where Rt is the series termination resistance of
transmission line.
Fig 3.12 Comparison of calculation and simulation data for signal delay
Comparing the calculation and simulation data, the following conclusion are made:
46
1. The delay of a lossy transmission line is independent of characteristic impedance. It
depends on line inductance and capacitance.
(3.5.1)
In practice, the total inductance and capacitance should include bond wire inductance
and pad capacitance.
2. The delay is linear with line length.
3. The lumped RLC distributed model of the lossy transmission line is accurate enough
to estimate the delay. If more segments are used (select bigger N), estimation will be
more accurate.
4. Comparing gate delay with interconnection delay, as line length becomes larger, the
interconnection delay becomes dominant (much larger than gate delay, >10 times).
3.6 Points of Design
• Check out the possible length range of interconnects and determine if transmission
lines should be used by using risetime specification and possible line lengths (timeof
flight)(t, <2.5tf ). (see section 3.1)
• Select a characteristic impedance which is much larger than output impedance of line
driver to increase signal incidence voltage but not too large avoiding high signal
resistive loss (20 (30.Q.1 00il)) (see section 3.2.1)
• Compare the estimated line resistance and chosen characteristic impedance.
Detennine the type of transmission line, lossless, lossy or fully lossy.
47
• For a lumped RC interconnect, the lumped delay model (equation 3.2.13) is used to
estimate signal delay. For a transmission line, the delay is proportional to Line length
(equation 3.5.1) and a lumped distributed RLC model can be used for simulation.
• Optimal delay is obtained when setting Rtota/ =(l ~ 3)20 (3.2.19). When selecting the
total resistance, termination methods, driver size should be considered (see chapter 4).
• From the chosen characteristic impedance and delay specification, total line
inductance and capacitance can be estimated. Based on equations (3.5.1) and (2.5.2)
(3.6.1)
• When estimating the interconnection delay, the effect of bond wire and input/output
pads must be considered. Make bond wire inductance and pad capacitance as small
as possible. Check out if there is a resonance induced by including the bond wire
inductance at both input and output ends.
• Make sure C d «C/o to achieve parallel termination for lossless transmission !.ine po rne
and open circuit for lossy transmission line (see section 4.1).
• Estimate line resistance and check the quality factor, Q, to make sure the interconnect
being critically damped. If not, make the total resistance larger by increasing either
output impedance of driver, line resistance or termination resistance (series
termination).
• Check the signal risetime using equation (4.2.1). If the risetime doesn't satisfy the
specification, modify line resistance and redesign the line geometry.
48
CHAPTER 4
DESIGN CONSIDERATIONS TO ELIMINATE SELF
GENERATED NOISE
Interconnects not only cause signal delay but also generate noise. The
interconnection noise becomes larger as a result of faster signal risetimes, larger
switching current, longer interconnects and smaller spacing between interconnects.
Certain types of noise, such as crosstalk, that previously were considered only at the
board level become significant in high density and high frequency on chip circuits as well
as in MultiChip Module systems.
Signal reflection, crosstalk and simultaneous switching noise are three important
design issues regarding interconnects. In practice, a real transmission line is of finite
length and the end of the transmission line introduces a discontinuity that may generate
reflection noise. As the circuit density increases, smaller spacing between the
interconnects results in higher crosstalk noise because the capacitive, inductive and
resistive mutual coupling between become more significant. In addition, with large
amounts of current switching simultaneously, the inductive noise associated with power
line also increases, which is known as simultaneous switching noise.
In this chapter, design considerations for reflection noise, crosstalk and
simultaneous switching noise are discussed. The content includes the factors that
contribute to the generation of those noises and the effects of noise on the system
49
perfonnance. The methods of controlling these noises and interconnect driver width
design are also covered in the chapter.
4.1 Reflection Noise
Reflection noise is the noise caused by the discontinuities in a transmission line.
Whenever a change in characteristic impedance occurs, part of the incident
electromagnetic wave is reflected. The reflection coefficient, r, is given out by:
(4.1.1)
where Zo is the characteristic impedance of the transmission line on which the incident
wave travels, and Zioad is the load impedance of the line. If the load is matched to the line
impedance, e.g., Z/oad =Zo' no reflection occurs.
4.1.1 Series Termination
There are a few methods to mitigate the reflection noise. Parallel and senes
tennination are two most usually used methods. The following figure presents the
simplified circuit for both approaches.
R, Z, R, R, z, L D' r l (a) (b)
Fig. 4.1 (a). Parallel tennination; (b). Series termination
50
When comparing these two methods, they have advantages and disadvantages
respectively. Parallel tennination can have several loads (Ci) without creating excessive
reflections and has one half the risetime of a comparable seriestermination line with
same load [2]. However the output with parallel tennination depends on signal loss and
reflection coefficient and its series dc losses costs noise margin. It also results in more
DC power consumption and greater difficulty in selecting the correct terminating resistor
because the parallel loading reduces the characteristic impedance (see section 2.5.2) [15].
For example, assuming Zo =son, RaUl =3.530, RUne =7.5750. and R, =490.,
Vo(DC) =VsR, /(Ron + RUne + RI ) =0.815Vs
There is around 20% loss in DC voltage. This consumes a significant amount of the
noise margin. In order to compensate for the DC loss, Rt can be slightly larger than Zo or
ROlli and RUne should be very small compared to Rt or both. Making R, a little larger than
ideal tennination resistance can obtain small positive reflection coefficient resulting in
improvement of signal first incidence voltage but may limit the hne to one load.
Reducing Rout requires a very large transistor that can eventually contribute to other
problems such as source degeneration and gate resistance limitations for reduced device
operating bandwidth (see chap. 5) Nonnally, the series resistance is limited to 10% of R,
for successful parallel tennination due to DC loss problem. For a parallel tennination
transmission line, a lower characteristic impedance with lower line resistance is
preferred. Only at the end of a parallel tennination line can R, be slightly larger than Zo
to compensate for signal loss.
51
Series termination can overcome the DC loss problem of the parallel termination.
It has no DC IR drop, Vo always get to the correct value "eventually". This also results in
no DC power consumption. This characteristic is useful for CMOS and low power
MCMs. The termination is less sensitive to exact used values of the resistance, the
selection range is limited by the signal ring (resistance is too small) and excessive delay
(resistance is too large). However, it is only suitable for use with single load. It is often
the case on MCMs with CMOS drivers that design of the driver output impedance in
combination with line resistance and termination resistance produces an effective series
termination value. The disadvantage of a series termination includes: the slow risetime
and "secondincidence switching" when multiple loads are on the line. In another word,
far end load switches at t =t d as parallel termination but the near end load switches at
t = 2td rather than at t = a for parallel termination. This problem can be solved using
the parallel fanout with multiple series termination. The number of multiple loads must
be limited by (2~5) [15][1]. Figure 4.2 shows "secondincidence switching" problem and
its solution.
(a) (b)
Fig. 4.2 (a). Secondincidence switching problem of series termination with multiple loads; (b).
Parallel fanout with multiple series termination.
4.1.2 Optimal Value of Termination
52
The selection of parallel or series tennination is detennined by the application. In
brief, for an application with faster signal risetime and multiple loads along the line, such
as critical clock paths, parallel termination is preferred. For an application with
considerable line resistance or driver output impedance (DC loss can not be neglected),
single load and low power consumption, the series termination has better performance.
Reference [2] discusses the design of parallel terminations in detail. In MCMs and large
SOI/SOS VLSI applications, series termination or nontermination is recommended for
long interconnects.
The series termination resistance is often selected to be equal to the characteristic
impedance of transmission line. But Rihini Gupta [28] points out this design is only
optimal for limited cases. R1 equal to Zo will result in overdamping of the signal and
extra delay in the following cases. (1) The line driver has a significant rise/fall time, e.g.,
the channel resistance is considerable compared to Zo, which is normal case for CMOS
driver; (2) The line resistance is large, such as long transmission line; (3) The circuit has
significant capacitive loading.
Variant factors, such as driver channel resistance (driver size), transmission line
resistance, loading capacitance and fanout topologies, have effects on the optimal
termination. For the parallel fanout shown in 4.2(b), the signal reflection coupling by
driver output impedance should be considered. In brief, R, =2 0  NRoUI  RUne' Here N is
the number of parallel lines (limited 25) and every line must have same length and
identical load [2].. Table 4.1 gives out the optimal termination data from simulations
with different line resistance, load capacitance and driver size. Figure 4.3 (a ~ c) are
53
plots of tennination resistance versus line resistance, width and loading capacitance
respectively.
Table.4.1 Series termination simulation data
Rime (0) Rt(O) C10ad (pF) Rt (0) Ron (0) (width(~m» Rt(O)
2.525 54 0.1 52 28.24 (400) 35.5
5.05 51.5 0.5 45 14.12 (800) 40.3
7.575 48.9 1.0 40 7.06 (1600) 45.4
10.1 46.37 1.5 37 3.53 (3200) 49
12.625 43.8 2.0 35 1.765 (6400) 50.6
15.15 41.3 2.5 34
Rl{o/vn) va. aa.;
R1va.lIlno
!II
!+R1(o/vn>! 54
52
~" 'E'"
i .. is'' ;:r
11:. .. ..
'"
'"
CIood(pfl 'oos ..00 71i1'!> 10.1
R1lno(cnrt
(a) (b)
Rl(ohm) va. driver atte
55 .,
1R1(d'm) I
50
1__ Rl(ohm) I
JOL.__ l
.00 fIIOO 1eoo 3200 8400
Driver Wldlh(um)
(c)
Fig. 4.3 The function of termination resistance, R" vs. (a). load capacitance C'O<Ju; (b). line
resistance, R"ne.; and (c). Driver channel resistance, Rout.
a. Figure 4.3a shows the optimal tennination resistance (Rropr) as function of capacitive
load (Cr). The required tennination resistance (Rt) reduces as the load capacitance
increases. Recall section 2.5.1, the load capacitance reduces the value of effective Zo
54
(equation 2.5.4) and lower 20 requires smaller Rr for optimal termination. When
CL < Cline' optimal termination resistance is equal to characteristic impedance, i.g.
R,_OP' =Zo' In addition, as CL increases, the quality factor, Q, reduces. For the same
Q, a smaller Rr is required.
b. 4.3b is the function of Rr.opt versus line resistance (RlinJ. The optimal termination
resistance for a lossy transmission line decreases with the increase of Runc. The
interconnect for MCMs with high frequency signals has a significant line resistance
due to its long length and the skin effect. This has a large effect on signal termination
and delay.
c. 4.3c shows that the termination resistance (Rt) increases as driver size becomes larger.
The driver size contributes to the signal termination by its channel resistance, which
also contributes to signal risetime.
When selecting a series termination resistance, the effective characteristic
impedance of line should be used. The line resistance and driver output impedance
should be subtracted from the ideal seriestermination value (20).
4.1.3 Signal Termination Simulation
A lossy transmission line is divided into several segments as shown in figure 3.10
for simulation. Changing transmission line length, value of tennination resistance,
loading capacitance and driver size, we get the curves shown in figure 4.4 and data in
table 4.1.
~ !r·~·········~····_·_·_·······_········~·_··········· ~._ __._._._ .. ~.;.:. ;::':.''''.;:;t,L;'''9~ VIUI 0111.,...111 T:,..._tl_ I.I~. I
i i
~··"'1 I!iI:i
,.::,.~~lQct~1
!
I i ......_l._ _ ...... _ ..~_ _ 1_. •.1_ •._ ,,; _.(C,.u, •• ICf.I" ...,n.'I, ••In••} ,,::':'1111 .1«_ItI ••In••,)
(a)
!I!
i ............................................................·_··············· _ ••1
.. ...... .... t ....
••'IfU'1i • I ••rd•• 1.1:.1..1) .ICO'''·1 • ~'.::hlO .•IU,I) • I(I'UI"
(b)
55
Fig. 4.4 Simulation wavefonns of series tennination. (a) Optimal tennination with different
transmission line length; (b). Different tennination resistance with fixed line length i.e.
line resistance.
From the simulation waveforms and data, the following conclusions are made:
• Series signal termination is determined not only by series termination resistance but
also line resistance and driver channel resistance.
• The total resistance Rtolal for optimal value for termination is roughly
R,efJ ~ (0.9 ~ 1.5)20
(4.1.2)
(4.1.3)
Figure 4.4(b) shows the simulation results of optimal termination resistance that all
the overshoot or undershoot are less than 10%. R,efJ =(I ~ 1r)20 can also be used in
Rtejf estimation [28]. Here the effective characteristic impedance of line should be
used for 20• Combining equations 4.1.2 and 4.1. 3, optimal termination resistance is
easy to be estimated.
• Too small a termination resistance causes excessIve ringing. The quality factor
should keep small (Figure 4.4b).
(4.1.4)
• The different line geometries will have different termination resistance.
•
•
•
56
The optimal series tennination can be obtained by changing any of followings, line
geometry (Rune), driver size (Ron) and tennination resistance (Rr), separately or
adjusting them together.
The signal selftermination, Rr=O, can also be obtained by designing proper driver
size and line geometry in some cases.
There are also other several topologies of signal termination, such as split parallel
tennination, capacitive tennination, etc. [2].
4.2 Driver Size Design
As noted previously, transmission line driver size is a very important parameter in
interconnection design. Based on the analysis in Chapter 3 and the previous section, it is
known that the driver width has significant effects on signal propagation delay of fully
lossy transmission line and reflection noise control. It is also an important parameter in
the estimation of maximum available line length (see section 3.2.1). The output
impedance of driver is one of the most important factors in detennine the simultaneous
switching noise [1] (see section 4.4). In this section, we discuss how to estimate the
driver size with a known risetime, optimal tennination, fixed line width and length (Rune)
and fixed load capacitance (eL).
4.2.1 Drive Size Estimation Model
57
As we discussed in chapter 3, a transmission line can be modeled as lumped RLC
segments in series and signal delay along line is independent on output impedance of
driver. It is difficult and complex to estimate signal risetime tr using the distributed RLC
model. A simple lumped model is desired to estimate tr and determine the output
impedance of the driver, i.e. driver width, combined with the consideration of driver size
effects on signal termination and reduction of simultaneous noise. Figure 4.5 shows the
model which is used to estimated signal risetime.
Rout Rl R~ne
.A./'I',AM.. .......'VV\n
ClumD~
a
Fig. 4.5 Estimation model of signal risetime
From the above model, equation 4.2.1 is held:
Here, Rt is the termination resistance
(4.2.1)
Rout is the average channel resistance (output impedance) of driver
Rune is the resistance oftransmission line
C'ump is the capacitance of the last segment
CL is the load capacitance
The average channel resistance is
where
(4.2.2)
R _ 1 L
ohmic  K(V  v: )W
GS T
(4.2.3)
(4.2.4)
58
Ronmax is more conservative estimation which is obtained from the current with
maximwn gate and source bias ~ VGsl =VDD. IVDSI =VDD)
w= VDD 1
I]ox v (V _ v: ) Rop,  RUne  R,
t max DD T
ox
(4.2.5)
(4.2.6)
Where Vmax is maximum electron velocity in velocity saturation. Here, it is 1.5.105m / s .
L and W here are transistor channel length and width respectively and Ropt is total optimal
termination resistance. In this section, Ronmax (4.2.5) is used to estimate the driver channel
resistance.
4.2.2 Simulation and Discussion
The circuit schematics shown in figure 4.7 are used to simulate the signal
risetime. Changing the driver size, loading capacitance and transmission line length,
several groups of data are obtained and shown in Table 4.2 and 4.3. Table 4.2 shows the
simulation and calculation data for different drive sizes. Table 4.3 gives out simulation
and calculation data with different line length and loading capacitance for 50n and 750
59
characteristic impedance respectively. Figure 4.6 gIVes out the simulation results of
signal risetime versus (a) transmission line length and (b) driver size.
..•, _._ __ _..........•................__ _ :
~ l()oSO .... AttS oM. 0.0 I"'. ~, S3 i
: Ir'flvl 91gnel :
; l.ftQ',....lOCa ;
1 1""9''''1:;11''''' c.c. ~
1 f
"1 1
I !
: I . l
: ! ~. . •... _.0," .••.... _ ...•.....••..•_•..•• _. _._ ......•...• __ ••..•... "r ••• o' ... e." ...... 1.'
.. 1(I1:U ••~C11!J") • <It'll:' 1«t':I) n.
(a)
•••,._ ••••••••••••••••••••••••••• _ •••••••__•••••••••__ •••••_ •• .4 ••••••• _ •••••••••• _ ••• i "'""" ..........'0....... :
~ Vl;~!
,.•~:. "'ll~eoo. 1
"'l"'~ ;: !i
i
1! .i. "1 I
i !
i ! •.•........................__._. __.............•..................., !
IHfto ... 1iS_ ...... ... ....
.'(C":II ·It(P:J) • ...:11 .. IJU'::" .IJ,II'1rtl
Ol.
(b)
Fig. 4.6 The simulation results of signal risetirne (a) Risetirne ys. transmission line length
and (b) Risetirne vs. driver size.
(a)
i1 1I
<E>>'Ml.8l1JY1.~
655W
(b)
Figure 4.7 Risetime simulation schematics and segment
Table 4.2 The effect of driver width on signal risetime
Zo=5012, Length=3cm, C1oad=O.lpF
Width 400um 800um 1600um 3200um 6400um
Rout(12) 28.24 14.12 7.06 3.53 1.765
Trise(pS) (CAL) 131.97 118.49 111.75 105.88 102.95
Trise(PS) (81M) 116.47 108.26 104.79 102.89 102.58
60
Table 4.3 Risetirne calculation and simulation data with different line lengths
(a) Zo=75 ohm, C=1.128Pf/cm, L=6.338nHJcm, R=13.82nJcm, W=3.91um, t=3.Oum
Tennination Resistance R. = 70n, Cl =O.OlpF and Cl =O.lpF
Length (cm) C1urrq> (pF/cm) Rune (n)
. 0.5 0.2819 6.91
1.0 0.3759 13.82
1.5 0.4229 20.73
2.0 0.4511 27.64
2.5 0.4028 34.55
3.0 0.4229 41.46
True(Cal)(p Trise(Sim) Trise(Cal)(ps) Trise(Sim) Trise (Cal)(ps) Trise(Sim)
s)R. = 70n, (ps) R. = 70n, CL (ps) R. = 35n, CL (ps)
CL =O.OlpF =O.lpF =O.lpF
51.65 43.36 67.58 52.38 38.1 36.5
74.16 68.25 91.45 80.53 54.8 52.4
89.77 82.59 108.43 91.76 68.14 64.77
102.6 91.72 122.6 99.72 80.2 74.3
104.15 95.65 119.55 103.58 80.8 74.97
109.5 104.01 132.28 113.67 92.02 90.26
(b) Zo=50 olun, C=1.749Pflem, L=4.368nHJcm, R=5.05Q/cm, W=16.85um, t=3.0um
Length (em) Clump (pF/cm) Rline (0)
0.5 0.4372 2.525
1.0 0.583 5.05
1.5 0.6558 7.575
2.0 0.6996 10.1
2.5 0.6246 12.625
3.0 0.6558 15.15
Trise (Cal)(ps) Trise(Sim) Trise (Cal)(ps) Trne(Sim) Trise(Cal) (ps) Trise(Sim)(
Rt = 450, CL (ps) ~ = 450, CL (ps) R, = 250, CL ps)
=O.OlpF =O.lpF =O.lpF
50.23 43.9 60.33 50.45 38.28 36.7
69.9 62.62 80.5 72.05 58.4 50.4
82.18 79.24 93.29 83.57 68.83 60.03
91.52 92.33 103.1 96.68 77.37 67.95
85.38 82.89 97.49 90.25 75.28 65.6
93.27 92.93 105.88 98.96 81.71 72.6
Comparing the simulation and calculation data, figure 4.8 and 4.9 give insight
into the parameter effects on risetime. Figure 4.8(a) and (b) are risetime versus line
length curves for different load capacitance (CL ) and termination series resistance (Rt) for
61
SOO and 7S0 characteristic impedances respectively. Figure 4.9 shows the calculation
and simulation data curves of risetime versus driver size with Za=5OQ, CL=O.lpF and
R,=450.
~,, ..,.,. .
. 
~ IllI==:;~::~:~;;;~~=:j l Il
j ~I'~:::..._I~.._ ._
R....~
:Ilf"~_ ..
~ o.
12>1 :::...."'_1
..'"
'(Ilt:::::=:::~~:::::::::i;"~j t ~t;,~~"""==;:~==:::J7":<::::::"'"j
~ 1IJl:r~~"..:.<~;:_~.:::::"i_W'.i..i.i.;ia_;_~
~ Cl.~""':::"'__\~===
2l.~__\=_~=_:===:
~......,.,~'"
(a) (b)
Figure 4.8. Risetime comparison between calculation and simulation. (a)Z0=500 and (b)
Z0=750, with different load capacitance, termination resistance and line width
140, ,
100 ~..........:====I*F==...
a::o 16ll 3m
llM!' Vtt(lS!1
Fig. 4.9 Risetime comparison between calculation and simulation with different driver size
Based on the above analysis and simulation results, the following observations are
obtained:
62
1. The model of Figure 4.5 is good enough to estimate the driver size with the largest
error being less than 15%. The channel resistance of driver has effect on the signal
risetime combined with line resistance and load capacitance. For fixed line geometry
and load, model in figure 4.5 can be used for driver width estimation.
2. The error between calculation and simulation is due to the estimation of the ROllI. Roul
is estimated in the velocity saturation region. This is the more conservative
estimation so that the calculation values are larger than those obtained from the
simulation (see Dr. Johnson's notes).
3. The shorter the line, the larger the estimation error. For shorter line, line resistance is
smaller so the Roul has more effect on the calculation result.
4. From the figure 4.9, the same conclusion can be obtained. The smaller the driver
width, the larger the channel resistance, so the larger error ofthe.
5. The channel Resistance of the driver also has effect on the termination and the delay
of signal (see section 3.2.3 and .41.2).
6. This model supplies a simple estimation of driver size for the engineer. Transmission
line driver design is related to many complex factors. The driving ability and
transient switching noise are two main considerations. With fixed line length, loading
capacitance, optimal termination resistance and decoupling capacitance, the model in
Figure 4.6 is a quick and easy method for estimating driver size.
4.3 Crosstalk
63
VLSI interconnects become one of the important limitation factors oftoday's high
speed and high density circuits performances with the advent of deepsubmicron
technologies and subnano second switching circuits. As chip dimensions and clock
frequency increase, the wavelength of signals become comparable to interconnection
length and this makes interconnects better "antennas" [1]. Mutual capacitance and
inductance induce unwanted electrical coupling known as crosstalk noise on neighboring
wires. Whenever a signal edge travels along a signal trace, bond wire and connector lead,
both a forward and a backward noise pulses are generated. Crosstalk is one of the most
critical noises between interconnect wires of highspeed and highdensity circuits.
Several authors [9][ 14] offered experimental simulation results and concluded that
crosstalk is dependent on substrate material, buffer size, termination resistance,
interconnect line length and spacing between the lines. C.T. Chang and G.A. Garcia
suggested that coplanar waveguides are much better than two parallel microstrips built on
the same substrate [29]. In this chapter, capacitive crosstalk of both microstrips and
coplanar waveguides are discussed and the simulation results of crosstalk versus line
space, termination resistance, drive size and line length are given.
4.3.1 Calculation of Crosstalk
Microstrips and coplanar waveguides are the primary interconnect structures for
very highspeed integrated circuits. Compared to other kinds of interconnections,
coplanar waveguides are easier to connect to shunt circuit elements and maintains the
same characteristic impedance when its dimensions are scaled. These advantages are due
64
to signal and ground conductors of coplanar waveguides being located on the same side
of insulating substrate. Figure 4.10 shows the crosssections of microstrips and coplanar
waveguides.
Signal Signal
GNO Signal GND Trace Signal GND
¥
w
(a)
w
(b)
w
Fig. 4.10 Crosssections of (a) coplanar waveguides; (b) microstrips
Where w is transmission line width, s is the space between the signal and ground trace.
Wg is ground trace width. For microstrips, s is the space between two signal traces.
The method of conformal mapping and an elliptical transformation are used by
C.T. Chang et. al [29] and Y.C. Lim et. al (30] to calculate the capacitive coupling
between two coplanar waveguides. The method of confonnal mapping converts the
planar geometry of coplanar waveguides to the geometries of parallel plate transmission
line. More physical insight than original planar geometry is provided and approximation
of capacitive coupling is allowed by conformal mapping. The elliptic integrals are
reduced to simplified forms. In brief, the elliptical integral transformation used here is
defined as:
<1> dO
F(a, et» = Jr====
o Jl sin 2 a sin 2 0
where a for this application is
a =arcsin( W )
w+2s
(4.3.1)
(4.3.2)
65
so the mapping parallel plate transmission line width is given by:
6w = F[a, arcsin W + 2s JF[a, arcsin__W_+_2_S
__)
w+4s+2wg . 3w+4w+2wg
(4.3.3)
The electrical field lines originate from one signal trace and tenninate at another
neighboring one by the paths through the underlying substrate and the above free space.
The two capacitance in parallel are taken into account by using the dielectric constant
(&r + 1)&0 which is equivalent to 2(&r +1)&0 /2 being the effective dielectric constant
and factor representing two capacitance in parallel [30]. The coupling capacitance per
unit is given by:
~W
6C =1.5(&eff +1)&0 !ld
. w+2s . w+2s
F(a, arcsm )  F(a, arcsm )
w+ 4s + 2w 3w+4s+ 2w
= 1.5(&eff +1)&0 g g
F(tr a tr)
2 '2
(4.3.4)
F(~  a, ~) is the mappmg spacmg between two signal traces and 1.5 is the
approximate correcting factor for the end effect at the edge of the signal trace. The total
coupling capacitance is given by:
CcOupling =6C, d (4.3.5)
Figure 4.11 shows a simple circuit model for capacitive crosstalk between two
coplanar waveguides. Here coupling capacitance is treated as lumped capacitor between
two terminated transmission lines with characteristic impedance Zoo
66
Zo v
1I 1 z. J C
_ ••'"
~ V'2
Fig 4.11 Circuit model for crosstalk due to capacitive coupling.
Based on the circuit model, the following formula is held:
(4.3.6)
Solving for crosstalk, and the real part of V/2 is
and
(4.3.7)
(4.3.8)
M
Fig. 4.12 Capacitive crosstalk of coplanar waveguides versus ground line width and signal
frequency.
Figure 4.12 gives out the capacitive crosstalk changes versus ground trace width
and signal frequency. Note the axis of ground line width and signal frequency are
67
already nonnalized. It shows the coupling crosstalk reduces as ground separation trace
width increases but increases as signal frequency increases. More detail discussion will
be given in the next section.
4.3.2 Simulation of Crosstalk
The capacitive crosstalk simulation schematic is shown in figure 4.13(a). In this
simulation, the transmission lines are modeled by series lumped RLC segments and each
segment has same equivalent parameters. The values of R, L, C for different line lengths
are different. The peak values of crosstalk at the "far end" and "near end" are measured
respectively. Figure 4.13(b) shows one sample of simulation wavefonn and measured
values.
$"'"T.     ,            _••     1
, <4,0i2 mV i
I
s. 1;::,:;;;.~':;. ,.;;,.~_;,;,~;:;;;J
• U(CL'2':2) _ U(illI2:2)
(b)
68
Fig. 4.13 Capacitive Crosstalk Simulation; (a) Simulation Schematic; (b) One sample simulation
waveform.
4.3.2.1 The Accuracy ofMathematical Model
To check the accuracy of the mathematical model, transmission lines with
different line lengths are used. Because of differences in line length the lumped RLC
parameters of segments are different, however the total line capacitance, inductance and
resistance are linearly scaled. For observation convenience, the coupling capacitance is
kept the same for different line lengths by changing the spacing (inserted ground trace
width, wg , figure 4.10). The longer the line, the larger the spacing. Table 4.4 contains
calculation and simulation data of transmission lines with six different line lengths.
Table 4.4 Calculation and simulation data for mathematical model accuracy
Length N wg(um) C(wg) Cctotal(wg) Celu mp TNcross TNcro..(mV) TNcross(rnV)
(ern) (pF/ern) (tF) (iF) (mV)(Cal) (Sim)(Near (Sim)(Far
End) End)
0.5 2 110.8 0.6373 3.186 1.593 2.503 2.71 4.02
1.0 3 167.2 0.3169 3.169 1.056 2.489 2.55 3.9
1.5 4 210.0 0.2117 3.176 0.794 2.494 2.75 3.99
2.0 5 245.7 0.1595 3.19 0.638 2.505 2.24 3.73
2.5 7 278.0 0.1272 3.181 0.454 2.5 2.36 3.42
3.0 8 306.85 0.1061 3.182 0.398 2.499 2.21 3.55
Where wg is the width of inserted ground trace (GND trace); C(wg) is self
capacitance ofGND trace; CClolaJ and Ccfump are coupling capacitance for total line and per
lump respectively. Note: The total coupling capacitance is roughly the same because the
total crosstalk noise TNcross is setup to be the same (60dB).
Here Zo=50ohm, C=1.749Pf/cm, L=4.368nH/cm, R=5.05.Q/cm, w=16.85um,
s=4.21um, t=3.0um and N is the number of segments.
69
Croutall Comparison 1141tw. 81m. & ell
"
.... •
4.14 Crosstalk comparison between simulation and calculation data
Figure 4.14 shows the comparison between the simulation and calculation data.
The near end crosstalk data is much closer to the calculation data. As H.W. John and M.
Graham (2] pointed out the forward crosstalk is proportional to the derivative of input
signal and each coupling capacitance and inductance. Since the forward crosstalk arrives
at the far end of line simultaneously, the total forward crosstalk is proportional to the total
coupling capacitance and is cumulative. In our simulation, the crosstalk is doubled at far
end because of opencircuit load. The reverse coupling is different. Even though the
total coupling capacitance is same as forward crosstalk but the reverse crosstalk spread
over the round trip transmission line delay and the value is not cumulative. After a round
trip delay, the far end crosstalk reflects back to near end. So the far end crosstalk is
larger due to opencircuit reflection. Based on the data in table 4.4 and figure 4.14, this
model is accurate enough to estimate the crosstalk and only the far end crosstalk is
valuable.
4.3.2.2 Crosstalk vs. Spacing between Two Signal Lines
70
Table 4.5 gives out the simulation and calculation data with different spacing
between two signal lines. 3.0cm and i.5cm long lines are used. The signal line
geometries are same as those used in previous section (recall table 2.1). Figure 4.15
shows the comparison result of simulation and calculation data, where Zo=50.a, L=3.0cm
and i.5cm, Rt=42Q, CL=O.lpF
Table 4.5. Simulation and calculation data of crosstalk vs. spacing
Space( Crosstalk Crosstalk Crosstalk Crosstalk
/lm) (mV, Cal., 3cm) (mV, Sim., 3cm) (mV, Cal., 1.5cm) (mV, Sim., 1.5cm)
100 17.75 18.99 8,874 8.41
200 5.443 5.214 2.721 2.56
300 2.605 2.69 1.303 1.44
400 1.523 1.43 0.762 0.73
500 0.998 0.914 0.499 0.485
~un)
Fig. 4.15. Capacitive crosstalk: vs. spacing of two signal lines.
... ..
S'"
.5.u
:!! !! .. l! • o •
~....___.mi. ""'i
 ••• ·~trN.3cml
.)lW(CIlrtfl, 1~
__..srn.fItfJ,1.5crrf
...
It is easily observed that the calculation data is very close to simulation results.
The model given by equations 4.3.4 and 4.3.6 is accurate enough to predict the capacitive
coupling for coplanar waveguides. The following observation cab be made:
• The capacitive coupling crosstalk decreases fast as the spacing of two signal lines
increases. Here the spacing is the ground trace width. The importance of ground
separation trace will be further discussed in section 4.3.2.7. The ratio of the spacing
(GND trace width) vs. signal line width depends on line length and required noise
.,
~.
J,.
d
71
margm. For example, in the above simulation case, a 3cm long signal line with 16fJJn
width required 350pm to obtain 60dB crosstalk (2.5mv); a 1.5cm length line requires
only 220fJJn to achieve the same crosstalk.
• Crosstalk reduction "saturates" as the spacing becomes larger. In the above
simulation condition, when the space is larger than 500fJJn, the crosstalk will not be
reduced more and crosstalk difference between lines with various lengths becomes
very small. This infonnation implies we can set up a spacing point for different line
lengths to achieve minimum crosstalk and here it is around 25~30 times of signal
trace width. This point can be found through the PSPICE simulation.
4.3.2.3 Crosstalk vs. Termination Resistance
The series termination resistance has an effect on the crosstalk. S. Seki and H.
Hasegawa [33] pointed out that the floating interconnection has larger crosstalk
amplitude and as the termination resistance is reduced, the lumped RLC oscillation
becomes dominant and detennines the crosstalk amplitude (see section 4.1). As
termination resistance R1 increases, the RLC oscillation reduces resulting reduced
crosstalk. However too large a termination resistance will contribute to additional signal
delay, more signal loss and larger risetime (see chapter 3 and section 4.1 and 4.2). Table
4.6 and figure 4.16 give the simulation data and curve of 1.5cm and 3.0cm long
transmission lines and confinn the crosstalk change trend discussed above.
d
72
Table 4.6 Simulation data ofcrosstalk ys. termination resistance R,
Rt(O) Xtalk(mV, 3cm) Xtalk(mV, 1.5cm)
10 6.1 5.35
30 3.16 2.96
45 2.32 1.82
70 1.928 1.42
90 1.67 1.27
Where 20=50[2, Length =3. Oem and 1.5cm, CL=O.lpF
Crosstalk vs. Rl
__X'l/lolntll.3cnt
__XII/il(ntlI. Uon1
~ • » m
Termination At.l.tance Rl(ohm)
Fig 4.16 Crosstalk YS. termination resistance
As the termination resistance increases, capacitive coupling crosstalk reduces and
the change becomes slowly for large tennination resistance. There is a tradeoff in the
selection of tennination resistance between signal perfonnance (signal delay, integrity
and risetime) and noise control (reflection and crosstalk noise).
4.3.2.4 Crosstalk vs. Transmission Line Driver Size
By changing driver size and keeping the other parameters (signal line geometry,
spacing and termination resistance, etc.) unchanged, the crosstalk simu~ation data is
obtained. Table 4.7 and figure 4.16 shows the corresponding data and curves with line
length equal 3.0em and 1.5cm respectively. Here 20=50.Q, Length=3.0em and J.5em,
Rt=42[2, CL=O.lpF and driver size is changed from 400J.lnl to 6400J.lnl.
d
73
Table 4.7 Simulation data of crosstalk vs. driver size
DriverSize(um) Xtalk(mV, 3cm) Xtalk(mV,1.5cm)
400 2.28 1.53
800 2.57 1.64
1600 2.61 1.71
3200 2.70 1.73
6400 2.68 1.8
Crosstalk VS. Dlrver Size
• • • 2.5 ... :> 2
E~ • • • • 19 1 .5 .
III
III
.0.. 1
0
0.5 I_XlllIk(mv.3ClnI
_XlllIk(mv.1.5cm)
400 aDD 1600 32<10 6400
Driver Slze(um)
Fig. 4.17 Crosstalk vs. driver size
From the data in table 4.7 and the curves shown in figure 4.17, the following
conclusions are made:
• Driver size has little effect on the crosstalk because the signal risetime is dominated
by both tennination resistance R( and line resistance RUne. Recall the data of risetime
model in section 4.2, we can find the risetime data ranges from 116.5 ps to 102.6 ps
as the driver size changes from 400j.irn to 6400 f.ll1l, a variation less than 10%.
• Faster signal risetime increases crosstalk. From the Fig. 4.15, we can see that smaller
drivers with larger risetime have reduced crosstalk. The signal risetime is preferred to
be close to the required specification as slow as possible.
4.3.2.5 Crosstalk vs. Transmission Line Length
74
Changing the coplanar waveguide length and keep the inserted ground trace width
fixed (300pm), Table 4.8 and figure 4.18 give the simulation and calculation data and
comparison curves. Here Zo=50n, line length changed from O.5cm to 3.0cm, R,=42Q,
CL=O.lpF and driver width equals 3200pm (pFE1).
Table 4.8 Simulation and calculation data of crosstalk vs. different line length
Length(c Xtalk(mV) Xtalk(dB) Xtalk(mV) Xtalk(dB)
m) (Cal. (Cal. (Sim. (Sim.
Wg=300um) Wg=300um) wg=300um) wg=300urn)
0.5 0.434 75.2 0.75 70.46
1.0 0.868 69.19 1.18 66.52
1.5 1.303 65.66 1.77 63.00
2.0 1.737 63.16 2.14 61.35
2.5 2.17 61.23 2.52 59.93
3.0 2.605 59.64 2.76 59.14
.. ,
U"u..llilC~
Crollllik VI. Une Length
>' ' •1..
t
<3,
"
Fig. 4.18 Crosstalk vs. line length.
As the line length increases, the crosstalk and the coupling capacitance increases
linearly as equation 4.3.4 indicates. For longer signal traces, larger spacing is required to
maintain lower crosstalk.
4.3.2.6 Comparison of Coplanar Waveguides and Adjacent Microstrips
75
The ground between two signal lines plays very important role in the shielding of
crosstalk noise (recall figure 4.10). Using the same model for coplanar waveguides,
which has separating ground trace between two signal lines, and two adjacent microstrips
without separating ground trace i.e. wg = 0, the spacing data with same crosstalk in two
cases are obtained and shown in table 4.9, and figure 4.19 shows the comparison results.
Table 4.9 Crosstalk simulation data for waveguides with separating GND trace and adjacent
microstrip lines without separating GND trace.
Xtalk(dB) 30 35 40 45 50 55 60 65 70 75 80
Space(llm, 43.72 63.01 88.95 123.7 170.2 232.3 315.2 425.8 573.3 770 1032
withGND)
Space(JlID, 76.23 141.8 258.4 466 835.2 1492 2659 4735
without
GND) I
em
t5:D _
!IXllr.====:=:=::=::::;;i .." +~"'<Nl'"
 ~  !
+~.aJOO
E:IID ..
'i:m)
am> <IJ
Fig. 4.19 Effect ofGND trace on crosstalk
• GND separation is very helpful on crosstalk reduction. The coplanar waveguides
have much less crosstalk than two parallel microstrips with same spacing. The
coplanar waveguides can save wiring space over parallel microstrips
•
76
Crosstalk reduces as the width of GND separation between two signal traces
increases. The width ofground trace depends on line geometry and required crosstalk
. .
nOise margm.
• Improvement in crosstalk approaches zero as the GND width increases, e.g. for 50
ohm, 3cm coplanar waveguide, there is no further improvement when GND width
>500um (a wg jw ratio is about 25~30). This point can be estimated by using the
illustrated model for the worst case (maximum line length, minimum crosstalk margin
or fastest signal risetime). More accurate estimation can be obtained by simulation.
4.3.3 Discussion and Reduction of Crosstalk
a. From the model used for analysis, the crosstalk is contributed by the mutual coupling
capacitance. This model is more accurate for low frequency. For high frequency, the
effect of magnetic coupling (the inductive coupling) will play a dominant role in
determining the crosstalk. The inductive coupling decreases slowly as the spacing
between two signal lines increases because the magnetic field reduces slowly along
the substrate and it can not be shielded. H.T. Yuan, et. al [14] presents the capacitive
and inductive coupling data which indicated that the mutual capacitance reduces by a
factor five when the spacing between two lines increases eight times, but mutual
inductance just reduces 30 percent. Therefore, inductive coupling will become more
troublesome than capacitive coupling in high speed application.
b. The coupling capacitance and coplanar waveguide (CPW) characteristic impedance
are not dependent on the absolute dimensions of CPW. They are dependent on the
....
77
relative dimensions, W, s and wg• When these parameters are scaled, the coupling
capacitance per unit length will remain constant [29].
c. The transmission line length, spacing between two lines, termination and output
driver size (the risetime of the signal) have large and complex effects on crosstalk. In
the above sections, we discussed these effects respectively. Brief conclusions are
summarized as follows:
1. Longer signal lines, larger the crosstalk.
2. Larger termination resistance, less crosstalk.
3. Higher frequency signals have larger crosstalk than lower frequency signals for
identical geometries.
4. Driver size has little effect on crosstalk.
5. A GND separation trace reduces crosstalk effectively.
6. Substrate thickness and line load also has measurable effects on crosstalk [33].
7. RLC oscillation increases the crosstalk.
d. The crosstalk can be reduced by
1. Using a ground trace between two adjacent signal traces. The ground trace width
is determined by signal line geometry and crosstalk noise margin.
2. Increasing the spacing between two adjacent signal lines.
3. Avoiding routing parallel signal lines especially sensitive signals.
4. Using largest the termination resistance as possible.
5. Using the shortest line as possible.
6. Full shielding can be used for some ultrasensitive signal line [15].
7. Choosing the smallest driver possible.
cd
78
8. Using the transmission line with larger line resistance.
9. Reducing the substrate thickness to reduce inductive coupling.
10. Using a shielded multi interconnection scheme [33].
4.4 Simultaneous Switching Noise (Ground Bounce)
In large die SOl/SOS or MCMs system, as device geometry is scaled down, the
number of devices (gates) integrated in one system has increased enormously. This
results in increased switching current. In a highspeed digital system, large output drivers
are used to improve the switch speed and drive ability. The increase of a driver's width
increases the switching current that flows in and out the chips through power supply and
ground pins. Since the drivers drive not only the chips but also the interconnects, the
substrate to package wire bond and the package parasitics and all these components have
inductance, current and ground bounce swing can be significant. The change of current,
which is primarily due to the charging and discharging of parasitic capacitance, causes a
voltage drop (!1v =L dI/dt) across the parasitic inductance. This kind of noise is
referred as simultaneous switching noise (ground bounce). For constant field scaling,
both switching current I and speed tr scale down by factor a but parasitic inductance L
doesn't scale down resulting Ltv unchanged. Since Vdd scales down, therrefore ground
bounce consumes more noise margin, i.e. !1v/Vlid increases. To reduce Ltv, parasitic
inductance L should be scaled down but this is not effective because inductance changes
as a logarithm function of line geometry. In SOl/SOS application, ground bounce
becomes worse because the well to bulk capacitance, which works as temporary current
st1
79
source when device switches, has been eliminated. If ground bounce is too large, it will
cause logic errors.
Ground bounce is a very complex phenomenon in integrated circuits. The reasons
are: (1) ground bounce is typically not significant unless large number of gates or drivers
switch simultaneously; (2) ground bounce happening in different system sections can
interact by sharing the same power/ground traces; (3) the enormous number of transistors
in a system make it difficult to estimate switching capacitance accurately; (4) the short
circuit current, as well as charging and discharging current, has an effect in determining
ground bounce.
Controlling ground bounce becomes a more important design issue and has
received much more attention in high speed and high pin count VLSI design. Previous
work has used simple lumped element circuit models to discuss the properties of ground
bounce [34][35]. A transmission line model is also used by Senthinathan [36] to describe
the propagation of ground bounce along multichip module interconnects. In this study, a
simple equivalent lumped circuit model is assumed.
Several techniques are used to control ground bounce. The decoupling
capacitance is placed as close as possible to the chip (gates) in order to serve as
temporary source of current to maintain a constant DC power supply. Damped
power/ground traces due to proper trace geometry and driver width design are helpful in
reducing ground bounce [9][37][38]. In addition, evenly distribution circuitry among
many power/ground pins are preferred [34]. The following sections set up the model for
simultaneous switching noise analysis and its equivalent RLC circuit. Finally the
simulation results and methods to reduce the ground bounce are discussed.
cd
80
4.4.1 Analysis of Simultaneous Switching Noise (Ground Bounce)
Figure 4.20 presents (a) an approximate model of the switching circuit with
parasitic inductance, (b) a equivalent analysis circuit and (c) equivalent input voltage and
switching current waveform. In order to simplify the analysis, we use a onesided
equivalent circuit with parasitic parameters of the power supply trace and consider the
transient switch from 0 ~ 1. The behavior of the ground trace is identical to the power
supply trace when the signal switches from 1 ~ O. The switching current is modeled as
triangle to approximate the real current waveform.
CIRCUIT
CO""
L.~
(a)
(b)
t
JLAJuL .:~t,:. .::
(c)
Fig. 4.20, Equivalent circuit and switching current model
In (a) an onchip circuit core and off chip driver use separated power supplies and
grounds to reduce interaction. The behavior of ground bounce in both sections is
st1
81
identical and can be represented by the simplified circuit model in (b). In (b). Ltot is the
total inductance including trace and package parasitic inductance (power and ground
pins). RIOt is total resistance of power supply system. CD is the inserted decoupling
capacitance and CDVc(O) represents its initial condition. When a signal switches from
o~ 1. the capacitor CD'S initial condition is Vdd. Isw(s) is the equivalent switching
current shown in (c). The shape of switching current depends on driver ability (size) and
the risetime /falltime of input signal. Here we assume signal risetime and falltime are
equal. tr is the switching time, f is the signal frequency and I max is the maximum
switching current. In the following analysis, only the rising edge is considered to
simplify the analysis.
Writing the node equation of Vx(s), the following equation is held:
(4.4.1)
Solving for Vx(s):
V ( ~R) [s+R~J
M s+ L
V (s) = L,O
' + _1_ 2 101 IJw(s)
J: ( s+RiolJ2 +( 1 Riot22] CD (S +Rto/ ) +(1 Rrot22]
2Ltol Lto/CD 4L/ol 2Llo/ LlotCD 4Ltot
(4.4.2)
let
R
a=~;
2Ltot (
2 ]1/2
fJ 1 ~
 Ltot CD 4Llo/2
(4.4.3)
substituting equation (4.4.3) into (4.4.2), (4.4.2) is simplified
d
82
V() _Vdd (s+2a) 1 (s+2a)
s  + 1 (s)
x (s+a)2 +132 CD (s+a)2 + 132 sw
(4.4.4)
From (c) in fig. 4.20, the switching current at one rising edge can be expressed as:
The close Conn of Vx(t) is unnecessarily complicated to solve. Here we use a
(4.4.7)
(4.4.5)
(4.4.6)
and dV =Vdd , dt =t r
1 (s)21=~1 ( 12e~2s +eI,s J
sW t 2
r S
1 =C dV.
L dt '
Considering switching current, we have:
Now Substituting it in (4.4.4)
Taylor series to approximate the second tenn in (4.4.7), so
Equation (4.4.8) presents an estimate of ground bounce. It can be readily
observed that the first component of interests is an oscillation with a decaying magnitude.
The oscillation frequency OJo and decay factor a are given by (4.4.3). For fast decay of
oscillation, damped power traces are required. The second tenn of (4.4.7) can be thought
as the initial offset of oscillation. Because a Taylor Series is used and only low order
tenns are kept to simplify the expression, the equation may introduce errors. Examining
(4.4.8), it is desired this offset is very small and as a result the ratio of CL / CD should be
cd
83
very large, Le. CD» CL · Note, because only signal edge is considered, t is limited,
t < 1/(2f). For a more accurate estimation, simulation is required.
4.4.2 Fonning Damped RLC Equivalent Circuit of Power Trace
The inductance and resistance of power supply traces, load capacitance, and
driver tumon resistance fonn an equivalent RLC circuit. It may oscillate if it is not
damped and the oscillation also induces simultaneous noise to the system. The
equivalent RLC and simplified circuit are given by T. Gabara [37][38] and shown in
figure 4.21. For more accurate analysis, further investigation is required for equivalent
RLC circuit.
R,.,
L,.
Fiiure 4.21 Equivalent RLe circuit for power supply system
In figure 4.21, LtGt, Ctot and Rtot are total effective inductance, capacitance and
resistance respectively. In a MCMs or SOI/SOS large die application, we assume there
are a total ofK power supply and ground pins. Note, in order to simplify the analysis, we
assume (a) every power or ground pin has an identical inductance and the inductance of
all bond wires is much larger than total pad inductance allowing pad inductance to be
d
&4
neglected; and (b) decoupling capacitance is much larger than load capacitance. The total
resistance, capacitance and inductance are given:
Lgrd
Ltol =LUn £' +
K
(4.4.9)
(4.4.10)
(4.4.11)
In the above equations, Lline and RUne are total inductance and resistance of power
supply and ground traces. CD is the total decoupling capacitance. Ron is total effective
tumon resistance of the switched gates/drivers. The value of L,ot• CIOI and RIot will
slower due to the increased resistance and capacitance and the design concern becomes
happens and ground bounce decays faster. However, the response of signal becomes
(4.4. 12b)
critically or overdamped (4.4.12a)
Resistive damping techniques to reduce the switching noise have been studied
critical or over damped condition is given by:
determine whether an oscillation will be generated at the power/ground nodes. The
the delay of switching. When total resistance or capacitance is reduced and condition
[37] [3 8]. If the equivalent RLC circuit is either critically or overdamped, no oscillation
(4.4.12a) is not satisfied, the equivalent RLC circuit exhibits oscillatory behavior
resulting in ground bounce. This also can be observed in the simulation waveform
(4.23d). The design issue becomes how not to tradeoff the switching delay or driver
delay and avoid the switching noise. Overdamping of the equivalent circuit can be
obtained by the proper design of power traces, driver size and proper number of power
d
85
pms. The power pin inductance plays the dominant inductance role in ground bounce..
The limited number of physical I/O pins makes reducing pin inductance difficult. In
many cases, power and ground leads can consume up to 30'Y040% of the total I/O pins to
ensure a low inductance path. In summary, the total capacitance can be increased by
inserting more decoupling capacitance and the smallest driver possible while satisfying
the risetime specification. The Simulation result (4.23e) are in agreement with the
analysis.
4.4.3 Simulation of Ground Bounce
r.JL~~..........;.;;;;..."::4'
r..
(a)
··l···....···················..·····..····..··......··......_·.._····......·..··········1
! 1
i j
'1t1II<
Ii .....L. ••. 1 _ __:
.IC.") 'III(U' •• 'II'''1
(b)
Fig. 4.22 Ground bounce simulation circuit and typical response
Figure 4.22 shows the simulation circuit and typical ground bounce response. In
the simulation, we just observe the ground bounce on power supply. The observed
bounce on ground trace is exactly similar as that on power supply. Two inverters are
used here for simplicity. One (2nd
) works as switching driver and the other buffers ideal
pulse to ensure a worst case but realistic clock edge into 2nd inverter. Those two inverters
have different power supplies to isolate switching current. Line inductance and
86
resistance data is taken from table 2.1. CL represents the total equivalent switching
capacitive loads.
The following simulations have been done to observe the effective changing
current and ground bounce by changing parameters.
(a). Load capacitance is changed but the other parameters are kept constant. Here
CL=lpF, lOpF and SOpF; CD=100pF; Lline=SnH; Rune=S.Q; Driver Width W=3200j1Jn.
The measured ground bounce an